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authorSwati Sharma <swati2.sharma@intel.com>2022-06-30 13:15:11 +0300
committerJuha-Pekka Heikkila <juhapekka.heikkila@gmail.com>2022-07-01 12:41:09 +0300
commit01f75333df0d27768ef987653ab49c3a1223ce3d (patch)
tree0b709a2a9299fa87931d72f217851642998340ef
parent6f242a33955e948d4ea256ec111d214ee8331b7f (diff)
tests/i915/kms_flip_scaled_crc: Add new tests covering modifiers and pixel-formats
New test cases are added covering various modifiers and pixel-formats. v2: fixed typo Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
-rw-r--r--tests/i915/kms_flip_scaled_crc.c258
1 files changed, 257 insertions, 1 deletions
diff --git a/tests/i915/kms_flip_scaled_crc.c b/tests/i915/kms_flip_scaled_crc.c
index d6edb01c..88640da2 100644
--- a/tests/i915/kms_flip_scaled_crc.c
+++ b/tests/i915/kms_flip_scaled_crc.c
@@ -58,6 +58,38 @@ const struct {
2.0,
},
{
+ "flip-32bpp-yftile-to-64bpp-yftile-downscaling",
+ "Flip from 32bpp non scaled fb to 64bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-32bpp-xtile-to-64bpp-xtile-downscaling",
+ "Flip from 32bpp non scaled fb to 64bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-32bpp-4tile-to-64bpp-4tile-downscaling",
+ "Flip from 32bpp non scaled fb to 64bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-32bpp-linear-to-64bpp-linear-downscaling",
+ "Flip from 32bpp non scaled fb to 64bpp downscaled fb to stress CD clock programming",
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
+ {
"flip-64bpp-ytile-to-32bpp-ytile-downscaling",
"Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB16161616F,
@@ -66,6 +98,38 @@ const struct {
2.0,
},
{
+ "flip-64bpp-yftile-to-32bpp-yftile-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB8888,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-64bpp-xtile-to-32bpp-xtile-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB8888,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-64bpp-4tile-to-32bpp-4tile-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB8888,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-64bpp-linear-to-32bpp-linear-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB8888,
+ 1.0,
+ 2.0,
+ },
+ {
"flip-64bpp-ytile-to-16bpp-ytile-downscaling",
"Flip from 64bpp non scaled fb to 16bpp downscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB16161616F,
@@ -74,6 +138,38 @@ const struct {
2.0,
},
{
+ "flip-64bpp-yftile-to-16bpp-yftile-downscaling",
+ "Flip from 64bpp non scaled fb to 16bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_RGB565,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-64bpp-xtile-to-16bpp-xtile-downscaling",
+ "Flip from 64bpp non scaled fb to 16bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_RGB565,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-64bpp-4tile-to-16bpp-4tile-downscaling",
+ "Flip from 64bpp non scaled fb to 16bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_RGB565,
+ 1.0,
+ 2.0,
+ },
+ {
+ "flip-64bpp-linear-to-16bpp-linear-downscaling",
+ "Flip from 64bpp non scaled fb to 16bpp downscaled fb to stress CD clock programming",
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_RGB565,
+ 1.0,
+ 2.0,
+ },
+ {
"flip-32bpp-ytileccs-to-64bpp-ytile-downscaling",
"Flip from 32bpp non scaled fb to 64bpp downscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED_CCS, DRM_FORMAT_XRGB8888,
@@ -82,6 +178,14 @@ const struct {
2.0,
},
{
+ "flip-32bpp-yftileccs-to-64bpp-yftile-downscaling",
+ "Flip from 32bpp non scaled fb to 64bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED_CCS, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ 1.0,
+ 2.0,
+ },
+ {
"flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling",
"Flip from 32bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB8888,
@@ -90,6 +194,14 @@ const struct {
2.0,
},
{
+ "flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling",
+ "Flip from 32bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, DRM_FORMAT_XRGB8888,
+ 1.0,
+ 2.0,
+ },
+ {
"flip-32bpp-ytile-to-32bpp-ytileccs-downscaling",
"Flip from 32bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB8888,
@@ -98,6 +210,14 @@ const struct {
2.0,
},
{
+ "flip-32bpp-yftile-to-32bpp-yftileccs-downscaling",
+ "Flip from 32bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_Yf_TILED_CCS, DRM_FORMAT_XRGB8888,
+ 1.0,
+ 2.0,
+ },
+ {
"flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling",
"Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB16161616F,
@@ -106,6 +226,14 @@ const struct {
2.0,
},
{
+ "flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling",
+ "Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, DRM_FORMAT_XRGB8888,
+ 1.0,
+ 2.0,
+ },
+ {
"flip-32bpp-ytile-to-64bpp-ytile-upscaling",
"Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB8888,
@@ -114,6 +242,38 @@ const struct {
1.0,
},
{
+ "flip-32bpp-yftile-to-64bpp-yftile-upscaling",
+ "Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-32bpp-xtile-to-64bpp-xtile-upscaling",
+ "Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-32bpp-4tile-to-64bpp-4tile-upscaling",
+ "Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-32bpp-linear-to-64bpp-linear-upscaling",
+ "Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
"flip-64bpp-ytile-to-32bpp-ytile-upscaling",
"Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB16161616F,
@@ -122,6 +282,38 @@ const struct {
1.0,
},
{
+ "flip-64bpp-yftile-to-32bpp-yftile-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB8888,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-xtile-to-32bpp-xtile-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB8888,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-4tile-to-32bpp-4tile-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB8888,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-linear-to-32bpp-linear-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB8888,
+ 0.5,
+ 1.0,
+ },
+ {
"flip-64bpp-ytile-to-16bpp-ytile-upscaling",
"Flip from 64bpp non scaled fb to 16bpp upscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB16161616F,
@@ -130,6 +322,38 @@ const struct {
1.0,
},
{
+ "flip-64bpp-yftile-to-16bpp-yftile-upscaling",
+ "Flip from 64bpp non scaled fb to 16bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_RGB565,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-xtile-to-16bpp-xtile-upscaling",
+ "Flip from 64bpp non scaled fb to 16bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_X_TILED, DRM_FORMAT_RGB565,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-4tile-to-16bpp-4tile-upscaling",
+ "Flip from 64bpp non scaled fb to 16bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_RGB565,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-linear-to-16bpp-linear-upscaling",
+ "Flip from 64bpp non scaled fb to 16bpp upscaled fb to stress CD clock programming",
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_RGB565,
+ 0.5,
+ 1.0,
+ },
+ {
"flip-32bpp-ytileccs-to-64bpp-ytile-upscaling",
"Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED_CCS, DRM_FORMAT_XRGB8888,
@@ -138,6 +362,14 @@ const struct {
1.0,
},
{
+ "flip-32bpp-yftileccs-to-64bpp-yftile-upscaling",
+ "Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED_CCS, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB16161616F,
+ 0.5,
+ 1.0,
+ },
+ {
"flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling",
"Flip from 32bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB8888,
@@ -146,6 +378,14 @@ const struct {
1.0,
},
{
+ "flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling",
+ "Flip from 32bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, DRM_FORMAT_XRGB8888,
+ 0.5,
+ 1.0,
+ },
+ {
"flip-32bpp-ytile-to-32bpp-ytileccs-upscaling",
"Flip from 32bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB8888,
@@ -154,13 +394,29 @@ const struct {
1.0,
},
{
- "flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling",
+ "flip-32bpp-yftile-to-32bpp-yftileccs-upscaling",
+ "Flip from 32bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_Yf_TILED, DRM_FORMAT_XRGB8888,
+ I915_FORMAT_MOD_Yf_TILED_CCS, DRM_FORMAT_XRGB8888,
+ 0.5,
+ 1.0,
+ },
+ {
+ "flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling",
"Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
I915_FORMAT_MOD_Y_TILED, DRM_FORMAT_XRGB16161616F,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, DRM_FORMAT_XRGB8888,
0.5,
1.0,
},
+ {
+ "flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling",
+ "Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
+ I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, DRM_FORMAT_XRGB8888,
+ 0.5,
+ 1.0,
+ },
};
static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width,