lib/intel_mmio: add additional api for multiple devices

Library  was limited for reading registers for only
one device at a time in igt tests.
Changes in this patch give as oportunity to test multiple devices in
the same time.

v8: pack and rename structure, remove unnecessary field
v7: remove unnecessary code
v6: Reword patch. Cosmetic changes.

Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>

Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

22 files changed, 243 insertions, 187 deletions

diff --git a/benchmarks/gem_latency.c b/benchmarks/gem_latency.c
index c3fc4bf0..0fc4b05e 100644
--- a/benchmarks/gem_latency.c
+++ b/benchmarks/gem_latency.c
@@ -55,6 +55,7 @@
 static int done;
 static int fd;
 static volatile uint32_t *timestamp_reg;
+static struct intel_mmio_data mmio_data;
 
 #define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x)
 #define REG_OFFSET(x) ((volatile char *)(x) - (volatile char *)igt_global_mmio)
@@ -456,7 +457,7 @@ static int run(int seconds,
 	if (gen < 6)
 		return IGT_EXIT_SKIP; /* Needs BCS timestamp */
 
-	intel_register_access_init(intel_get_pci_device(), false, fd);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd);
 
 	if (gen == 6)
 		timestamp_reg = REG(RCS_TIMESTAMP);
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index b8e22b3f..87f873b0 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -238,6 +238,7 @@ struct workload
 	} busy_balancer;
 };
 
+struct intel_mmio_data mmio_data;
 static const unsigned int nop_calibration_us = 1000;
 static unsigned long nop_calibration;
 
@@ -3071,7 +3072,7 @@ static void init_clocks(void)
 	uint32_t rcs_start, rcs_end;
 	double overhead, t;
 
-	intel_register_access_init(intel_get_pci_device(), false, fd);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd);
 
 	if (verbose <= 1)
 		return;
diff --git a/lib/intel_io.h b/lib/intel_io.h
index 49ab08ac..1cfe4fb6 100644
--- a/lib/intel_io.h
+++ b/lib/intel_io.h
@@ -30,17 +30,42 @@
 
 #include <stdint.h>
 #include <pciaccess.h>
+#include <stdbool.h>
 
-/* register access helpers from intel_mmio.c */
 extern void *igt_global_mmio;
-void intel_mmio_use_pci_bar(struct pci_device *pci_dev);
-void intel_mmio_use_dump_file(char *file);
 
-int intel_register_access_init(struct pci_device *pci_dev, int safe, int fd);
-void intel_register_access_fini(void);
-uint32_t intel_register_read(uint32_t reg);
-void intel_register_write(uint32_t reg, uint32_t val);
-int intel_register_access_needs_fakewake(void);
+/* register access helpers from intel_mmio.c */
+struct intel_register_range {
+	uint32_t base;
+	uint32_t size;
+	uint32_t flags;
+};
+
+struct intel_register_map {
+	struct intel_register_range *map;
+	uint32_t top;
+	uint32_t alignment_mask;
+};
+
+struct intel_mmio_data {
+	void *igt_mmio;
+	struct intel_register_map map;
+	uint32_t pci_device_id;
+	int key;
+	bool safe;
+};
+
+void intel_mmio_use_pci_bar(struct intel_mmio_data *mmio_data,
+			    struct pci_device *pci_dev);
+void intel_mmio_use_dump_file(struct intel_mmio_data *mmio_data, char *file);
+
+int intel_register_access_init(struct intel_mmio_data *mmio_data,
+			       struct pci_device *pci_dev, int safe, int fd);
+void intel_register_access_fini(struct intel_mmio_data *mmio_data);
+uint32_t intel_register_read(struct intel_mmio_data *mmio_data, uint32_t reg);
+void intel_register_write(struct intel_mmio_data *mmio_data, uint32_t reg,
+			  uint32_t val);
+int intel_register_access_needs_fakewake(struct intel_mmio_data *mmio_data);
 
 /* mmio register access functions that use igt_global_mmio */
 
@@ -86,17 +111,24 @@ __OUTREG(8,8)
 #undef __OUTREG
 
 /* sideband access functions from intel_iosf.c */
-uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
-void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
-uint32_t intel_flisdsi_reg_read(uint32_t reg);
-void intel_flisdsi_reg_write(uint32_t reg, uint32_t val);
-uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg);
-void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val);
-
-int intel_punit_read(uint32_t addr, uint32_t *val);
-int intel_punit_write(uint32_t addr, uint32_t val);
-int intel_nc_read(uint32_t addr, uint32_t *val);
-int intel_nc_write(uint32_t addr, uint32_t val);
+uint32_t intel_dpio_reg_read(struct intel_mmio_data *mmio_data, uint32_t reg,
+			     int phy);
+void intel_dpio_reg_write(struct intel_mmio_data *mmio_data, uint32_t reg,
+			  uint32_t val, int phy);
+uint32_t intel_flisdsi_reg_read(struct intel_mmio_data *mmio_data, uint32_t reg);
+void intel_flisdsi_reg_write(struct intel_mmio_data *mmio_data, uint32_t reg,
+			     uint32_t val);
+uint32_t intel_iosf_sb_read(struct intel_mmio_data *mmio_data, uint32_t port,
+			    uint32_t reg);
+void intel_iosf_sb_write(struct intel_mmio_data *mmio_data, uint32_t port,
+			 uint32_t reg, uint32_t val);
+
+int intel_punit_read(struct intel_mmio_data *mmio_data, uint32_t addr,
+		     uint32_t *val);
+int intel_punit_write(struct intel_mmio_data *mmio_data, uint32_t addr,
+		      uint32_t val);
+int intel_nc_read(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t *val);
+int intel_nc_write(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t val);
 
 /* register maps from intel_reg_map.c */
 #ifndef __GTK_DOC_IGNORE__
@@ -107,17 +139,6 @@ int intel_nc_write(uint32_t addr, uint32_t val);
 #define INTEL_RANGE_RW		(INTEL_RANGE_READ | INTEL_RANGE_WRITE)
 #define INTEL_RANGE_END		(1<<31)
 
-struct intel_register_range {
-	uint32_t base;
-	uint32_t size;
-	uint32_t flags;
-};
-
-struct intel_register_map {
-	struct intel_register_range *map;
-	uint32_t top;
-	uint32_t alignment_mask;
-};
 struct intel_register_map intel_get_register_map(uint32_t devid);
 struct intel_register_range *intel_get_register_range(struct intel_register_map map, uint32_t offset, uint32_t mode);
 #endif /* __GTK_DOC_IGNORE__ */
diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
index 3b5a1370..16862ef4 100644
--- a/lib/intel_iosf.c
+++ b/lib/intel_iosf.c
@@ -19,8 +19,8 @@
 /* Private register write, double-word addressing, non-posted */
 #define SB_CRWRDA_NP   0x07
 
-static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
-			   uint32_t *val)
+static int vlv_sideband_rw(struct intel_mmio_data *mmio_data, uint32_t port,
+			   uint8_t opcode, uint32_t addr, uint32_t *val)
 {
 	int timeout = 0;
 	uint32_t cmd, devfn, be, bar;
@@ -34,22 +34,24 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
 		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
 		(bar << IOSF_BAR_SHIFT);
 
-	if (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+	if (intel_register_read(mmio_data, VLV_IOSF_DOORBELL_REQ) &
+	    IOSF_SB_BUSY) {
 		igt_warn("warning: pcode (%s) mailbox access failed\n", is_read ? "read" : "write");
 		return -EAGAIN;
 	}
 
-	intel_register_write(VLV_IOSF_ADDR, addr);
+	intel_register_write(mmio_data, VLV_IOSF_ADDR, addr);
 	if (!is_read)
-		intel_register_write(VLV_IOSF_DATA, *val);
+		intel_register_write(mmio_data, VLV_IOSF_DATA, *val);
 
-	intel_register_write(VLV_IOSF_DOORBELL_REQ, cmd);
+	intel_register_write(mmio_data, VLV_IOSF_DOORBELL_REQ, cmd);
 
 	do {
 		usleep(1);
 		timeout++;
-	} while (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY &&
-		 timeout < TIMEOUT_US);
+	} while (intel_register_read(mmio_data->igt_mmio,
+				     VLV_IOSF_DOORBELL_REQ) &
+		IOSF_SB_BUSY && timeout < TIMEOUT_US);
 
 	if (timeout >= TIMEOUT_US) {
 		igt_warn("timeout waiting for pcode %s (%d) to finish\n", is_read ? "read" : "write", addr);
@@ -57,8 +59,8 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
 	}
 
 	if (is_read)
-		*val = intel_register_read(VLV_IOSF_DATA);
-	intel_register_write(VLV_IOSF_DATA, 0);
+		*val = intel_register_read(mmio_data->igt_mmio, VLV_IOSF_DATA);
+	intel_register_write(mmio_data->igt_mmio, VLV_IOSF_DATA, 0);
 
 	return 0;
 }
@@ -73,9 +75,10 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_punit_read(uint32_t addr, uint32_t *val)
+int intel_punit_read(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t *val)
 {
-	return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr,
+			       val);
 }
 
 /**
@@ -88,9 +91,10 @@ int intel_punit_read(uint32_t addr, uint32_t *val)
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_punit_write(uint32_t addr, uint32_t val)
+int intel_punit_write(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t val)
 {
-	return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr,
+			       &val);
 }
 
 /**
@@ -103,9 +107,10 @@ int intel_punit_write(uint32_t addr, uint32_t val)
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_nc_read(uint32_t addr, uint32_t *val)
+int intel_nc_read(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t *val)
 {
-	return vlv_sideband_rw(IOSF_PORT_NC, SB_CRRDDA_NP, addr, val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRRDDA_NP, addr,
+			       val);
 }
 
 /**
@@ -118,9 +123,10 @@ int intel_nc_read(uint32_t addr, uint32_t *val)
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_nc_write(uint32_t addr, uint32_t val)
+int intel_nc_write(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t val)
 {
-	return vlv_sideband_rw(IOSF_PORT_NC, SB_CRWRDA_NP, addr, &val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRWRDA_NP, addr,
+			       &val);
 }
 
 /**
@@ -133,14 +139,16 @@ int intel_nc_write(uint32_t addr, uint32_t val)
  * Returns:
  * The value read from the register.
  */
-uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
+uint32_t intel_dpio_reg_read(struct intel_mmio_data *mmio_data, uint32_t reg, int phy)
 {
 	uint32_t val;
 
 	if (phy == 0)
-		vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MRD_NP, reg,
+				&val);
 	else
-		vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MRD_NP, reg,
+				&val);
 	return val;
 }
 
@@ -152,38 +160,40 @@ uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
  *
  * 32-bit write of the register at @offset through the DPIO sideband port.
  */
-void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
+void intel_dpio_reg_write(struct intel_mmio_data *mmio_data, uint32_t reg, uint32_t val, int phy)
 {
 	if (phy == 0)
-		vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
 	else
-		vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MWR_NP, reg,
+				&val);
 }
 
-uint32_t intel_flisdsi_reg_read(uint32_t reg)
+uint32_t intel_flisdsi_reg_read(struct intel_mmio_data *mmio_data, uint32_t reg)
 {
 	uint32_t val = 0;
 
-	vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
 
 	return val;
 }
 
-void intel_flisdsi_reg_write(uint32_t reg, uint32_t val)
+void intel_flisdsi_reg_write(struct intel_mmio_data *mmio_data, uint32_t reg, uint32_t val)
 {
-	vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
 }
 
-uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg)
+uint32_t intel_iosf_sb_read(struct intel_mmio_data *mmio_data, uint32_t port, uint32_t reg)
 {
 	uint32_t val;
 
-	vlv_sideband_rw(port, SB_CRRDDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, port, SB_CRRDDA_NP, reg, &val);
 
 	return val;
 }
 
-void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val)
+void intel_iosf_sb_write(struct intel_mmio_data *mmio_data, uint32_t port,
+			 uint32_t reg, uint32_t val)
 {
-	vlv_sideband_rw(port, SB_CRWRDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, port, SB_CRWRDA_NP, reg, &val);
 }
diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c
index 464e6528..667a69f5 100644
--- a/lib/intel_mmio.c
+++ b/lib/intel_mmio.c
@@ -70,57 +70,57 @@
  *
  * Pointer to the register range, initialized using intel_register_access_init()
  * or intel_mmio_use_dump_file(). It is not recommended to use this directly.
+ * This pointer is valid only for one drm device.
  */
 void *igt_global_mmio;
 
-static struct _mmio_data {
-	int inited;
-	bool safe;
-	uint32_t i915_devid;
-	struct intel_register_map map;
-	int key;
-} mmio_data;
-
 /**
  * intel_mmio_use_dump_file:
+ * @mmio_data:  mmio structure for IO operations
  * @file: name of the register dump file to open
  *
- * Sets up #igt_global_mmio to point at the data contained in @file. This allows
- * the same code to get reused for dumping and decoding from running hardware as
- * from register dumps.
+ * Sets also up mmio_data->igt_mmio to point at the data contained
+ * in @file. This allows the same code to get reused for dumping and decoding
+ * from running hardware as from register dumps.
  */
 void
-intel_mmio_use_dump_file(char *file)
+intel_mmio_use_dump_file(struct intel_mmio_data *mmio_data, char *file)
 {
 	int fd;
 	struct stat st;
 
+	memset(mmio_data, 0, sizeof(struct intel_mmio_data));
 	fd = open(file, O_RDWR);
 	igt_fail_on_f(fd == -1,
 		      "Couldn't open %s\n", file);
 
 	fstat(fd, &st);
-	igt_global_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
-	igt_fail_on_f(igt_global_mmio == MAP_FAILED,
+	mmio_data->igt_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
+	igt_fail_on_f(mmio_data->igt_mmio == MAP_FAILED,
 		      "Couldn't mmap %s\n", file);
+
+	igt_global_mmio = mmio_data->igt_mmio;
+
 	close(fd);
 }
 
 /**
  * intel_mmio_use_pci_bar:
+ * @mmio_data:  mmio structure for IO operations
  * @pci_dev: intel gracphis pci device
  *
- * Sets up #igt_global_mmio to point at the mmio bar.
+ * Fill a mmio_data stucture with igt_mmio to point at the mmio bar.
  *
  * @pci_dev can be obtained from intel_get_pci_device().
  */
 void
-intel_mmio_use_pci_bar(struct pci_device *pci_dev)
+intel_mmio_use_pci_bar(struct intel_mmio_data *mmio_data, struct pci_device *pci_dev)
 {
 	uint32_t devid, gen;
 	int mmio_bar, mmio_size;
 	int error;
 
+	memset(mmio_data, 0, sizeof(struct intel_mmio_data));
 	devid = pci_dev->device_id;
 	if (IS_GEN2(devid))
 		mmio_bar = 1;
@@ -139,7 +139,9 @@ intel_mmio_use_pci_bar(struct pci_device *pci_dev)
 				      pci_dev->regions[mmio_bar].base_addr,
 				      mmio_size,
 				      PCI_DEV_MAP_FLAG_WRITABLE,
-				      &igt_global_mmio);
+				      &mmio_data->igt_mmio);
+
+	igt_global_mmio = mmio_data->igt_mmio;
 
 	igt_fail_on_f(error != 0,
 		      "Couldn't map MMIO region\n");
@@ -153,6 +155,7 @@ release_forcewake_lock(int fd)
 
 /**
  * intel_register_access_init:
+ * @mmio_data:  mmio structure for IO operations
  * @pci_dev: intel graphics pci device
  * @safe: use safe register access tables
  *
@@ -160,76 +163,72 @@ release_forcewake_lock(int fd)
  * handling and also allows register access to be checked with an explicit
  * whitelist.
  *
- * It also initializes #igt_global_mmio like intel_mmio_use_pci_bar().
+ * It also initializes mmio_data->igt_mmio like intel_mmio_use_pci_bar().
  *
  * @pci_dev can be obtained from intel_get_pci_device().
  */
 int
-intel_register_access_init(struct pci_device *pci_dev, int safe, int fd)
+intel_register_access_init(struct intel_mmio_data *mmio_data, struct pci_device *pci_dev, int safe, int fd)
 {
 	int ret;
 
-	/* after old API is deprecated, remove this */
-	if (igt_global_mmio == NULL)
-		intel_mmio_use_pci_bar(pci_dev);
+	intel_mmio_use_pci_bar(mmio_data, pci_dev);
 
-	igt_assert(igt_global_mmio != NULL);
+	igt_assert(mmio_data->igt_mmio != NULL);
 
-	if (mmio_data.inited)
-		return -1;
-
-	mmio_data.safe = (safe != 0 &&
+	mmio_data->safe = (safe != 0 &&
 			intel_gen(pci_dev->device_id) >= 4) ? true : false;
-	mmio_data.i915_devid = pci_dev->device_id;
-	if (mmio_data.safe)
-		mmio_data.map = intel_get_register_map(mmio_data.i915_devid);
+	mmio_data->pci_device_id = pci_dev->device_id;
+	if (mmio_data->safe)
+		mmio_data->map = intel_get_register_map(mmio_data->pci_device_id);
 
 	/* Find where the forcewake lock is. Forcewake doesn't exist
 	 * gen < 6, but the debugfs should do the right things for us.
 	 */
 	ret = igt_open_forcewake_handle(fd);
 	if (ret == -1)
-		mmio_data.key = FAKEKEY;
+		mmio_data->key = FAKEKEY;
 	else
-		mmio_data.key = ret;
+		mmio_data->key = ret;
 
-	mmio_data.inited++;
 	return 0;
 }
 
 static int
-intel_register_access_needs_wake(void)
+intel_register_access_needs_wake(struct intel_mmio_data *mmio_data)
 {
-	return mmio_data.key != FAKEKEY;
+	return mmio_data->key != FAKEKEY;
 }
 
 /**
  * intel_register_access_needs_fakewake:
+ * @mmio_data:  mmio structure for IO operations
  *
  * Returns:
  * Non-zero when forcewake initialization failed.
  */
-int intel_register_access_needs_fakewake(void)
+int intel_register_access_needs_fakewake(struct intel_mmio_data *mmio_data)
 {
-	return mmio_data.key == FAKEKEY;
+	return mmio_data->key == FAKEKEY;
 }
 
 /**
  * intel_register_access_fini:
+ * @mmio_data:  mmio structure for IO operations
  *
  * Clean up the register access helper initialized with
  * intel_register_access_init().
  */
 void
-intel_register_access_fini(void)
+intel_register_access_fini(struct intel_mmio_data *mmio_data)
 {
-	if (mmio_data.key && intel_register_access_needs_wake())
-		release_forcewake_lock(mmio_data.key);
-	mmio_data.inited--;
+	if (mmio_data->key && intel_register_access_needs_wake(mmio_data))
+		release_forcewake_lock(mmio_data->key);
 }
 
 /**
  * intel_register_read:
+ * @mmio_data:  mmio structure for IO operations
  * @reg: register offset
  *
  * 32-bit read of the register at @offset. This function only works when the new
@@ -242,20 +241,18 @@ intel_register_access_fini(void)
  * The value read from the register.
  */
 uint32_t
-intel_register_read(uint32_t reg)
+intel_register_read(struct intel_mmio_data *mmio_data, uint32_t reg)
 {
 	struct intel_register_range *range;
 	uint32_t ret;
 
-	igt_assert(mmio_data.inited);
-
-	if (intel_gen(mmio_data.i915_devid) >= 6)
-		igt_assert(mmio_data.key != -1);
+	if (intel_gen(mmio_data->pci_device_id) >= 6)
+		igt_assert(mmio_data->key != -1);
 
-	if (!mmio_data.safe)
+	if (!mmio_data->safe)
 		goto read_out;
 
-	range = intel_get_register_range(mmio_data.map,
+	range = intel_get_register_range(mmio_data->map,
 					 reg,
 					 INTEL_RANGE_READ);
 
@@ -266,13 +263,14 @@ intel_register_read(uint32_t reg)
 	}
 
 read_out:
-	ret = ioread32(igt_global_mmio, reg);
+	ret = ioread32(mmio_data->igt_mmio, reg);
 out:
 	return ret;
 }
 
 /**
  * intel_register_write:
+ * @mmio_data:  mmio structure for IO operations
  * @reg: register offset
  * @val: value to write
  *
@@ -283,19 +281,17 @@ out:
  * white lists.
  */
 void
-intel_register_write(uint32_t reg, uint32_t val)
+intel_register_write(struct intel_mmio_data *mmio_data, uint32_t reg, uint32_t val)
 {
 	struct intel_register_range *range;
 
-	igt_assert(mmio_data.inited);
-
-	if (intel_gen(mmio_data.i915_devid) >= 6)
-		igt_assert(mmio_data.key != -1);
+	if (intel_gen(mmio_data->pci_device_id) >= 6)
+		igt_assert(mmio_data->key != -1);
 
-	if (!mmio_data.safe)
+	if (!mmio_data->safe)
 		goto write_out;
 
-	range = intel_get_register_range(mmio_data.map,
+	range = intel_get_register_range(mmio_data->map,
 					 reg,
 					 INTEL_RANGE_WRITE);
 
@@ -303,5 +299,5 @@ intel_register_write(uint32_t reg, uint32_t val)
 		      "Register write blocked for safety ""(*0x%08x = 0x%x)\n", reg, val);
 
 write_out:
-	iowrite32(igt_global_mmio, reg, val);
+	iowrite32(mmio_data->igt_mmio, reg, val);
 }
diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
index e56d6278..9ddb348c 100644
--- a/tests/i915/gem_exec_latency.c
+++ b/tests/i915/gem_exec_latency.c
@@ -61,6 +61,8 @@
 
 static unsigned int ring_size;
 static double rcs_clock;
+static struct intel_mmio_data mmio_data;
+
 
 static void
 poll_ring(int fd, unsigned ring, const char *name)
@@ -667,7 +669,7 @@ igt_main
 		if (ring_size > 1024)
 			ring_size = 1024;
 
-		intel_register_access_init(intel_get_pci_device(), false, device);
+		intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device);
 		rcs_clock = clockrate(device, RCS_TIMESTAMP);
 		igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n",
 			 rcs_clock / 1e3, 1e9 / rcs_clock);
diff --git a/tests/i915/gem_exec_parse.c b/tests/i915/gem_exec_parse.c
index 62e8d0a5..60bee26d 100644
--- a/tests/i915/gem_exec_parse.c
+++ b/tests/i915/gem_exec_parse.c
@@ -58,6 +58,8 @@
 
 static int parser_version;
 
+struct intel_mmio_data mmio_data;
+
 static int command_parser_version(int fd)
 {
 	int version = -1;
@@ -284,9 +286,9 @@ test_lri(int fd, uint32_t handle, struct test_lri *test)
 		  test->name, test->reg, test->test_val,
 		  expected_errno, expect);
 
-	intel_register_write(test->reg, test->init_val);
+	intel_register_write(&mmio_data, test->reg, test->init_val);
 
-	igt_assert_eq_u32((intel_register_read(test->reg) &
+	igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) &
 			   test->read_mask),
 			  test->init_val);
 
@@ -296,7 +298,7 @@ test_lri(int fd, uint32_t handle, struct test_lri *test)
 		   expected_errno);
 	gem_sync(fd, handle);
 
-	igt_assert_eq_u32((intel_register_read(test->reg) &
+	igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) &
 			   test->read_mask),
 			  expect);
 }
@@ -530,7 +532,7 @@ igt_main
 #undef REG
 
 		igt_fixture {
-			intel_register_access_init(intel_get_pci_device(), 0, fd);
+			intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, fd);
 		}
 
 		for (int i = 0; i < ARRAY_SIZE(lris); i++) {
@@ -543,7 +545,7 @@ igt_main
 		}
 
 		igt_fixture {
-			intel_register_access_fini();
+			intel_register_access_fini(&mmio_data);
 		}
 	}
 
diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 81c356f0..dd6316ea 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -225,6 +225,7 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
 
 igt_main
 {
+	struct intel_mmio_data mmio_data;
 	int device = -1;
 	const struct {
 		const char *name;
@@ -256,7 +257,7 @@ igt_main
 		device = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(device);
 
-		intel_mmio_use_pci_bar(intel_get_pci_device());
+		intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device());
 
 		gen = intel_gen(intel_get_drm_devid(device));
 
diff --git a/tests/i915/i915_pm_lpsp.c b/tests/i915/i915_pm_lpsp.c
index b319dbe9..42938e10 100644
--- a/tests/i915/i915_pm_lpsp.c
+++ b/tests/i915/i915_pm_lpsp.c
@@ -187,7 +187,7 @@ int drm_fd;
 uint32_t devid;
 drmModeResPtr drm_res;
 drmModeConnectorPtr drm_connectors[MAX_CONNECTORS];
-
+struct intel_mmio_data mmio_data;
 igt_main
 {
 	igt_fixture {
@@ -210,7 +210,7 @@ igt_main
 
 		igt_require(supports_lpsp(devid));
 
-		intel_register_access_init(intel_get_pci_device(), 0, drm_fd);
+		intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, drm_fd);
 
 		kmstest_set_vt_graphics_mode();
 	}
@@ -227,7 +227,7 @@ igt_main
 	igt_fixture {
 		int i;
 
-		intel_register_access_fini();
+		intel_register_access_fini(&mmio_data);
 		for (i = 0; i < drm_res->count_connectors; i++)
 			drmModeFreeConnector(drm_connectors[i]);
 		drmModeFreeResources(drm_res);
diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
index 726bb4b6..6d11659e 100644
--- a/tools/intel_audio_dump.c
+++ b/tools/intel_audio_dump.c
@@ -42,6 +42,7 @@ static uint32_t devid;
 static int aud_reg_base = 0;	/* base address of audio registers */
 static int disp_reg_base = 0;	/* base address of display registers */
 
+
 #define IS_HASWELL_PLUS(devid)  (IS_HASWELL(devid) || IS_BROADWELL(devid))
 
 #define BITSTO(n)		(n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
@@ -2464,6 +2465,7 @@ static void dump_braswell(void)
 int main(int argc, char **argv)
 {
 	struct pci_device *pci_dev;
+	struct intel_mmio_data mmio_data;
 
 	pci_dev = intel_get_pci_device();
 	devid = pci_dev->device_id; /* XXX not true when mapping! */
@@ -2471,9 +2473,9 @@ int main(int argc, char **argv)
 	do_self_tests();
 
 	if (argc == 2)
-		intel_mmio_use_dump_file(argv[1]);
+		intel_mmio_use_dump_file(&mmio_data, argv[1]);
 	else
-		intel_mmio_use_pci_bar(pci_dev);
+		intel_mmio_use_pci_bar(&mmio_data, pci_dev);
 
 	printf("%s audio registers:\n\n", intel_get_device_info(devid)->codename);
 	if (IS_VALLEYVIEW(devid)) {
diff --git a/tools/intel_backlight.c b/tools/intel_backlight.c
index 067fd418..edf06022 100644
--- a/tools/intel_backlight.c
+++ b/tools/intel_backlight.c
@@ -38,9 +38,10 @@
 
 int main(int argc, char** argv)
 {
+	struct intel_mmio_data mmio_data;
 	uint32_t current, max;
 
-	intel_mmio_use_pci_bar(intel_get_pci_device());
+	intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device());
 
 	current = INREG(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 	max = INREG(BLC_PWM_PCH_CTL2) >> 16;
diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 51f5b9a5..f4797a20 100644
--- a/tools/intel_display_poller.c
+++ b/tools/intel_display_poller.c
@@ -962,6 +962,7 @@ static void __attribute__((noreturn)) usage(const char *name)
 
 int main(int argc, char *argv[])
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	int pipe = 0, bit = 0, target_scanline = 0, target_fuzz = 1;
 	bool test_pixelcount = false;
@@ -1187,7 +1188,7 @@ int main(int argc, char *argv[])
 		break;
 	}
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data ,intel_get_pci_device(), 0, -1);
 
 	printf("%s?\n", test_name(test, pipe, bit, test_pixelcount));
 
@@ -1262,7 +1263,7 @@ int main(int argc, char *argv[])
 		assert(0);
 	}
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	if (quit)
 		return 0;
diff --git a/tools/intel_forcewaked.c b/tools/intel_forcewaked.c
index 02fbf888..87b26d43 100644
--- a/tools/intel_forcewaked.c
+++ b/tools/intel_forcewaked.c
@@ -57,14 +57,15 @@ help(char *prog) {
 }
 
 static int
-is_alive(void) {
+is_alive(struct intel_mmio_data *mmio_data) {
 	/* Read the timestamp, which should *almost* always be !0 */
-	return (intel_register_read(0x2358) != 0);
+	return (intel_register_read(mmio_data, 0x2358) != 0);
 }
 
 int main(int argc, char *argv[])
 {
 	int ret;
+	struct intel_mmio_data mmio_data;
 
 	if (argc > 2 || (argc == 2 && !strncmp(argv[1], "-h", 2))) {
 		help(argv[1]);
@@ -80,7 +81,7 @@ int main(int argc, char *argv[])
 		INFO_PRINT("started daemon");
 	}
 
-	ret = intel_register_access_init(intel_get_pci_device(), 1, -1);
+	ret = intel_register_access_init(&mmio_data, intel_get_pci_device(), 1, -1);
 	if (ret) {
 		INFO_PRINT("Couldn't init register access\n");
 		exit(1);
@@ -88,16 +89,16 @@ int main(int argc, char *argv[])
 		INFO_PRINT("Forcewake locked\n");
 	}
 	while(1) {
-		if (!is_alive()) {
+		if (!is_alive(&mmio_data)) {
 			INFO_PRINT("gpu reset? restarting daemon\n");
-			intel_register_access_fini();
-			ret = intel_register_access_init(intel_get_pci_device(), 1, -1);
+			intel_register_access_fini(&mmio_data);
+			ret = intel_register_access_init(&mmio_data, intel_get_pci_device(), 1, -1);
 			if (ret)
 				INFO_PRINT("Reg access init fail\n");
 		}
 		sleep(1);
 	}
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 	INFO_PRINT("Forcewake unlock\n");
 
 	if (daemonized) {
diff --git a/tools/intel_gpu_time.c b/tools/intel_gpu_time.c
index 56d65fe0..11bf7354 100644
--- a/tools/intel_gpu_time.c
+++ b/tools/intel_gpu_time.c
@@ -65,9 +65,10 @@ int main(int argc, char **argv)
 	uint64_t ring_idle = 0, ring_time = 0;
 	struct timeval start, end;
 	static struct rusage rusage;
+	struct intel_mmio_data mmio_data;
 	int status;
 
-	intel_mmio_use_pci_bar(intel_get_pci_device());
+	intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device());
 
 	if (argc == 1) {
 		fprintf(stderr, "usage: %s cmd [args...]\n", argv[0]);
diff --git a/tools/intel_infoframes.c b/tools/intel_infoframes.c
index 2ef5d4fd..d4bf528c 100644
--- a/tools/intel_infoframes.c
+++ b/tools/intel_infoframes.c
@@ -264,6 +264,7 @@ const char *dip_frequency_names[] = {
 
 struct pci_device *pci_dev;
 int gen = 0;
+struct intel_mmio_data mmio_data;
 
 static const char *spd_source_to_string(SourceDevice source)
 {
@@ -1108,7 +1109,7 @@ int main(int argc, char *argv[])
 	       " perfectly: the Kernel might undo our changes.\n");
 
 	pci_dev = intel_get_pci_device();
-	intel_register_access_init(pci_dev, 0, -1);
+	intel_register_access_init(&mmio_data, pci_dev, 0, -1);
 	intel_check_pch();
 
 	if (IS_GEN4(pci_dev->device_id))
@@ -1256,6 +1257,6 @@ int main(int argc, char *argv[])
 	}
 
 out:
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 	return ret;
 }
diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c
index 4179c5ae..06a185c9 100644
--- a/tools/intel_l3_parity.c
+++ b/tools/intel_l3_parity.c
@@ -176,6 +176,7 @@ static void usage(const char *name)
 
 int main(int argc, char *argv[])
 {
+	struct intel_mmio_data mmio_data;
 	const char *path[REAL_MAX_SLICES] = {"l3_parity", "l3_parity_slice_1"};
 	int row = 0, bank = 0, sbank = 0;
 	int fd[REAL_MAX_SLICES] = {0}, ret, i;
@@ -189,7 +190,7 @@ int main(int argc, char *argv[])
 	if (intel_gen(devid) < 7 || IS_VALLEYVIEW(devid))
 		exit(77);
 
-	assert(intel_register_access_init(intel_get_pci_device(), 0, device) == 0);
+	assert(intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, device) == 0);
 
 	dir = igt_sysfs_open(device);
 
@@ -217,7 +218,7 @@ int main(int argc, char *argv[])
 	 * now. Just be aware of this if for some reason a hang is reported
 	 * when using this tool.
 	 */
-	dft = intel_register_read(0xb038);
+	dft = intel_register_read(&mmio_data, 0xb038);
 
 	while (1) {
 		int c, option_index = 0;
@@ -366,10 +367,10 @@ int main(int argc, char *argv[])
 				assert(i < 2);
 				dft |= i << 1; /* slice */
 				dft |= 1 << 0; /* enable */
-				intel_register_write(0xb038, dft);
+				intel_register_write(&mmio_data, 0xb038, dft);
 				break;
 			case 'u':
-				intel_register_write(0xb038, dft & ~(1<<0));
+				intel_register_write(&mmio_data ,0xb038, dft & ~(1<<0));
 				break;
 			case 'L':
 				break;
@@ -378,7 +379,7 @@ int main(int argc, char *argv[])
 		}
 	}
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 	if (action == 'l')
 		exit(EXIT_SUCCESS);
 
diff --git a/tools/intel_lid.c b/tools/intel_lid.c
index 37c6ba5e..2a1d9800 100644
--- a/tools/intel_lid.c
+++ b/tools/intel_lid.c
@@ -117,9 +117,10 @@ out:
 
 int main(int argc, char **argv)
 {
+	struct intel_mmio_data mmio_data;
 	int swf14, acpi_lid;
 
-	intel_mmio_use_pci_bar(intel_get_pci_device());
+	intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device());
 
 	while (1) {
 		swf14 = INREG(SWF14);
diff --git a/tools/intel_panel_fitter.c b/tools/intel_panel_fitter.c
index 137ef61a..64078705 100644
--- a/tools/intel_panel_fitter.c
+++ b/tools/intel_panel_fitter.c
@@ -273,6 +273,7 @@ int main (int argc, char *argv[])
 	bool do_disable = false, do_dump = false, do_usage = false;
 	struct pci_device *pci_dev;
 	uint32_t devid;
+	struct intel_mmio_data mmio_data;
 
 	printf("WARNING:\n"
 	       "This tool is a workaround for people that don't have a Kernel "
@@ -280,7 +281,7 @@ int main (int argc, char *argv[])
 	       "solution that may or may not work. Use it at your own risk.\n");
 
 	pci_dev = intel_get_pci_device();
-	intel_register_access_init(pci_dev, 0, -1);
+	intel_register_access_init(&mmio_data, pci_dev, 0, -1);
 	devid = pci_dev->device_id;
 
 	if (!HAS_PCH_SPLIT(devid)) {
@@ -342,6 +343,6 @@ int main (int argc, char *argv[])
 	}
 
 out:
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 	return ret;
 }
diff --git a/tools/intel_perf_counters.c b/tools/intel_perf_counters.c
index 50c4bce6..5824d9c1 100644
--- a/tools/intel_perf_counters.c
+++ b/tools/intel_perf_counters.c
@@ -441,6 +441,7 @@ gen7_get_counters(void)
 int
 main(int argc, char **argv)
 {
+	struct intel_mmio_data mmio_data;
 	uint32_t devid;
 	int counter_format;
 	int counter_count;
@@ -483,10 +484,11 @@ main(int argc, char **argv)
 
 	if (oacontrol) {
 		/* Forcewake */
-		intel_register_access_init(intel_get_pci_device(), 0, fd);
+		intel_register_access_init(&mmio_data, intel_get_pci_device(),
+				0, fd);
 
 		/* Enable performance counters */
-		intel_register_write(OACONTROL,
+		intel_register_write(&mmio_data, OACONTROL,
 			counter_format << OACONTROL_COUNTER_SELECT_SHIFT |
 			PERFORMANCE_COUNTER_ENABLE);
 	}
@@ -520,10 +522,10 @@ main(int argc, char **argv)
 
 	if (oacontrol) {
 		/* Disable performance counters */
-		intel_register_write(OACONTROL, 0);
+		intel_register_write(&mmio_data, OACONTROL, 0);
 
 		/* Forcewake */
-		intel_register_access_fini();
+		intel_register_access_fini(&mmio_data);
 	}
 
 	free(totals);
diff --git a/tools/intel_reg.c b/tools/intel_reg.c
index e517956b..847fdbed 100644
--- a/tools/intel_reg.c
+++ b/tools/intel_reg.c
@@ -57,6 +57,7 @@ static inline int _not_supported(void)
 
 struct config {
 	struct pci_device *pci_dev;
+	struct intel_mmio_data mmio_data;
 	char *mmiofile;
 	uint32_t devid;
 
@@ -387,7 +388,7 @@ static int read_register(struct config *config, struct reg *reg, uint32_t *valp)
 				reg->port_desc.name);
 			return -1;
 		}
-		val = intel_iosf_sb_read(reg->port_desc.port, reg->addr);
+		val = intel_iosf_sb_read(&config->mmio_data, reg->port_desc.port, reg->addr);
 		break;
 	default:
 		fprintf(stderr, "port %d not supported\n", reg->port_desc.port);
@@ -458,7 +459,7 @@ static int write_register(struct config *config, struct reg *reg, uint32_t val)
 				reg->port_desc.name);
 			return -1;
 		}
-		intel_iosf_sb_write(reg->port_desc.port, reg->addr, val);
+		intel_iosf_sb_write(&config->mmio_data, reg->port_desc.port, reg->addr, val);
 		break;
 	default:
 		fprintf(stderr, "port %d not supported\n", reg->port_desc.port);
@@ -552,9 +553,9 @@ static int intel_reg_read(struct config *config, int argc, char *argv[])
 	}
 
 	if (config->mmiofile)
-		intel_mmio_use_dump_file(config->mmiofile);
+		intel_mmio_use_dump_file(&config->mmio_data, config->mmiofile);
 	else
-		intel_register_access_init(config->pci_dev, 0, -1);
+		intel_register_access_init(&config->mmio_data, config->pci_dev, 0, -1);
 
 	for (i = 1; i < argc; i++) {
 		struct reg reg;
@@ -570,7 +571,7 @@ static int intel_reg_read(struct config *config, int argc, char *argv[])
 		}
 	}
 
-	intel_register_access_fini();
+	intel_register_access_fini(&config->mmio_data);
 
 	return EXIT_SUCCESS;
 }
@@ -584,7 +585,7 @@ static int intel_reg_write(struct config *config, int argc, char *argv[])
 		return EXIT_FAILURE;
 	}
 
-	intel_register_access_init(config->pci_dev, 0, -1);
+	intel_register_access_init(&config->mmio_data, config->pci_dev, 0, -1);
 
 	for (i = 1; i < argc; i += 2) {
 		struct reg reg;
@@ -609,7 +610,7 @@ static int intel_reg_write(struct config *config, int argc, char *argv[])
 		write_register(config, &reg, val);
 	}
 
-	intel_register_access_fini();
+	intel_register_access_fini(&config->mmio_data);
 
 	return EXIT_SUCCESS;
 }
@@ -620,9 +621,9 @@ static int intel_reg_dump(struct config *config, int argc, char *argv[])
 	int i;
 
 	if (config->mmiofile)
-		intel_mmio_use_dump_file(config->mmiofile);
+		intel_mmio_use_dump_file(&config->mmio_data, config->mmiofile);
 	else
-		intel_register_access_init(config->pci_dev, 0, -1);
+		intel_register_access_init(&config->mmio_data, config->pci_dev, 0, -1);
 
 	for (i = 0; i < config->regcount; i++) {
 		reg = &config->regs[i];
@@ -634,7 +635,7 @@ static int intel_reg_dump(struct config *config, int argc, char *argv[])
 		dump_register(config, &config->regs[i]);
 	}
 
-	intel_register_access_fini();
+	intel_register_access_fini(&config->mmio_data);
 
 	return EXIT_SUCCESS;
 }
@@ -648,7 +649,7 @@ static int intel_reg_snapshot(struct config *config, int argc, char *argv[])
 		return EXIT_FAILURE;
 	}
 
-	intel_mmio_use_pci_bar(config->pci_dev);
+	intel_mmio_use_pci_bar(&config->mmio_data, config->pci_dev);
 
 	/* XXX: error handling */
 	if (write(1, igt_global_mmio, config->pci_dev->regions[mmio_bar].size) == -1)
diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c
index 6bde63ec..3f90de82 100644
--- a/tools/intel_reg_checker.c
+++ b/tools/intel_reg_checker.c
@@ -342,10 +342,11 @@ check_dpfc_control_sa(void)
 int main(int argc, char** argv)
 {
 	struct pci_device *dev;
+	struct intel_mmio_data mmio_data;
 
 	dev = intel_get_pci_device();
 	devid = dev->device_id;
-	intel_mmio_use_pci_bar(dev);
+	intel_mmio_use_pci_bar(&mmio_data, dev);
 
 	if (IS_GEN7(devid))
 		gen = 7;
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index e71c3d9c..14d1ae0d 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -237,6 +237,7 @@ static const char *skl_nv12_buf_cfg_reg_name(int pipe, int plane)
 
 static void skl_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int pipe, plane, level;
 	int num_pipes = 3;
 	int max_planes = skl_max_planes(devid);
@@ -249,7 +250,7 @@ static void skl_wm_dump(void)
 	uint32_t plane_ctl[num_pipes][max_planes];
 	uint32_t wm_linetime[num_pipes];
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	for (pipe = 0; pipe < num_pipes; pipe++) {
 		int num_planes = skl_num_planes(devid, pipe);
@@ -458,6 +459,7 @@ static void skl_wm_dump(void)
 
 static void ilk_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	uint32_t dspcntr[3];
 	uint32_t spcntr[3];
@@ -469,7 +471,7 @@ static void ilk_wm_dump(void)
 	int num_pipes = intel_gen(devid) >= 7 ? 3 : 2;
 	struct ilk_wm wm = {};
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	for (i = 0; i < num_pipes; i++) {
 		dspcntr[i] = read_reg(0x70180 + i * 0x1000);
@@ -505,7 +507,7 @@ static void ilk_wm_dump(void)
 	if (IS_BROADWELL(devid) || IS_HASWELL(devid))
 		wm_misc = read_reg(0x45260);
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	for (i = 0; i < num_pipes; i++)
 		printf("    WM_PIPE_%c = 0x%08x\n", pipe_name(i), wm_pipe[i]);
@@ -610,6 +612,7 @@ static void ilk_wm_dump(void)
 
 static void vlv_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	unsigned int num_pipes = IS_CHERRYVIEW(devid) ? 3 : 2;
 	uint32_t dsparb, dsparb2, dsparb3;
@@ -619,7 +622,7 @@ static void vlv_wm_dump(void)
 	uint32_t dsp_ss_pm, ddr_setup2;
 	struct gmch_wm wms[MAX_PLANE] = {};
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	dsparb = read_reg(0x70030);
 	dsparb2 = read_reg(0x70060);
@@ -650,13 +653,13 @@ static void vlv_wm_dump(void)
 
 		ddl3 = read_reg(0x70058);
 
-		intel_punit_read(0x36, &dsp_ss_pm);
-		intel_punit_read(0x139, &ddr_setup2);
+		intel_punit_read(&mmio_data, 0x36, &dsp_ss_pm);
+		intel_punit_read(&mmio_data, 0x139, &ddr_setup2);
 	} else {
 		fw7 = read_reg(0x7007c);
 	}
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	printf("        FW1 = 0x%08x\n", fw1);
 	printf("        FW2 = 0x%08x\n", fw2);
@@ -827,6 +830,7 @@ static void vlv_wm_dump(void)
 
 static void g4x_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	uint32_t dspacntr, dspbcntr;
 	uint32_t dsparb;
@@ -835,7 +839,7 @@ static void g4x_wm_dump(void)
 	uint32_t mi_arb_state;
 	struct gmch_wm wms[MAX_PLANE] = {};
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	dspacntr = read_reg(0x70180);
 	dspbcntr = read_reg(0x71180);
@@ -846,7 +850,7 @@ static void g4x_wm_dump(void)
 	mi_display_power_down = read_reg(0x20e0);
 	mi_arb_state = read_reg(0x20e4);
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	printf("             DSPACNTR = 0x%08x\n", dspacntr);
 	printf("             DSPBCNTR = 0x%08x\n", dspbcntr);
@@ -913,6 +917,7 @@ static void g4x_wm_dump(void)
 
 static void gen4_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	int totalsize = IS_CRESTLINE(devid) ? 128 : 96;
 	uint32_t dsparb;
@@ -921,7 +926,7 @@ static void gen4_wm_dump(void)
 	uint32_t mi_arb_state;
 	struct gmch_wm wms[MAX_PLANE] = {};
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	dsparb = read_reg(0x70030);
 	fw1 = read_reg(0x70034);
@@ -930,7 +935,7 @@ static void gen4_wm_dump(void)
 	mi_display_power_down = read_reg(0x20e0);
 	mi_arb_state = read_reg(0x20e4);
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	printf("                  FW1 = 0x%08x\n", fw1);
 	printf("                  FW2 = 0x%08x\n", fw2);
@@ -983,6 +988,7 @@ static void gen4_wm_dump(void)
 
 static void pnv_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	int totalsize = 96; /* FIXME? */
 	uint32_t dsparb;
@@ -992,7 +998,7 @@ static void pnv_wm_dump(void)
 	uint32_t cbr;
 	struct gmch_wm wms[MAX_PLANE] = {};
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	dsparb = read_reg(0x70030);
 	fw1 = read_reg(0x70034);
@@ -1002,7 +1008,7 @@ static void pnv_wm_dump(void)
 	mi_display_power_down = read_reg(0x20e0);
 	mi_arb_state = read_reg(0x20e4);
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	printf("               DSPARB = 0x%08x\n", dsparb);
 	printf("                  FW1 = 0x%08x\n", fw1);
@@ -1073,6 +1079,7 @@ static void pnv_wm_dump(void)
 
 static void gen3_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	int totalsize = IS_945GM(devid) ? 128 : 96; /* FIXME? */
 	uint32_t dsparb;
@@ -1082,7 +1089,7 @@ static void gen3_wm_dump(void)
 	uint32_t mi_arb_state;
 	struct gmch_wm wms[MAX_PLANE] = {};
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	dsparb = read_reg(0x70030);
 	instpm = read_reg(0x20c0);
@@ -1090,7 +1097,7 @@ static void gen3_wm_dump(void)
 	fw_blc_self = read_reg(0x20e0);
 	mi_arb_state = read_reg(0x20e4);
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	printf("      DSPARB = 0x%08x\n", dsparb);
 	printf("      FW_BLC = 0x%016" PRIx64 "\n", fw_blc);
@@ -1142,6 +1149,7 @@ static void gen3_wm_dump(void)
 
 static void gen2_wm_dump(void)
 {
+	struct intel_mmio_data mmio_data;
 	int i;
 	int totalsize;
 	uint32_t dsparb;
@@ -1151,7 +1159,7 @@ static void gen2_wm_dump(void)
 	uint32_t mi_state;
 	struct gmch_wm wms[MAX_PLANE] = {};
 
-	intel_register_access_init(intel_get_pci_device(), 0, -1);
+	intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
 
 	dsparb = read_reg(0x70030);
 	mem_mode = read_reg(0x20cc);
@@ -1159,7 +1167,7 @@ static void gen2_wm_dump(void)
 	fw_blc_self = read_reg(0x20e0);
 	mi_state = read_reg(0x20e4);
 
-	intel_register_access_fini();
+	intel_register_access_fini(&mmio_data);
 
 	printf("     DSPARB = 0x%08x\n", dsparb);
 	printf("   MEM_MODE = 0x%08x\n", mem_mode);