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authorMika Kahola <mika.kahola@intel.com>2019-11-14 11:44:01 +0200
committerImre Deak <imre.deak@intel.com>2019-11-18 11:44:35 +0200
commitfa0f7422409dfa32aa6f0d4eadcd7de28ff7c169 (patch)
treea7b46de1804fbe1b1d032ca08965b56d4f46ab0c /include
parent14d19371610fabafa0ee5a21160373b90ada0a30 (diff)
Format modifier for Intel Gen-12 render compression
Gen-12 has a new compression format for render compression. For this, a new modifier is needed to indicate that. Signed-off-by: Mika Kahola <mika.kahola@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm-uapi/drm_fourcc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 3feeaa3f..b93eb2d4 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -409,6 +409,7 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks