diff options
| author | Jeevan B <jeevan.b@intel.com> | 2022-03-02 20:09:16 +0530 |
|---|---|---|
| committer | Kunal Joshi <kunal1.joshi@intel.com> | 2022-03-09 11:16:34 +0530 |
| commit | ff9b8f21ce93309ed516e2bab2833985abf0de19 (patch) | |
| tree | d867fb65a1bd1133a80ebaf61fcfcbb5559971dc /lib/gpu_cmds.c | |
| parent | 534d00d3ffe1e1f592ba5772a763893d80db1d1e (diff) | |
igt/lib: Add tile 4(F-tile) format support
Introduce support for the new Tile4 format, which is
4K column-major tiles consisting of 64B row-major subtiles,
with same base structure as Y Tile(16B OWords * 4)
v2: place I915_TILING_4 correctly.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Diffstat (limited to 'lib/gpu_cmds.c')
| -rw-r--r-- | lib/gpu_cmds.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c index a45a9048..c31b51f7 100644 --- a/lib/gpu_cmds.c +++ b/lib/gpu_cmds.c @@ -156,7 +156,7 @@ gen8_fill_surface_state(struct intel_bb *ibb, if (buf->tiling == I915_TILING_X) ss->ss0.tiled_mode = 2; - else if (buf->tiling == I915_TILING_Y) + else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4) ss->ss0.tiled_mode = 3; address = intel_bb_offset_reloc(ibb, buf->handle, @@ -211,7 +211,7 @@ gen11_fill_surface_state(struct intel_bb *ibb, if (buf->tiling == I915_TILING_X) ss->ss0.tiled_mode = 2; - else if (buf->tiling == I915_TILING_Y) + else if (buf->tiling == I915_TILING_Y || buf->tiling == I915_TILING_4) ss->ss0.tiled_mode = 3; else ss->ss0.tiled_mode = 0; |