lib/intel_mmio: add additional api for multiple devices

Library  was limited for reading registers for only
one device at a time in igt tests.
Changes in this patch give as oportunity to test multiple devices in
the same time.

v8: pack and rename structure, remove unnecessary field
v7: remove unnecessary code
v6: Reword patch. Cosmetic changes.

Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>

Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 42 insertions, 32 deletions

diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
index 3b5a1370..16862ef4 100644
--- a/lib/intel_iosf.c
+++ b/lib/intel_iosf.c
@@ -19,8 +19,8 @@
 /* Private register write, double-word addressing, non-posted */
 #define SB_CRWRDA_NP   0x07
 
-static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
-			   uint32_t *val)
+static int vlv_sideband_rw(struct intel_mmio_data *mmio_data, uint32_t port,
+			   uint8_t opcode, uint32_t addr, uint32_t *val)
 {
 	int timeout = 0;
 	uint32_t cmd, devfn, be, bar;
@@ -34,22 +34,24 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
 		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
 		(bar << IOSF_BAR_SHIFT);
 
-	if (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+	if (intel_register_read(mmio_data, VLV_IOSF_DOORBELL_REQ) &
+	    IOSF_SB_BUSY) {
 		igt_warn("warning: pcode (%s) mailbox access failed\n", is_read ? "read" : "write");
 		return -EAGAIN;
 	}
 
-	intel_register_write(VLV_IOSF_ADDR, addr);
+	intel_register_write(mmio_data, VLV_IOSF_ADDR, addr);
 	if (!is_read)
-		intel_register_write(VLV_IOSF_DATA, *val);
+		intel_register_write(mmio_data, VLV_IOSF_DATA, *val);
 
-	intel_register_write(VLV_IOSF_DOORBELL_REQ, cmd);
+	intel_register_write(mmio_data, VLV_IOSF_DOORBELL_REQ, cmd);
 
 	do {
 		usleep(1);
 		timeout++;
-	} while (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY &&
-		 timeout < TIMEOUT_US);
+	} while (intel_register_read(mmio_data->igt_mmio,
+				     VLV_IOSF_DOORBELL_REQ) &
+		IOSF_SB_BUSY && timeout < TIMEOUT_US);
 
 	if (timeout >= TIMEOUT_US) {
 		igt_warn("timeout waiting for pcode %s (%d) to finish\n", is_read ? "read" : "write", addr);
@@ -57,8 +59,8 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
 	}
 
 	if (is_read)
-		*val = intel_register_read(VLV_IOSF_DATA);
-	intel_register_write(VLV_IOSF_DATA, 0);
+		*val = intel_register_read(mmio_data->igt_mmio, VLV_IOSF_DATA);
+	intel_register_write(mmio_data->igt_mmio, VLV_IOSF_DATA, 0);
 
 	return 0;
 }
@@ -73,9 +75,10 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_punit_read(uint32_t addr, uint32_t *val)
+int intel_punit_read(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t *val)
 {
-	return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr,
+			       val);
 }
 
 /**
@@ -88,9 +91,10 @@ int intel_punit_read(uint32_t addr, uint32_t *val)
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_punit_write(uint32_t addr, uint32_t val)
+int intel_punit_write(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t val)
 {
-	return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr,
+			       &val);
 }
 
 /**
@@ -103,9 +107,10 @@ int intel_punit_write(uint32_t addr, uint32_t val)
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_nc_read(uint32_t addr, uint32_t *val)
+int intel_nc_read(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t *val)
 {
-	return vlv_sideband_rw(IOSF_PORT_NC, SB_CRRDDA_NP, addr, val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRRDDA_NP, addr,
+			       val);
 }
 
 /**
@@ -118,9 +123,10 @@ int intel_nc_read(uint32_t addr, uint32_t *val)
  * Returns:
  * 0 when the register access succeeded, negative errno code on failure.
  */
-int intel_nc_write(uint32_t addr, uint32_t val)
+int intel_nc_write(struct intel_mmio_data *mmio_data, uint32_t addr, uint32_t val)
 {
-	return vlv_sideband_rw(IOSF_PORT_NC, SB_CRWRDA_NP, addr, &val);
+	return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRWRDA_NP, addr,
+			       &val);
 }
 
 /**
@@ -133,14 +139,16 @@ int intel_nc_write(uint32_t addr, uint32_t val)
  * Returns:
  * The value read from the register.
  */
-uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
+uint32_t intel_dpio_reg_read(struct intel_mmio_data *mmio_data, uint32_t reg, int phy)
 {
 	uint32_t val;
 
 	if (phy == 0)
-		vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MRD_NP, reg,
+				&val);
 	else
-		vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MRD_NP, reg,
+				&val);
 	return val;
 }
 
@@ -152,38 +160,40 @@ uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
  *
  * 32-bit write of the register at @offset through the DPIO sideband port.
  */
-void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
+void intel_dpio_reg_write(struct intel_mmio_data *mmio_data, uint32_t reg, uint32_t val, int phy)
 {
 	if (phy == 0)
-		vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
 	else
-		vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val);
+		vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MWR_NP, reg,
+				&val);
 }
 
-uint32_t intel_flisdsi_reg_read(uint32_t reg)
+uint32_t intel_flisdsi_reg_read(struct intel_mmio_data *mmio_data, uint32_t reg)
 {
 	uint32_t val = 0;
 
-	vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
 
 	return val;
 }
 
-void intel_flisdsi_reg_write(uint32_t reg, uint32_t val)
+void intel_flisdsi_reg_write(struct intel_mmio_data *mmio_data, uint32_t reg, uint32_t val)
 {
-	vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
 }
 
-uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg)
+uint32_t intel_iosf_sb_read(struct intel_mmio_data *mmio_data, uint32_t port, uint32_t reg)
 {
 	uint32_t val;
 
-	vlv_sideband_rw(port, SB_CRRDDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, port, SB_CRRDDA_NP, reg, &val);
 
 	return val;
 }
 
-void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val)
+void intel_iosf_sb_write(struct intel_mmio_data *mmio_data, uint32_t port,
+			 uint32_t reg, uint32_t val)
 {
-	vlv_sideband_rw(port, SB_CRWRDA_NP, reg, &val);
+	vlv_sideband_rw(mmio_data, port, SB_CRWRDA_NP, reg, &val);
 }