diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-09-09 17:20:43 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-10-11 15:46:26 +0300 |
| commit | 1fccf9f6791b5a5bfde0f8df12d6212d168d3c7b (patch) | |
| tree | 55618fe120429d739ba3138dd907f49427b0432f /lib/intel_reg.h | |
| parent | f54bf8f4a5fc0a77ce80dc5d1018a2084f0a7352 (diff) | |
tools/intel_display_poller: Add async flip test mode
Test various things using mmio async flips. These are present since
g4x, except g4x does not seem to have a working flipdone interrupt.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'lib/intel_reg.h')
| -rw-r--r-- | lib/intel_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/intel_reg.h b/lib/intel_reg.h index ab01a283..0590aa93 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -2330,6 +2330,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PIPEEDPCONF 0x7F008 +#define DSPAADDR_VLV 0x7017C /* vlv/chv */ +#define DSPBADDR_VLV 0x7117C /* vlv/chv */ +#define DSPCADDR_CHV 0x7417C /* chv */ #define DSPACNTR 0x70180 #define DSPBCNTR 0x71180 #define DSPCCNTR 0x72180 |