i915/gem_exec_balancer: Test parallel execbuf

Add basic parallel execbuf submission test which more or less just
submits the same BB in loop a which does an atomic increment to a memory
location. The memory location is checked at the end for the correct
value. Different sections use various IOCTL options (e.g. fences,
location of BBs, etc...).

In addition to above sections, an additional section ensure the ordering
of parallel submission by submitting a spinning batch to 1 individual
engine, submit a parallel execbuf to all engines instances within the
class, verify none on parallel execbuf make to hardware, release
spinner, and finally verify everything has completed.

The parallel-ordering section assumes default timeslice / preemption
timeout values. If these values are changed the test may fail.

v2:
 (Daniele)
  - Add assert to ensure parallel & load_balance both not set in ctx lib
  - s/count/expected/g in check_bo()
  - use existing query library functions
  - clean up bb_per_execbuf / count usage
  - drop dead loop
  - add comment for parallel-ordering
  - don't declare loop variables inside loop
v3:
 (Daniele)
  - Read timeslice from sysfs
v4:
 (Daniele)
  - Add comment in timeslice sysfs function

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index c447525a..44b0d480 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2642,6 +2642,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define STATE3D_COLOR_FACTOR	((0x3<<29)|(0x1d<<24)|(0x01<<16))
 
+/* Atomics */
+#define MI_ATOMIC			((0x2f << 23) | 2)
+#define   MI_ATOMIC_INLINE_DATA         (1 << 18)
+#define   MI_ATOMIC_ADD                 (0x7 << 8)
+
 /* Batch */
 #define MI_BATCH_BUFFER		((0x30 << 23) | 1)
 #define MI_BATCH_BUFFER_START	(0x31 << 23)