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authorJeevan B <jeevan.b@intel.com>2022-05-16 20:38:24 +0530
committerKunal Joshi <kunal1.joshi@intel.com>2022-05-17 22:37:51 +0530
commit70cfef35851891aeaa829f5e8dcb7fd43b454bde (patch)
tree0fb61d32169b347acd7f59a6ba5771364f609e1d /lib
parent08aa9296163b94cf4c529fc890ae3e90e21c3cdb (diff)
lib/intel_batchbuffer: Fix typo from src_tiling to dst_tiling
fix typo to avoid CRC mismatch for tile-4 tests Signed-off-by: Jeevan B <jeevan.b@intel.com> Fixes: ff9b8f21ce93 ("igt/lib: Add tile 4(F-tile) format support") Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'lib')
-rw-r--r--lib/intel_batchbuffer.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ebf3c598..8680c9ba 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -658,7 +658,7 @@ static uint32_t fast_copy_dword1(unsigned int src_tiling,
if (src_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
/* Repurposed as Tile-4 on DG2 */
dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
- if (dst_tiling == I915_TILING_Yf || src_tiling == I915_TILING_4)
+ if (dst_tiling == I915_TILING_Yf || dst_tiling == I915_TILING_4)
/* Repurposed as Tile-4 on DG2 */
dword1 |= XY_FAST_COPY_DST_TILING_Yf;