diff options
| author | Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> | 2022-06-10 09:07:48 +0200 |
|---|---|---|
| committer | Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> | 2022-06-13 17:28:24 +0200 |
| commit | 899ff3663841eba92aa503d760b5d316b2e972df (patch) | |
| tree | c0ed2019c11bc61fba4e2579f7753efd53c0fb4d /lib | |
| parent | dfc7ef0b191b45056a6006555cf0a70ae55886d8 (diff) | |
lib/intel_reg: Add common MI_* macros to remove duplicates
In few tests we got some MI_* duplicates (MI_MATH for example).
Add common definitions in intel_reg.h and remove local definitions
in the tests.
v2: Definitions MI_LOAD_REGISTER_MEM_GEN8 was removed so from now
on user will need to encode length on it own. :
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/intel_aux_pgtable.c | 4 | ||||
| -rw-r--r-- | lib/intel_reg.h | 47 |
2 files changed, 48 insertions, 3 deletions
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index e31a6c34..7556351a 100644 --- a/lib/intel_aux_pgtable.c +++ b/lib/intel_aux_pgtable.c @@ -644,11 +644,11 @@ gen12_emit_aux_pgtable_state(struct intel_bb *ibb, uint32_t state, bool render) if (!state) return; - intel_bb_out(ibb, MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12); + intel_bb_out(ibb, MI_LOAD_REGISTER_MEM | MI_MMIO_REMAP_ENABLE_GEN12 | 2); intel_bb_out(ibb, table_base_reg); intel_bb_emit_reloc(ibb, ibb->handle, 0, 0, state, ibb->batch_offset); - intel_bb_out(ibb, MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12); + intel_bb_out(ibb, MI_LOAD_REGISTER_MEM | MI_MMIO_REMAP_ENABLE_GEN12 | 2); intel_bb_out(ibb, table_base_reg + 4); intel_bb_emit_reloc(ibb, ibb->handle, 0, 0, state + 4, ibb->batch_offset); } diff --git a/lib/intel_reg.h b/lib/intel_reg.h index e26ee82a..e4d1f1c2 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -2623,8 +2623,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define MI_LOAD_SCAN_LINES_INCL (0x12<<23) #define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1) -#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2)) +#define MI_LOAD_REGISTER_REG ((0x2A << 23) | 1) +#define MI_LOAD_REGISTER_MEM (0x29 << 23) +#define MI_CS_MMIO_DST (1 << 19) +#define MI_CS_MMIO_SRC (1 << 18) #define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17) +#define MI_WPARID_ENABLE_GEN12 (1 << 16) +#define MI_STORE_REGISTER_MEM (0x24 << 23) +#define MI_STORE_PREDICATE_ENABLE_GEN12 (1 << 21) /* Flush */ #define MI_FLUSH (0x04<<23) @@ -2642,6 +2648,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define MI_NOOP_WRITE_ID (1<<22) #define MI_NOOP_ID_MASK (1<<22 - 1) +/* ARB Check */ +#define MI_ARB_CHECK (0x5 << 23) + #define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16)) /* Atomics */ @@ -2657,12 +2666,48 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/ #define MI_BATCH_BUFFER_END (0xA << 23) #define MI_COND_BATCH_BUFFER_END (0x36 << 23) +#define MAD_GT_IDD (0 << 12) +#define MAD_GT_OR_EQ_IDD (1 << 12) +#define MAD_LT_IDD (2 << 12) +#define MAD_LT_OR_EQ_IDD (3 << 12) +#define MAD_EQ_IDD (4 << 12) +#define MAD_NEQ_IDD (5 << 12) #define MI_DO_COMPARE (1 << 21) #define MI_BATCH_NON_SECURE (1) #define MI_BATCH_NON_SECURE_I965 (1 << 8) #define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */ +/* Math */ +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* DG2+ */ +#define MI_MATH_SHL MI_MATH_INSTR(0x105, 0x0, 0x0) +#define MI_MATH_SHR MI_MATH_INSTR(0x106, 0x0, 0x0) +#define MI_MATH_SAR MI_MATH_INSTR(0x107, 0x0, 0x0) + +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + #define MAX_DISPLAY_PIPES 2 typedef enum { |