diff options
author | Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> | 2020-09-11 10:07:24 +0200 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-09-16 14:15:22 +0100 |
commit | a86802d988c1aeda34ac2911200213a48b934117 (patch) | |
tree | 12c07e1c0bca8cefc3a3e71e3ee5551722a35f1a /tests/i915/api_intel_bb.c | |
parent | a13282d661bb5af9e6aa61317924b340b0a650e8 (diff) |
lib/intel_batchbuffer: use canonical addresses for 48bit ppgtt
For all EXEC_OBJECT_PINNED objects we need to be sure address
passed must be in canonical form.
Until IGT allocator will be written just limit 48 and 47 bit
gtt tables to 46 bit only. We don't want to play with canonical
addresses with 47-bit set to 1 (and then 63:48).
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tests/i915/api_intel_bb.c')
-rw-r--r-- | tests/i915/api_intel_bb.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c index cf7f6e91..d0c182fd 100644 --- a/tests/i915/api_intel_bb.c +++ b/tests/i915/api_intel_bb.c @@ -165,6 +165,47 @@ static void simple_bb(struct buf_ops *bops, bool use_context) gem_context_destroy(i915, ctx); } +/* + * Make sure intel-bb space allocator currently doesn't enter 47-48 bit + * gtt sizes. + */ +static void check_canonical(struct buf_ops *bops) +{ + int i915 = buf_ops_get_fd(bops); + struct intel_bb *ibb; + struct intel_buf *buf; + uint32_t offset; + uint64_t address; + bool supports_48bit; + + ibb = intel_bb_create(i915, PAGE_SIZE); + supports_48bit = ibb->supports_48b_address; + if (!supports_48bit) + intel_bb_destroy(ibb); + igt_require_f(supports_48bit, "We need 48bit ppgtt for testing\n"); + + address = 0xc00000000000; + if (debug_bb) + intel_bb_set_debug(ibb, true); + + offset = intel_bb_emit_bbe(ibb); + + buf = intel_buf_create(bops, 512, 512, 32, 0, + I915_TILING_NONE, I915_COMPRESSION_NONE); + + buf->addr.offset = address; + intel_bb_add_intel_buf(ibb, buf, true); + intel_bb_object_set_flag(ibb, buf->handle, EXEC_OBJECT_PINNED); + + igt_assert(buf->addr.offset == 0); + + intel_bb_exec(ibb, offset, + I915_EXEC_DEFAULT | I915_EXEC_NO_RELOC, true); + + intel_buf_destroy(buf); + intel_bb_destroy(ibb); +} + #define MI_FLUSH_DW (0x26<<23) #define BCS_SWCTRL 0x22200 #define BCS_SRC_Y (1 << 0) @@ -673,6 +714,9 @@ igt_main_args("dpi", NULL, help_str, opt_handler, NULL) igt_subtest("simple-bb-ctx") simple_bb(bops, true); + igt_subtest("check-canonical") + check_canonical(bops); + igt_subtest("blit-noreloc-keep-cache") blit(bops, NORELOC, KEEP_CACHE); |