diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-21 10:45:26 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-02-28 22:09:09 +0000 |
| commit | f6809084b1217b5f0b3b6487099b0a86ffb5f8c0 (patch) | |
| tree | 936c318096230ed379d9b844de738f0fa9c3915f /tests/i915/gem_exec_latency.c | |
| parent | 3fe5828f45fc533ba4d9ee84dbb5aea320ce61bc (diff) | |
i915: Start putting the mmio_base to wider use
Several tests depend upon the implicit engine->mmio_base but have no
means of determining the physical layout. Since the kernel has started
providing this information, start putting it to use.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Diffstat (limited to 'tests/i915/gem_exec_latency.c')
| -rw-r--r-- | tests/i915/gem_exec_latency.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c index 3d99182a..d2159f31 100644 --- a/tests/i915/gem_exec_latency.c +++ b/tests/i915/gem_exec_latency.c @@ -109,7 +109,7 @@ poll_ring(int fd, unsigned ring, const char *name) igt_spin_free(fd, spin[0]); } -#define RCS_TIMESTAMP (0x2000 + 0x358) +#define TIMESTAMP (0x358) static void latency_on_ring(int fd, unsigned ring, const char *name, unsigned flags) @@ -119,6 +119,7 @@ static void latency_on_ring(int fd, struct drm_i915_gem_exec_object2 obj[3]; struct drm_i915_gem_relocation_entry reloc; struct drm_i915_gem_execbuffer2 execbuf; + const uint32_t mmio_base = gem_engine_mmio_base(fd, name); igt_spin_t *spin = NULL; IGT_CORK_HANDLE(c); volatile uint32_t *reg; @@ -128,7 +129,8 @@ static void latency_on_ring(int fd, double gpu_latency; int i, j; - reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + RCS_TIMESTAMP); + igt_require(mmio_base); + reg = (volatile uint32_t *)((volatile char *)igt_global_mmio + mmio_base + TIMESTAMP); memset(&execbuf, 0, sizeof(execbuf)); execbuf.buffers_ptr = to_user_pointer(&obj[1]); @@ -176,7 +178,7 @@ static void latency_on_ring(int fd, map[i++] = 0x24 << 23 | 1; if (has_64bit_reloc) map[i-1]++; - map[i++] = RCS_TIMESTAMP; /* ring local! */ + map[i++] = mmio_base + TIMESTAMP; map[i++] = offset; if (has_64bit_reloc) map[i++] = offset >> 32; @@ -266,11 +268,14 @@ static void latency_from_ring(int fd, struct drm_i915_gem_exec_object2 obj[3]; struct drm_i915_gem_relocation_entry reloc; struct drm_i915_gem_execbuffer2 execbuf; + const uint32_t mmio_base = gem_engine_mmio_base(fd, name); const unsigned int repeats = ring_size / 2; uint32_t *map, *results; uint32_t ctx[2] = {}; int i, j; + igt_require(mmio_base); + if (flags & PREEMPT) { ctx[0] = gem_context_create(fd); gem_context_set_priority(fd, ctx[0], -1023); @@ -351,7 +356,7 @@ static void latency_from_ring(int fd, map[i++] = 0x24 << 23 | 1; if (has_64bit_reloc) map[i-1]++; - map[i++] = RCS_TIMESTAMP; /* ring local! */ + map[i++] = mmio_base + TIMESTAMP; map[i++] = offset; if (has_64bit_reloc) map[i++] = offset >> 32; @@ -376,7 +381,7 @@ static void latency_from_ring(int fd, map[i++] = 0x24 << 23 | 1; if (has_64bit_reloc) map[i-1]++; - map[i++] = RCS_TIMESTAMP; /* ring local! */ + map[i++] = mmio_base + TIMESTAMP; map[i++] = offset; if (has_64bit_reloc) map[i++] = offset >> 32; @@ -669,7 +674,7 @@ igt_main ring_size = 1024; intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device); - rcs_clock = clockrate(device, RCS_TIMESTAMP); + rcs_clock = clockrate(device, 0x2000 + TIMESTAMP); igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n", rcs_clock / 1e3, 1e9 / rcs_clock); rcs_clock = 1e9 / rcs_clock; |