diff options
| author | Ramalingam C <ramalingam.c@intel.com> | 2019-11-20 18:54:01 +0530 |
|---|---|---|
| committer | Ramalingam C <ramalingam.c@intel.com> | 2019-11-20 23:44:20 +0530 |
| commit | 65fed6a79adea14f7bef6d55530da47d7731d370 (patch) | |
| tree | bb4cc97b2101a498057350d708e132823ca14e5d /tests/i915/gem_workarounds.c | |
| parent | a19df6f52812517a4a84e6e630506512575b10da (diff) | |
tests/i915/WA: Mark FF_MODE2 as WO for TGL
On TGL till B0 stepping FF_MODE2(0x6604) register is not readable. But
we need to program this register for Wa_1604555607 for better
performance. Hence to skip the verification attempt on this register
through read, we are marking this register as write only.
As of now I have marked this register as write only for gen12, we can
narrow it down to TGL <= B0, if we can retrieve the stepping of the
platform at IGT.
v2:
comma is added [Chris]
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tests/i915/gem_workarounds.c')
| -rw-r--r-- | tests/i915/gem_workarounds.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c index dd6316ea..02c1f9d5 100644 --- a/tests/i915/gem_workarounds.c +++ b/tests/i915/gem_workarounds.c @@ -51,8 +51,8 @@ static struct write_only_list { unsigned int gen; uint32_t addr; } wo_list[] = { - { 10, 0xE5F0 } /* WaForceContextSaveRestoreNonCoherent:cnl */ - + { 10, 0xE5F0 }, /* WaForceContextSaveRestoreNonCoherent:cnl */ + { 12, 0x6604 }, /* FIXME: Stepping > B0 might be readable */ /* * FIXME: If you are contemplating adding stuff here * consider this as a temporary solution. You need to |