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2013-03-04assembler: Add a check for when width is 1 and hstride is not 0Damien Lespiau
The list of region restrictions in bspec do say that we can't have: width == 1 && hstrize != 0 We do have plenty of assembly code that don't respect that behaviour. So let's hide the warning under a -W flag (for now) while we fix things. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add error() and warn() shorthands and use them in set_src[01]Damien Lespiau
Now that we have locations, we can write error() and warn() functions giving more information about where it's going wrong. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add location supportDamien Lespiau
Let's generate location information about the tokens we are parsing. This can be used to give accurate location when reporting errors and warnings. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't warn if identical declared registers are redefinedDamien Lespiau
There's no real need to warn when the same register is declared twice. Currently the libva driver does do that and this warning makes other errors really hide in a sea of warnings. Redefining a register with different parameters is a real error though, so we should not allow that and error out in that case. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Store immediate values in reg.dw1.udDamien Lespiau
Another step in pushing the parsing in struct brw_reg. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Factor out the source register validationDamien Lespiau
The goal is to use brw_set_src[01](), so let's start by validating the register we have before generating the opcode. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_set_dest() to encode the destinationDamien Lespiau
A few notes: I needed to introduce a brw context and compile structs. These are only used to get which generation we are compiling code for, but eventually we can use more of the infrastructure. brw_set_dest() uses the destination register width to program the instruction execution size. The assembler can either take subnr in bytes or in number of elements, so we need a resolve step when setting a brw_reg. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Factor out the destination register validationDamien Lespiau
The goal is to use brw_set_dest(), so let's start by validating the register we have before generating the opcode. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_reg in the source operandDamien Lespiau
Last refactoring step in transition to struct brw_reg. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Get rid of src operand's swizzle_setDamien Lespiau
swizzle_set can be derived from the value of swizzle itself, no need for that field. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Consolidate the swizzling configuration on 8 bitsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct dst_operand by struct brw_regDamien Lespiau
One more step on the road to replacing all register-like structures by struct brw_reg. Two things in this commit are worth noting: * As we are using more and more brw_reg, a lot of the field-by-field assignments can be replaced by 1 assignment which results is a reduction of code * As the destination horizontal stride is now stored on 2 bits in brw_reg, it's not possible to defer the handling of DEFAULT_DSTREGION (aka (int)-1) when setting the destination operand. It has to be done when parsing the region and resolve_dst_region() is a helper for that task. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Unify the direct and indirect register typeDamien Lespiau
They are all struct brw_reg registers now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct indirect_reg by struct brw_regDamien Lespiau
More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct direct_reg by struct brw_regDamien Lespiau
More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Make struct declared_register use struct brw_regDamien Lespiau
It's time to start converting the emission code in gram.y to use libbrw infrastructure. Let's start with using brw_reg for declared register. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't change the size of opcodes!Damien Lespiau
Until now, the assembler had relocation-related fields added to struct brw_instruction. This changes the size of the structure and break code assuming the opcode structure is really 16 bytes, for instance the emission code in brw_eu_emit.c. With this commit, we build on the infrastructure that slowly emerged in the few previous commits to add a relocatable instruction with the needed fields. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Make explicit that labels are part of the instructions listDamien Lespiau
The output of the parsing is a list of struct brw_program_instruction. These instructions can be either GEN instructions aka struct brw_instruction or labels. To make this more explicit we now have a type to test to determine which instruction we are dealing with. This will also allow to to pull the relocation bits into struct brw_program_instruction instead of having them in the structure representing the opcodes. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Refactor the code adding instructions and labelsDamien Lespiau
Factoring out the code from the grammar will allow us to switch to using brw_compile in a cleaner way. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Simplify get_subreg_address()Damien Lespiau
This function can only be called to resolve subreg_nr in direct mode (there is an other function for the indirect case) and it makes no sense to call it with an immediate operand. Express those facts with asserts and simplify the logic. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use subreg_nr to store the address register subregDamien Lespiau
Another step towards using struct brw_reg for source and destination operands. Instead of having a separate field to store the sub register number of the address register in indirect access mode, we can reuse the subreg_nr field that was only used for direct access so far. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove the writemask_set field of struct dest_operandDamien Lespiau
writemask_set gets in the way of switching to using struct brw_reg and it's possible to derive it from the writemask value. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use BRW_WRITEMASK_XYZW instead of the 0xf constantDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename BRW_ACCWRCTRL_ACCWRCTRLDamien Lespiau
To a more self-describing define. This hopefully will help its inclusion into Mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Adopt enum brw_message_target from mesaDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename gen5 DP pixel_scoreboard_clear to last_render_targetDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove struct dp_write_gen6 and struct use gen6_dpDamien Lespiau
We ended up with 2 structures that where exactly the same, so just use one, which happens to be the one Mesa has. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename dp_gen7 to gen7_dp and sync it with Mesa'sDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. I had to drop how mesa splits msg_control as the current assembly language gives access the the whole msg_control field. Recompiling the xorg and the intel driver of libva shaders doesn't show any difference in the assembly created. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename dp_gen6 to gen6_dp and sync with Mesa'sDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. I had to drop how mesa splits msg_control as the current assembly language gives access the the whole msg_control field. Recompiling the xorg and the intel driver of libva shaders doesn't show any difference in the assembly created. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename dp_read_gen6 to gen6_dp_sampler_const_cacheDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename three_src_gen6 to da3srcDamien Lespiau
Mesa's brw_structs.h has named/renamed this field to da3src. Sync with them. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Sync brw_instruction's header with mesa'sDamien Lespiau
Two changes there, a field has been renamed and one bit of padding is now used for compressed instructions. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04build: Integrate the merged gen assembler in the build systemDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04Add autotools build system, and rearrange directory layout.Eric Anholt
2013-03-04Add support for register-indirect addressing in source operands.Eric Anholt
2013-03-04Add support for register-indirect access in destination registers.Eric Anholt
This is untested. Also, a few bits for source operand register-indirect access sneak in with this commit.
2013-03-04Add support for destination writemasks.Eric Anholt
This involved changing dest operands to have their own structure like src operands, as the destination writemask (which is align16-only) shares space with register numbers in align1 mode.
2013-03-04Avoid shift/reduce conflict in predicate by making flagreg and subreg 1 token.Eric Anholt
Thanks to keithp for pointing out where the conflict was.
2013-03-04Add support for predicate control.Eric Anholt
This is untested on programs using predicate control, and also causes a shift/reduce conflict.
2013-03-04Add support for swizzle control on source operands.Eric Anholt
This required restructuring to store source operands in a new structure rather than being stored in instructions, as swizzle is align16-only and shares storage with other fields for align1 mode. These changes were not tested on real programs using swizzle.
2013-03-04Add acc[01] as src operands.Eric Anholt
2013-03-04Comment cleanup and add missing semicolons after rules.Eric Anholt
2013-03-04Add support for more instruction options.Eric Anholt
2013-03-04Typo fix in comment.Eric Anholt
2013-03-04Rename direct_gen_reg struct to direct_reg now that it fills more roles.Eric Anholt
2013-03-04Support src ARF operands in another place, and spell it arch instead of acc.Eric Anholt
2013-03-04Add support for more registers as source operands.Eric Anholt
2013-03-04Add rules for more registers, and use some for destinations.Eric Anholt
2013-03-04Add many more opcodes.Eric Anholt
2013-03-04Lex the register number with the register name.Eric Anholt
This avoids the need for a start condition to prevent for example g1.8<0,1,0>UW being lexed as GENREG NUMBER LANGLE etc. rather than GENREG INTEGER DOT INTEGER LANGLE etc.
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