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2017-10-02benchmarks: Add wsim files to distPetri Latvala
Signed-off-by: Petri Latvala <petri.latvala@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-06-08gem_wsim: More interesting workloadsTvrtko Ursulin
These ones demonstrate fence usage and also mixing them with data dependencies. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-06-08gem_wsim: Add some randomness to the 17i7 workloadTvrtko Ursulin
It was the only one with no randomness. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-06-08gem_wsim: Asymmetrical 1-to-n workloadsTvrtko Ursulin
Simulates a single decoder feeding multiple processing and encoding pipelines. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-05-16gem_wsim: Implement sw sync point supportTvrtko Ursulin
Two new workload commands are added, 'f' and 'q.<idx>' which enable creation and signalling of non i915 fences. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-05-16gem_wsim: Fence supportTvrtko Ursulin
Add sync fence dependency support to workload steps. Only one sync fence dependency per step is supported at the moment. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-05-08gem_wsim: More simulated transcoding workloadsTvrtko Ursulin
hd06mp2, hd12: Want many parallel clients (20+) and lets itself be balanced. fhd26u7, 4k12u7: Simulates either encoder or decoder with VCS1 (HEVC) dependency and some balancing VCS usage. Needs fewer clients (3-6). hd01, hd17i4: Mostly RCS limited targetting maximum execution speed for a single client. Must not be hampered by incorrect balancing decisions. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-05-08gem_wsim: Support multiple dependenciesTvrtko Ursulin
Multiple dependencies separated by forward slashes are now supported. Some media workloads also updated to use this for better efficiency. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-05-05gem_wsim: Add some generic media workloadsTvrtko Ursulin
Workloads generated from a high level description of how things usually work in the transcoding world. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2017-04-25benchmarks/gem_wsim: Command submission workload simulatorTvrtko Ursulin
Tool which emits batch buffers to engines with configurable sequences, durations, contexts, dependencies and userspace waits. Unfinished but shows promise so sending out for early feedback. v2: * Load workload descriptors from files. (also -w) * Help text. * Calibration control if needed. (-t) * NORELOC | LUT to eb flags. * Added sample workload to wsim/workload1. v3: * Multiple parallel different workloads (-w -w ...). * Multi-context workloads. * Variable (random) batch length. * Load balancing (round robin and queue depth estimation). * Workloads delays and explicit sync steps. * Workload frequency (period) control. v4: * Fixed queue-depth estimation by creating separate batches per engine when qd load balancing is on. * Dropped separate -s cmd line option. It can turn itself on automatically when needed. * Keep a single status page and lie about the write hazard as suggested by Chris. * Use batch_start_offset for controlling the batch duration. (Chris) * Set status page object cache level. (Chris) * Moved workload description to a README. * Tidied example workloads. * Some other cleanups and refactorings. v5: * Master and background workloads (-W / -w). * Single batch per step is enough even when balancing. (Chris) * Use hars_petruska_f54_1_random IGT functions and see to zero at start. (Chris) * Use WC cache domain when WC mapping. (Chris) * Keep seqnos 64-bytes apart in the status page. (Chris) * Add workload throttling and queue-depth throttling commands. (Chris) v6: * Added two more workloads. * Merged RT balancer from Chris. v7: * Merged NO_RELOC patch from Chris. * Added missing RT balancer to help text. TODO list: * Fence support. * Batch buffer caching (re-use pool). * Better error handling. * Less 1980's workload parsing. * More workloads. * Threads? * ... ? Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: "Rogozhkin, Dmitry V" <dmitry.v.rogozhkin@intel.com>