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[why & how]
AMDGPU DM exposure a debugfs interface entry of visual confirm
debug option which is configured for debugging like surface
programming. It also supports the PSR feature visual confirm
debugging. We'd add helpers to read/write visual confirm debug
option from/to such interface entry.
The interface entry "amdgpu_dm_visual_confirm" is located in the
debugfs directory. We'd add the enumeration of visual confirm
option which is aligned to the amdgpu kernel driver.
Changes in v2:
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- close the file descriptor before return in helper of setting
visual confirm
- drop the '_dm_' from helpers to check visual confirm debugfs
existence, get/set option from/to the debugfs entry.
Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
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[why]
We need a test case to imitate the multiplane overlay (MPO) video
playback use case and check PSR-SU enablement during test run.
[how]
The test run only works for PSR-SU capable sink device and skip for
any non-eDP or non-PSR-SU connector or kernel driver not supporting
PSR-SU feature.
To emulate the video playback and MPO scenario, we use overlay plane
w/ size of addressable and primary plane w/ size of quater of overlay
acting as video playback region.
Create couple of framebuffers w/ size of primary plane and with
the pattern of vertical color strip on different position on the
FB. During test run, we flip the primary framebuffer and expect the
visual effect of moving strip within the region of primary plane
acting as video playback. The primary plane during test run is not
moving position or resizing.
changes in v3
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* make the indentation consistent to use tabs
* newline after for loop for readability
Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
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[why]
For AMDGPU devices, we'd check the PSR state via reading from the
debugfs interface for a given eDP connector, where the debugfs
interface path locates at
<debugfs_root>/dri/0/eDP-X/psr_state
where 'X' is the eDP connector index.
[how]
define and add the helper to check if PSR state debugfs interface
is supported in driver, and the helper to read PSR state from the
debugfs interface.
Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
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[why]
For AMDGPU devices, the debugfs interface to check sink PSR cap
is a bit different from that of i915, i.e. the interface is located
in the path
<debugfs_root>/dri/0/eDP-X/psr_capability
where 'X' is eDP connector index.
We need such debugfs interface to check if the sink device and the
x86 driver supports PSR or PSR-SU capabilities.
[how]
define and add the helpers to read from connector debugfs interface
For sink device PSR cap check:
- for PSR1 device, the psr version DPCD be 0x1
- for PSR-SU device, the psr version DPCD be either 0x3 or 0x4.
For amdgpu x86 driver PSR support check:
- for PSR1, expect to contain sub-string "yes"
- for PSR-SU, expect to contain sub-string "yes [0x1]"
changes in v2
-------------------
* fix the typo in string comp within the helper to read from
psr cap debugfs interface
Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
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[Why & How]
Add new igt test amd_ilr for ilr fature.
ILR (Intermediate Link Rate) is the feature introduced in eDP1.4.
For saving power purpose, it provides finer granularity of link
rates to optimize the allocated bandwidth needed for resolutions of
eDP panels.
This new igt test "amd_ilr" validates ILR feature from two perspective:
* Test if we can sucessfully train link rate at all supported ILRs
* Iterate over all modes to see if we do use ILR to optimize the link
rate to light up the mode.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
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This commit adds a DP DSC test that checks:
* Forces DSC on/off and ensures it is reset properly
* Check DSC slice height property
* Verify various DSC slice dimensions
* Tests various combinations of link_rate + lane_count and logs if DSC
enabled/disabled Tests different bpc settings and logs if DSC is
enabled/disabled
Change since V3:
- Drop useless test
Change since V2:
- Remove IGT_CRTC_DSC_SLICE_HEIGHT crtc property from this commit
Change since V1:
- Rebase
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Choi <Nicholas.Choi@amd.com>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Hayden Goodfellow <hayden.goodfellow@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Roman Li <roman.li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
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[Why]
Having a test that iterates through different link
settings and performs link training with them is useful
and currently missing from IGT.
[How]
Add a link settings test and its required helper functions.
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
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[Why]
There is a debugfs entry to trigger software hotplugs. We can use this
for IGT tests.
[How]
Add hotplug test for all connectors, hotplug after suspend.
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
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Allow amdgpu to run HW rotation IGT test case
Added conditions to bypass all the requirements needed for intel when testing amdgpu.
Additionally, freed unused frame buffers.
Added swizzle 64kb tiling method for amdgpu-specific.
Updated drm header for amdgpu tiling modifiers.
v2: drm_fourcc.h copied from kernel header commit:8ba16d5993749c3f31fd2b49e16f0dc1e1770b9c from drm-next.
removed igt_pipe_crc_collect_crc for intel gpu. Only on AMDGPU.
v3: moved drm_fourcc.h to another patch.
Removed creating redundant fb in prepare_crtc for amdgpu.
Guarded display commit for amdgpu.
Blocked cursor plane rotation for amdgpu.
Added back tiling when creating reference fb.
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Reviewed by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
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The kmstest_dumb_create API isn't suitable for creating multi-planar
buffers since it tries to calculate the size based on the first plane's
pitch only.
AMDGPU requires that the luma pitch be aligned to 256 for YUV buffers
which results in crashes on kms_plane@pixel-format-pipe-*-planes tests
when using kmstest_dumb_create since the buffer returned is smaller than
needed (16384 size returned, 24576 size required).
Create and map the buffer with the correct size by using the AMD helpers
introduced by this patch: igt_amd_create_bo and igt_amd_mmap_bo.
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
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