Age | Commit message (Collapse) | Author |
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Add support for DG2 flat ccs framebuffers with tile-4.
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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The present gen12 rendercopy is not compatible with gen21p71(dg2).
Add rendercopy support for dg2 and introduce gen12p71_render_copyfunc
function to use it.
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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1. In _gen9_render_op, check if the incoming batchbuffer
is marked with pxp enabled. If so, insert MI_SET_APPID
along with PIPE_CONTROL instructions at the start and
end of the rendering operation in the command buffer.
2. The two PIPE_CONTROLs will enable protected memory
at the start of the batch and disabling protected
memory at the end of it. These PIPE_CONTROLs require a
Post-Sync operation with a write to memory for hardware
to accept.
3. In order to satisfy #2, _gen9_render_op uses unused
regions of the ibb buffer for the PIPE_CONTROL PostSync
write to memory (no different from how other 3d states
are being referenced).
4. _gen9_render_op shall check the incoming surface
buffers for "is_protected" flag and if its set, it
will mark the SURFACE_STATE's MOCS field accordingly.
NOTE: _gen9_render_op needs to program the HW to enable
the PXP session as part of the rendering batch buffer
because the HW requires that enabling/disabling protected
memory access must be programmed in pairs within the same
"dispatch of rendering commands" to HW.
Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Gen12 onward platforms does not support coachability via PTE.
So I915_MOCS_PTE( index 1) may point to unspecified/reserved or some
other coachability MOCS index. This may leads to data corruption.
A helper function has been added to provide UC MOCS index based
on platform.
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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To ensure to cover all destination area during fast clear,
we need to round up the destination coordinates at the lower
right corner.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Enable fast clear rendering on rendercopy function.
v2: Modify _gen9_render_copyfunc to support fast clear (Matt)
Enable fast clear bit on 3D sequence (Matt)
Add helper function to figure out clear color modifier (Matt)
v3: Remove unrelated line additions/removes
v4: Fast clear with color (Imre)
v5: Write raw 32-bit color values to register (Imre)
Require 32-bit color format
v6: Rebase to use batchbuffer without libdrm dependency
v7: Enable clear color (Nanley)
v8: Various cleanups (Imre)
Modificate buffer creation (Imre)
v9: Renaming of render_copyfunc() to render_op() (Imre)
Remove igt_render_clearfunc variable (Imre)
v10: Dst buffer width division by 64 pixels and height by 16 lines (Imre)
Reorder ss10 bit fields (Imre)
Relocate buffer with clear color value enabled (Imre)
Set fast clear enable bit in correct dword (Imre)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
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With upcoming of allocator code we need to ensure batch will execute
with appropriate context. If mismatch between allocator data and batch
could lead to strange or wrong results. All functions which could change
context in execbuf called from intel_bb were removed.
As an allocator requires size (which was not previously required in
intel_bb) adding object to intel_bb is now mandatory.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Use intel_bb as main batch implementation to remove libdrm dependency.
Rewrite all pipelines to use intel_bb and update render|vebox_copy
function prototypes.
Note that this will introduce compile failures into the indiviual users
until they are transitioned over to the new interface in the following
patches. The process is completed with "lib/rendercopy_bufmgr: remove
rendercopy_bufmgr."
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Since both rendercopy_gen8.c and rendercopy_gen9.c declare cc/viewport
variables without marking them as static, -fcommon also causes these to
make our builds fail:
/usr/bin/ld:
lib/libigt-rendercopy_gen9_c.a(rendercopy_gen9.c.o):lib/rendercopy_gen9.c:46:
multiple definition of `cc';
lib/libigt-rendercopy_gen8_c.a(rendercopy_gen8.c.o):lib/rendercopy_gen8.c:45:
first defined here
/usr/bin/ld:
lib/libigt-rendercopy_gen9_c.a(rendercopy_gen9.c.o):lib/rendercopy_gen9.c:51:
multiple definition of `viewport';
lib/libigt-rendercopy_gen8_c.a(rendercopy_gen8.c.o):lib/rendercopy_gen8.c:50:
first defined here
So, fix this by marking them as static.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lyude Paul <lyude@redhat.com>
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UV FBs have two color surfaces so extend the igt_buf struct accordingly
to support blitting such FBs.
The patch is produced with the coccinelle patch below.
No functional changes.
@@
@@
struct igt_buf {
...
- uint32_t stride;
...
- uint32_t size;
+ struct {
+ uint32_t stride;
+ uint32_t size;
+ } surface[2];
...
};
@@
struct igt_buf b;
@@
<...
(
- b.stride
+ b.surface[0].stride
|
- b.size
+ b.surface[0].size
)
...>
@@
struct igt_buf *b;
@@
<...
(
- b->size
+ b->surface[0].size
|
- b->stride
+ b->surface[0].stride
)
...>
@@
identifier I;
expression E1;
expression E2;
@@
(
struct igt_buf I = {
- .size = E1,
- .stride = E2,
+ .surface[0] = {
+ .size = E1,
+ .stride = E2,
+ },
};
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struct igt_buf I = {
- .size = E1,
+ .surface[0] = {
+ .size = E1,
+ },
};
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struct igt_buf I = {
- .stride = E1,
+ .surface[0] = {
+ .stride = E1,
+ },
};
)
v2:
- Rebase on latest upstream. (Mika)
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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YUV FBs have two CCS surfaces so extend the igt_buf struct accordingly
to support blitting such FBs.
The patch is produced with the coccinelle patch below, along with some
w/s fixup.
No functional change.
@@
@@
struct igt_buf {
...
struct {
uint32_t offset;
uint32_t stride;
- } aux;
+ } ccs[2];
...
};
@@
struct igt_buf *b;
@@
(
- b->aux.offset
+ b->ccs[0].offset
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- b->aux.stride
+ b->ccs[0].stride
)
@@
struct igt_buf b;
@@
(
- b.aux.offset
+ b.ccs[0].offset
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- b.aux.stride
+ b.ccs[0].stride
)
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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Use the igt_buf compression field to determine the compression type for
a buffer, instead of the fact that AUX stride is set. We need to look at
the former one anyway to distinguish between compression types.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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Add subtests using the vebox copy function to test the blit
functionality involving media compressed source and destination buffers.
These cover all the source and destination tiling formats supported by
the vebox engine and validate the buffer sharing between the render and
vebox engine (a render compressed buffer used by the vebox engine and a
media compressed buffer used by the render engine).
v2:
- Rebase on latest igt.
Simplify the condition for enabling media compression in the surface
state.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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To produce surfaces that are compressed using the media compression
format we need to use one of the media engines. The simplest way for
this is to use the vebox engine's tiling convert command, so add support
for this.
v2:
- Rebase on latest igt. (Mika)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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The AUX pagetables need to be set up for blits using the vebox engine
too, so move the related helper functions to intel_aux_pgtable.c.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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GEN12 supports color clear feature on the 3rd plane. The patch
updates rendercopy function to and buffers to support clear color.
Surface state bitgroups 12 and 13 are updated to support clear value
or depth clear value.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Radhakrishna Sripada<radhakrishna.sripada@intel.com>
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On GEN12+ the AUX CCS surfaces required by the render and media
compression must be specified by a 3 level page table directory, which
translates the main surface graphics address to the AUX CCS surface
graphics address. For this purpose add support for creating a GEM buffer
to translate the linear surface address range to the linear AUX surface
address range.
The buffers containing the main surface must be pinned down, since the
directory table entry indices depend on the surface address, and they
must be 64kB aligned. The page table can be relocated OTOH, so allow
that and emit the required relocation entries.
v2:
- Make level variables to be 0 based (l1..l3 -> level=0..2).
- Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
non-Intel archs.
- Fix missing offsets in reloc entries of already bound objects. (Chris)
- Randomize pin offsets, to try to avoid eviction. (Chris)
- Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
- Stop using explicit reloc cache domains, as these don't make sense on
GEN12 anyway. (Chris)
- Fix missing autotools support. (Chris)
- s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
specific. (Chris)
v3:
- Make sure all objects with an AUX surface are pinned.
v4:
- s/MI_LOAD_REGISTER_MEM/MI_LOAD_REGISTER_MEM_GEN8/ (Chris)
- Fix using buf->bo->size instead of buf->size when finding a free
range for a pinned obj.
- Fix alignment of the reserved space start for a pinned obj.
- Move gen12_emit_aux_pgtable_state() to its logical spot.
v5:
- Fix reloc emit call, passing a relative instead of absolute target
offset. (Chris)
- Fix off-by-one error when generating a random offset for pinned objs.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Previous generations didn't use SWSB dependency tracking.
For that reason shader was adopted to handle that on TGL.
FIXME: Some tests still have to be fixed, currently working:
gem_render_copy @linear @x-tiled @y-tiled @yf-tiled
gem_render_copy_redux
gem_render_linear_blits @basic
gem_render_tiled_blits @basic
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
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Unify the MOCS to be more consistently across the platforms.
Currently gen8+ are specifyig UC whereas earlier platforms
generally use PTE. Let's make everyone more or less specify
L3+PTE.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Allow copying between fp16 surfaces. We'll use the FLOAT
surface format since that's all the display supports currently.
Hopefully the hardware gives us a 1:1 copy, at least if
the input doesn't contain crazy infs/nans etc. We could
choose UNORM instead but that won't work for eventually
exposing fp16+ccs. Although we do need to replace the
simple bpp value with a more specific format type to get
10bpc+ccs working as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Sprinkle some asserts into rendercopy to make sure we don't try
to exceed the render engine surface size/stride limitations.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Set up the surface state accordingly to support Yf/Ys tiling.
>From DK:
Rebase.
Move support to gen-9 surface state
Cc: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Create a gen9 specific struct so that the gen-9+ Yf/Ys tiling bits can be
added there.
Suggested-by: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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To handle drawing 16 bpp formats correctly with odd x/w, we need to
use the correct bpp to rendercopy. Now that everything sets bpp in
igt_buf, fix the rendercopy support to use it and set the correct
format.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[mlankhorst: Add assert(src->bpp == dst->bpp)]
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This patch introduces a render copy shader for GEN11.
The plumbing is same as with GEN9, so we can reuse it, extracting the
common parts, and wrapping it in GEN-specific helpers.
v2: Added gen11 shader source path next to its binary form
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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In shaders/ directory we got Intel specific information. As igt
is a project for more vendors, let's move this directory to
lib/i915.
v2: Changed shaders directory path in library files comments.
Signed-off-by: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Kalamarz Lukasz <lukasz.kalamarz@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Instead of using definitions duplicated in gen7_render header,
we should use the oldest definition that is working with chosen
gen. This patch reuse gen6 definitons if registers/fields/shifts
that were introduced in other genX_render headers.
v3: Rebase and checkpatch
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Populate the gen8+ SURFACE_STATE aux bits correctly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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gen8 introduces 48 bit virtual addresses. Set both dwords correctly
as otherwise the presumed_offset will not match what we actually
have stored in the surface state if the buffer is located somewhere
above 4GiB.
I guess we're not currently using 48bit addresses with rendercopy?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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No one generally needs to modify the igt_bufs we pass around,
so make them const.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Remove the hardcoded dword offsets for the relocs and instead rely
fully on intel_batchbuffer_subdata_offset().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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The shaders/blit.g7a has weird artefacts (random pixel kill) when
drawing to an odd destination coordinate. Rather than debug the
issue with the asm/assembler, replace the kernel with the one used by
SNA for simple copies.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #chv, skl
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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This patch cleans gen9 header from a duplicate definition
and it dependency.
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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This patch implements some changes in gen8_render header and
all files that include it. Renamed all definition that were
introduced in that file with prefix GEN8_* instead of
previous GEN's one if they were not implemented there,
otherwise dropped duplicates. Modified include to use
gen7_render header instead of gen6.
v2: Fixed commit message
v3: fixed typo in commit msg
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Instead of using definitions duplicated in gen7_render header,
we should use the oldest definition that is working with
chosen gen. This patch reuses gen6 definitons if
registers/fields/shifts that were reintroduced in
other genX_render headers.
v2: Fixed commit message
v3: fixed typos in commit msg
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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This patch is renaming all surfaceformat registers to use
names introduced in surfaceformat.h instead of using
per gen definitions
v2: Drop GEN_ from register names. Applied that to
other libs.
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
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Batch functions were copy/pasted across several libs.
With moving it into intel_batchbuffer lib test can now be
easly maintained without worrying that we forgot to modify
older version of lib.
v2: Added documentation into lib and rebased patch
v3: Fixed typos and rebased patch
v4: Fixed documentation issues
v5: Rename, clean up of leftovers from previous version
and documentation polishing
v6: Fixing assert
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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No functionality related to aub is provided by libdrm aside from
intel_aub.h which somewhat defines the file format. Move the
header into this project to ease aub-related development.
Signed-off-by: Scott D Phillips <scott.d.phillips@intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Emil prefers if the approach in v2 is used (it was sent around the time
v1 had been applied).
This reverts commit 438c8d7c688780337d271016d84a69aab0474097.
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File is provided by the libdrm_intel package which is optional. Since we
already have a local copy of the file, we might as well use it ;-)
Cc: Brian Starkey <brian.starkey@arm.com>
Reported-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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From Gen9, by default push constant command is not committed to the shader unit
untill the corresponding shader's BTP_* command is parsed. This is the
behaviour when set shader is enabled. This patch updates the batch to follow
this requirement otherwise it results in gpu hang.
Set shader need to be disabled if legacy behaviour is required.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89959
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Tested-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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Don't set the size of bindless surface state on rendercopy.
And as of doing so, take into account the workaround for setting
the command size.
This was tried during hunting for
https://bugs.freedesktop.org/show_bug.cgi?id=89959. But no
impact was found.
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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Add rules to fix unused-result warnings when compiling with
_FORTIFY_SOURCE defined and apply them to the library and tests.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
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Without emitting the default 3DSTATE_WM_DEPTH_STENCIL state the test
will fail.
Signed-off-by: Imre Deak <imre.deak@intel.com>
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After applying the commit(982f7eb238a0898c456e0574dee7c4507738d75f), the
OUT_RELOC is updated on Broadwell and later, which is to handle the
64-bit field of gfx address internally. In such case some commands
should be fixed, otherwise GPU hang will be triggered when running
rendercopy. (It is already fixed on Broadwell)
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Signed-off-by: Thomas Wood <thomas.wood@intel.com>
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A value less than 4 might result in GPU hang on simulation
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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This is from that on BDW. Without it, the pixel pipeline can't work well.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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