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On DG2, if we poison bit8 of this register 0x7000, it causes the test
to catch "GPU hung". bit8 is "Depth Related Cache Pipelined Flush
Disable", set this to enable slow mode.
This change is to mask off to set bit8 of this register.
Signed-off-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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For no-reloc we need to ensure all offset management is done with
userspace allocator. Leaving register write intact was wrong as
offsets returned by allocator could overlap with proposed by the
kernel (write_regs() didn't have EXEC_OBJECT_PINNED before).
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
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For newer gens we're not able to rely on relocations. Adopt to use
offsets acquired from the allocator.
v2: add missing put_offset/ahnd (Ashutosh)
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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v2 (Zbigniew Kempczyński):
- Drop ctx from tmpl_regs
- Fix a whitespace typo
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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Add a wrapper for gem_create_ext ioctl (a version of gem_create that
accepts extensions). In preparation for the driver change implementing it,
a local definition of its id and necessary structs have been added,
which are to be erased as soon as those definitions
appear in the i915_drm.h file.
The new ioctl wrapper is added to a separate file.
For consistency the wrapper of the old ioctl, gem_create
is moved from ioctl_wrappers to gem_create.
Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
Cc: Zbigniew Kempczynski <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Acked-by: Petri Latvala <petri.latvala@intel.com>
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Disable banning as we deliberately inject GPU resets to test isolation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Venkata Ramana Nayana <venkata.ramana.nayana@intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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We want to recognise future devices (gen = -1u) and treat them as an
extension of the latest known device, which is typically true.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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igt_require_gem() is a pecularity of i915/, move it out of the core.
Similar opportunistic move of gem_reopen_driver() and
gem_quiescent_gpu().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Convert over to the new dynamic subtests for the per-engine tests, and
in the process switch over to for-each-physical engine iterators.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Some of the non-privileged registers are at the same offset on each
engine. We can improve our coverage for unknown HW layout by using the
reported engine->mmio_base for relative offsets.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
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Switch from the existing engine iteration to using macro
__for_each_physical_engine which all engines that are actually present.
The invocation of __for_each_physical_engine sets the engine mapping
for context 0 to be all existing engines. Subsequent context creation
is done via gem_context_clone_with_engines so that all contexts share
the same engine mapping.
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Call function gem_class_can_store_dword instead of legacy function
gem_can_store_dword. This requires that e->class be available in the
calling function.
Instead of passing "engine" (== "e->flags") to functions, pass "e".
This makes e->class available where it is needed.
This commit is being kept separate from "part 2" in order to ensure
proper attribution to the author. The code associated with this
commit was written by Ramalingam C <ramalingam.c@intel.com>.
Since then, slight modifications have been done due to upstream
changes.
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>.
X-Original-Author: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Quick fixup to the test so correct way of iterating the static engine list
is used. More comprehensive fixes to the test are in progress.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # irc
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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gem_ctx_isolation/persistence"
This reverts commit 343aae776a58a67fa153825385e6fe90e3185c5b.
__for_each_physical_engine() reprograms the context, invalidating the
use of e->flags to select engines, necessitating e->index instead.
Without also fixing up the engine selection, the result is that random
engines were being used to read registers from the intended engine.
This does not end well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Andi Shyti <andi.shyti@intel.com>
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Align with gem_exec_basic and other tests using the newer
engine query interface into i915 to enumerate active engines.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Since these are non-privileged registers exposed by whitelist, it
depends on the platform as to whether the kernel added them to the
whitelist.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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There's very little variation in non-privileged registers for Tigerlake,
so we can mostly inherit the set from gen11. There is no whitelist at
present, so we do not need to add any special registers.
v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a
variety of huc readonly status registers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111599
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Verify that the values we store in our nonpriv context image registers
are restored after a switch.
v2: Use explicit ordering to ensure we force the context switch back and
forth in between the register writes and their read.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
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This macro is defined in two tests. We can move it to common place
in ioctl_wrappers, which is included by all tests.
v2: Missed intel_device_info lib. Moved BIT definition to
intel_chipset, which is part of igt.h
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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We need to keep igt working on linus and dif, or Joonas gets very upset.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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There is no guarantee that spinners are and will be implemented
using batches. As we have igt_spin_t, manipulate it through
igt_spin_* functions consistently and hide the batch nature.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Instead of opencoding the poll into the spinner, use
a helper to check if spinner has started.
v2: use zero as presumed offset (Chris)
v3: cleanup the relocs (Chris)
v4: leave the domains to zero, avoid relocation (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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This patch is a change to igt file tests/i915/gem_ctx_isolation.c to
add and enable Gen11 support.
This patch accounts for whitelisted registers appropriately for the
different Gen levels.
This patch accounts for the changed MMIO offsets of Gen11.
This patch redefines MAX_REG from 0x40000 to 0x200000 due to the
larger total register space for Gen11 mmio offsets.
A current Gen11 SKU has two video engines (with indexes 0 and 2,
for VCS0 and VCS2), with VCS1 not being used.
Current kernel and igt limitations only allow for VCS0 and VCS1.
Those limitations are in the process of being removed. See for
example the RFC/PATCH series on igt-dev from Andy Shyti:
[igt-dev] [RFC PATCH v9 0/5] new engine discovery interface
which depends on in-process kernel "media scalability" patches.
Lacking the above infrastructure at the moment:
The array of registers to be tested includes VCS2 and VCS3 registers.
They are present as a provision for the future, but they will
not actually be tested as those engines are not yet known to the
underlying infrastructure.
When run on Gen11 this patch skips the sub-tests for the non-existent VCS1
with these warnings:
Test requirement not met in function gem_require_engine, file ../lib/igt_gt.h:114:
Test requirement: gem_has_engine(gem_fd, class, instance)
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Verify that our list of nonpriv registers exist and are writable.
v2: TD_CTL has a write_mask of 0xffff instead of being a masked
register.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
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On Skylake, BB_OFFSET seems to be unstable. Since this is an
offset into the batch at the time of CS execution, it should be actively
written to as we read from the register so allow it a qword of
discrepancy (since the CS should be reading in qwords). This still
allows us to detect dirt across the rest of the register field, should
that be required.
v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing
(Antonio)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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We can already move all the tests with distinct prefixes: gem_, gen3_
and i915_.
pm_ and drv_ tests will follow in batches, so we can do the
adjustments in the reporting/filtering layer of the CI system.
v2: Fix test-list.txt generation with meson
v3: Fix docs build (Petri)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Tested-by: Petri Latvala <petri.latvala@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
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