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Make mmap play nice on discrete.
Issue: https://gitlab.freedesktop.org/drm/intel/-/issues/5451
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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In 4d9396e67930 we have started storing the opts with which the spin was
created as part of igt_spin_t. The ahnd stored as part of igt_spin_t is
therefore redundant. We can get ahnd from opts.ahnd.
Cc: Zbigniew Kempczynski <zbigniew.kempczynski@intel.com>
Cc: Jasmine Newsome <jasmine.newsome@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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The i915 currently has 2k visible priority levels which are currently
unique. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_ctx_shared to understand this. This entails updating
promotion test to use 3 levels that will map into different buckets and
also add bit of delay after releasing a cork beforing completing the
spinners to give time to the i915 schedule to process the fence and
release and queue the requests.
v2: Add a delay between starting releasing spinner and cork in
promotion
v3:
(Daniele)
- Always add delay, update commit message
v4:
(Tvrtko)
- Reduce sleep period
(Daniele)
- Add comment in code by sleep
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
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Use gem_uses_ppgtt() for create vm and gem_scheduler_enabled() for
context re-ordering.
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
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The function names gem_has_guc_submission and gem_has_execlists and
gem_has_semaphores are ambiguous. After "lib/i915: Return actual submission
method from gem_submission_method" these functions return which submission
method the kernel is actually using, not merely one which is
present (e.g. execlist submission is present on all kernels on which GuC
submission is present).
Therefore change the function names to clarify that they return the actual
submission method being used, not merely one which is present.
Suggested-by: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
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gem_submission_method() purports to return the currently used submission
method by the kernel, as evidenced by its callers. Therefore remove the
GEM_SUBMISSION_EXECLISTS flag when GuC submission is detected.
This also fixes gem_has_execlists() to match its description, previously
gem_has_execlists() would return true even if GuC submission was actually
being used in the driver.
v2: Or gem_has_execlists call-sites with gem_has_guc_submission to make the
new code equivalent to the previous code.
v3: Clarify that submission method is either guc (0x4), execlists (0x2) or
legacy without semaphores (0x0) or legacy with semaphores (0x1)
v4: Submission methods are now clearly defined as one of guc (3),
execlists (2) or legacy ring buffer (1)
Reported-by: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
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Resolved missing context id in exec buf by passing first context i.e
ctx[0].
This change would fix test assertion in gem_execbuf for
"exec_shared_gtt" subtest.
Signed-off-by: Arjun Melkaveri <arjun.melkaveri@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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For newer gens we're not able to rely on relocations. Adopt to use
offsets acquired from the allocator.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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Instead use either GET/SET_CONTEXT_PARAM or a create ext.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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v2 (Jason Ekstrand):
- Rework the Q- tests to share a VM and set SINGLE_TIMELINE
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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Add a wrapper for gem_create_ext ioctl (a version of gem_create that
accepts extensions). In preparation for the driver change implementing it,
a local definition of its id and necessary structs have been added,
which are to be erased as soon as those definitions
appear in the i915_drm.h file.
The new ioctl wrapper is added to a separate file.
For consistency the wrapper of the old ioctl, gem_create
is moved from ioctl_wrappers to gem_create.
Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
Cc: Zbigniew Kempczynski <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Chris P Wilson <chris.p.wilson@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Acked-by: Petri Latvala <petri.latvala@intel.com>
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Use the context local variant of __for_each_physical_engine() to update
the engine map on the context prior to iterating.
Signed-off-by: Steve Hampson <steven.t.hampson@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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As a stepping stone, increase the assumed 16 engines is enough for
everyone, to cover the current RING_MASK, the maximum number of engines
that can currently be selected during execbuf.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
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We want to recognise future devices (gen = -1u) and treat them as an
extension of the latest known device, which is typically true.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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The cmdparser is a cause of priority inversions [it is multiple FIFO
queues, the kworkers] and so may perturb the Q-independent tests by
delaying the high priority requests to only be submitted after the low
priority requests have already completed. The goal of the test is let
all be ready to run simultaneous and check that they are run in priority
order [that they can indeed be run independently despite sharing the
vm].
References: https://gitlab.freedesktop.org/drm/intel/-/issues/2013
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Can't test queues, if we don't have queues.
The queue ordering tests checked for scheduler support, assuming that
would mean we had full-ppgtt. Check for queues in case we solve the
scheduler problem on gen6/gen7.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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The cmd-parser causes a disturbance in our priority scheme. It uses a
CPU worker that does not inherit the context priority and so may use a
simple FIFO that causes the requests to be ready (and so executed) in
parser order rather than our expected inherited priority order. If we do
not need to wait for relocations, the cmdparser is run inline, i.e.
before the test unleashes the fence holding the requests back.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Local macros were declared in several files as a prelude to upstream
implementations. Now that we ship include/drm-uapi, we can remove LOCAL
as we upstream.
Cc: Dixit, Ashutosh <ashutosh.dixit@intel.com>
Cc: Tahvanainen Jari <jari.tahvanainen@intel.com>
Signed-off-by: ranjeet kumar <ranjeet1.kumar@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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igt_require_gem() is a pecularity of i915/, move it out of the core.
Similar opportunistic move of gem_reopen_driver() and
gem_quiescent_gpu().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Andi Shyti <andi.shyti@intel.com>
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Use the name generated for the engine list, let's not try and
incorrectly guess it from the wrong set of flags.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1533
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Convert over to the new dynamic subtests for the per-engine tests, and
in the process switch over to for-each-physical engine iterators.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Closes: https://gitlab.freedesktop.org/drm/intel/issues/1466
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Use a fence to submit the pair of batches tightly together, and in
particular not allow the system time to retire in between. Then by
passing the fence along the inter-context chain, we can force the
explicit order of execution, which we currently lack as we are avoiding
the implicit fences.
In particular, without the explicit ordering the second batch could
execute before the first had managed to asynchronously bind the hidden
buffer.
References: https://gitlab.freedesktop.org/drm/intel/issues/1420
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Several tests depend upon the implicit engine->mmio_base but have no
means of determining the physical layout. Since the kernel has started
providing this information, start putting it to use.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
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The only use for mmap__gtt here was to gain coherent access to the
buffer, so can be simply converted over to mmap__device_coherent.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Once the fence is retired, we discard its references to the context
state, including its timeline name. So the timeline query is only
accurate before being signaled, so keep the fence alive until after the
query.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Allow the subtests that want to limit the test to a single engine, to
limit the test to a single engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Provide the iterator name as an explicit macro parameter so that it is
known to the caller, and allows for them to properly nest loops over all
engines.
Fixes:
../tests/i915/gem_exec_schedule.c: In function ‘semaphore_noskip’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local [-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:653:2: note: in expansion of macro ‘for_each_physical_engine’
for_each_physical_engine(i915, other) {
^~~~~~~~~~~~~~~~~~~~~~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:652:2: note: in expansion of macro ‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~~~~~~~~~~~~~~~~~~~~~
../tests/i915/gem_exec_schedule.c: In function ‘measure_semaphore_power’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local [-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1740:3: note: in expansion of macro ‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~~~~~~~~~~~~~~~~~~~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1719:2: note: in expansion of macro ‘for_each_physical_engine’
for_each_physical_engine(i915, signaler) {
^~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
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If we are using an aliasing-ppgtt, the context images are in the same
virtual address space as our target objects. We have to be careful that
cloning and using a new context does not evict our unreferenced target
object. To avoid that, we first bind both context images while creating
the hole in the address space to ensure that the hole is still available
later on.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
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As we never officially write to the scratch buffer, the kernel will
leave it in the CPU read domain upon execution. Our attempt to
invalidate the CPU cache on !llc is therefore skipped as the kernel
doesn't believe the backing store has been invalidated. Use a WC mmap to
avoid the CPU cache for readback, and add an extra sanity check that the
scratch buffer is found at the same location after execution. (This
sanity check does not affect the failure rate on bsw, that is only fixed
after realising that we do not clflush for the invalidate prior to the
read).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111187
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
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In the exec-shared-gtt test, we cheekily try to reference an object we
placed in the GTT in an earlier execbuf (and avoid declaring it in the
later call). For a global GTT, where there may be existing objects, we
have to find a hole large enough to fit both and avoid and implicit
guard pages.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110876
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
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Since we are fiddling behind the scenes, we are writing to objects that
are not part of the execbuffer, do not rely on implicit domain
management being able to track the appropriate CPU cache status.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110890
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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I told vecs0 to use vecs1 registers...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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v2: Test each shared context is its own timeline and allows request
reordering between shared contexts.
v3: Use the modern interface to use physical engines for testing
single-timeline along each real engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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