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Eric is using meson nowadays.
v2: Fix up the test filter, meson lists now contain more than in the
automake lists.
Cc: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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We're not using automake to build tarballs anymore.
Acked-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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Emil has another auth test which could use the check_auth function, so
best to merge them all.
We need a subtest group and put the tests which need to fully control
who's master and how many open drm fd there are first.
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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There are 3 tests for basic variable refresh rate functionality.
The tests measure flipping at the average between the current mode
refresh rate and the minimum supported variable refresh rate.
It tests that VRR is enabled and that the difference between flip
timestamps converges to the requested rate. It also tests this under
both S3 and DPMS.
Potential ideas for future tests:
- Test behavior inside VRR range with a stepping test
- Test behavior outside of VRR range
- Multi-monitor (limited by no async pageflips in DRM atomic API)
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
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If the properties for gamma tables exist, their sizes must be
non-zero.
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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In 2013 we prevented changing the tiling of an active framebuffer:
commit 80075d492f8773209e26d11d6bb13ba624ef95a4
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Wed Oct 9 21:23:52 2013 +0200
drm/i915: prevent tiling changes on framebuffer backing storage
After this we no longer have any use for the bad-tiling subtest, and
only have to make sure changing tiling on a fb is not allowed.
Remove the original bad-tiling subtest, and add a i915_fb_tiling
subtest for this case.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
[mlankhorst: Fix build system changes]
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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Make certain viewports are divisible by four due to intel
hw workarounds for NV12.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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This patch adds one test to evaluate suspend/resume operations using kms_flip.
v2: Reduce test time to 10 (Daniel)
Signed-off-by: Shayenne Moura <shayenneluzmoura@gmail.com>
Reviewed-by: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
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Performing a GPU reset clobbers the fence registers, affecting which
addresses the tiled GTT mmap access. If the driver does not take
precautions across a GPU reset, a client may read the wrong values (but
only within their own buffer as the fence will only be degraded to
I915_TILING_NONE, reducing the access area). However, as this requires
performing a read using the indirect GTT at exactly the same time as the
reset occurs, it can be quite difficult to catch, so repeat the test
many times and across all cores simultaneously.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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If the device has error capturing disabled, we still allow previous
error state to be cleared by a write to sysfs/error. To actually confirm
that we can capture a fresh error state, we have to perform a read().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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We already depend on glib which has sha1, so we don't really need
openssl just for sha1.
The opensll dependency was added in commit caea9c5b3aa1
("igt/gem_userptr: Check read-only mappings").
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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The main tests for PSR1 check if hardware tracking is detecting
changes in planes when modifing it in different ways and now
those tests will also run for PSR2 if supported by source and sink.
v4: Dynamic generating PSR1 and PSR2 tests instead of copy and paste
tests twice.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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When the PSR2 tests were added it will be necessary switch between
PSR versions, so lets add test_setup() and make it call
setup_test_plane() and assert if PSR is active as it is the base for
every test.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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Add the mode parameter to psr_enable() and psr_sink_support() so PSR1
and PSR2 can be tested separated.
For now all PSR tests will run only with PSR1 and the tests for PSR2
will come in the future.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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This way we can test both PSR version separated.
v4: Dropping psr_state_check() to psr_active_check()
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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This is a initial preparation for PSR2 test support, as in PSR2 a
update to screen could mean that PSR is still active and the screen
will be update by a selective update this renamed is necessary.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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No point in sleeping 5 seconds between each modeset when running in ci.
So let's just make the default sleep interval 0 seconds and leave it up
to the user to bump it via -s when running interactively.
On a KBL + LSPCON + a 4k HDMI display with 36 modes listed:
time ./tests/testdisplay
- real 3m12,026s
- user 0m1,920s
- sys 0m1,241s
+ real 0m14,681s
+ user 0m3,135s
+ sys 0m1,340s
Cc: Martin Peres <martin.peres@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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No actual difference, size of a pointer is the same as
pointer-to-pointer.
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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The size of the UV plane is not calculated correctly - height is not tile
aligned. Make use of the stride and offset values intitialized in the
previous patch to calculate plane size. The next step would be to rewrite
the test to make use of library functions, but for now this should fix
NV12.
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
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The test does not initialize data->fb, initializing stride and offset is
necessary to fill NV12 planes correctly. We should ideally be using
library functions in place of handrolled code in this test, but let's start
by fixing the failures.
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
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Not clearing the pipe results in a test failure when the same pipe is
assigned to the next output.
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Suggested-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
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Add NV12 support for testing where available.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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rendered test image had off-by-one error in size calculation
which was failing some tests on certain resolutions and plane
sizes.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Use another sensitive CPU reloc to emit a chained batch from inside the
updated buffer to reduce the workload on slow machines to fit within the
CI timeout.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108248
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Some setups (e.g. guc and gen10+) can not disable the MI_USER_INTERRUPT
generation and so can not simulate missed interrupts. These tests would
fail, so skip when the kernel reports no tests available.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Use a specific timeout to exercise the race conditions, rather than a
number of tries -- this prevents it burning up too many minutes under CI
for little gain, we can just run it again to improve race detection.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108667
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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We multiply the memfd 64k to create a 2G arena which we then attempt to
write into after marking read-only. However, when it comes to unlock the
arena after the test, performance tanks as the kernel tries to resolve
the 64k repeated mappings onto the same set of pages. (Must not be a
very common operation!) We can get away with just mlocking the backing
store to prevent its eviction, which should prevent the arena mapping
from being freed as well.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108887
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Th heavy variant of gem_ctx_switch does little more than provide an
alternate timing for the basic gem_ctx_switch; the timing only effects
the HW and does not stress the driver any differently. As such,
including gem_ctx_switch/heavy provides no more basic coverage for BAT
over and above the default gem_ctx_switch and
i915_selftests/live_contexts.
It takes around 45s, of a 600s total target time for BAT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Tomi Sarvela <tomi.p.sarvela@intel.com>
Acked-by: Petri Latvala <petri.latvala@intel.com>
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The same code checking if sink supports PSR was spread into 3 tests,
better move it to lib and reuse.
v2: splitted previous patch into this one and the next one(Dhinakaran)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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So every function reading i915_edp_psr_status can allocate a buffer
long enough.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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If we break out of the test loop early, we may not have filled all
dwords, so be careful to only check as far as we completed.
Fixes: d9cd03c887a5 ("i915/gem_exec_whisper: Limit to a maximum of 150s")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109356
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Just use the normal library function, with the normal warning message
for an unmatched GPU so that CI buglog can filter it.
References: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Martin Peres <martin.peres@free.fr>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Fixes: 738f43a54d62 ("tests/amdgpu: Add test for Adaptive Backlight Management")
Reported-by: gitlab-CI
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: David Francis <David.Francis@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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Each individual pass is as effective at spotting an error using the
Chinese whisper as any other, so the effectiveness of adding more passes
rapidly diminishes. To keep the tests bounded within time, limit a
subtest to a mere 150s!
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108592
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Add test to check extreme alpha values i.e. fully opaque and fully transparent
for cursor plane and verify by calculating hardware and software CRC.
Signed-off-by: Mamta Shukla <mamtashukla555@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
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This patch adds a basic kms test to validate the display stream
compression functionality if supported on DP/eDP connector.
Currently this has only two subtests to force the DSC on all
the eDP and DP connectors that support it with default parameters.
This will be expanded to add more subtests to tweak DSC parameters.
v8 (from Manasi):
* Fix the logic to scan through all connectors even if some dont
support DSC/FEC (Petri)
* Fix the skip test logic if no connectors support DSC to avoid
false positives (Petri)
* Move test clenup to run_test
v7: (from Anusha)
* Code Style changes.(Petri)
* Use for_each_pipe() instead of for_each_pipe_static().(Petri)
* Correct logic by avoiding skipping of inner for loop completely.(Petri)
v6: (from Anusha)
* Fix run_test() (Petri)
* Fix update_display() to avoid leaks. (Petri)
v5:
* Fix test cleanup to avoid crash (Petri)
v4:
* Future proof for more test types (Petri)
* Fix alphabetical order (Petri)
* s/igt_display_init/igt_display_require (Petri)
* Remove blank lines after return (Petri)
v3:
* Use array of connectors and loop through (Petri)
* Also check for FEC on DP connectors (Manasi)
* Add a Pipe_A restriction on DP (Ville)
v2:
* Use IGT wrappers for all (DK, Antonio)
* Split into two subtests for eDP and DP types (Petri)
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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get_tiling == gem_get_tiling + igt_require; so do that instead of
opencoding the ioctl.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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If we do not know the underlying swizzle on the HW, we do not know the
full tiling pattern and cannot predict the expected results. This is
often because the swizzle varies between pages and is not as constant as
we naively expected.
v2: gem_get_tiling() does the physical==reported check, we just need to
add a require
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
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Currently blt-vs-render runs for a fixed loop count, and exceeds 360s
on a slow Skylake-y. It really doesn't tell us anything useful about low
likelihood events after the first few seconds it takes to fill memory,
so limit it to 30s (and hope that repeated runs in CI is enough to
exercise the even rarer corner cases).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108039
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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sysfs doesn't give the driver an open() callback, so we can only report
the unavailability of HW on the first read; so check read() after checking
open().
Fixes: 93f0ad4b835e ("i915/hangman: Skip if disabled by the kernel")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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These exercise a certain HW misfeature, no longer protected by the
kernel cmdparser due to obsolete userspace requirements.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Petri Latvala <petri.latvala at intel.com>
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On Skylake, BB_OFFSET seems to be unstable. Since this is an
offset into the batch at the time of CS execution, it should be actively
written to as we read from the register so allow it a qword of
discrepancy (since the CS should be reading in qwords). This still
allows us to detect dirt across the rest of the register field, should
that be required.
v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing
(Antonio)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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Some kernels may have to disable error capture for some hardware or by
it being configured out. Since it is conditionally available, asserting
it exists is not an actual requirement. For hardware where we are unable
to provide error state capture, skip.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Antonio Argenziano <antonio.argenziano@intel.com>
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Adaptive Backlight Management (ABM) is a power-saving
feature on AMD ASICs that reduces backlight while increasing
pixel contrast and luminance. This test confirms that
ABM is present and enabled, and that backlight performance
is sane. It uses AMD-specific debugfs entries to
read the backlight PWM values.
It has 5 subtests:
dpms_cycle
Sets brightness to half, then confirms that value is restored
after dpms off and then on.
backlight_monotonic_basic
Sets brightness to ten different values, confirming that
higher brightness values are brighter.
backlight_monotonic_abm
Same as backlight_monotonic_basic, but with abm enabled.
abm_enabled
Sets abm to its four intensity levels, confirming that
abm reduces the backlight, and the reduction is greater
for higher abm level.
abm_gradual
Sets abm to off and then maximum intensity, confirming
that brightness decreases continually over the first
second and eventually reaches the target value.
This test takes 30s to run.
v2: make sure that dpms is cycled on the eDP display
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
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The i915 specific feature requirements that would have failed subtests
from kms_plane, kms_plane_multiple and kms_plane_scaling have been
conditionally guarded against. These tests can now be run on AMDGPU
with the i915 specific tests skipped appropriately.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
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The kms_plane_lowres subtests will fail on non-i915 hardware because
of the devid lookups and tiling format requirements.
This patch makes use of the igt_display_has_format_mod() helper to
check for support before failing fb creation.
The tests still won't fully run yet on i915 hardware because they'll
skip during calls to igt_assert_plane_visible - those require an i915
extension to get the CRTC/plane set for a given pipe.
v2: Use igt_display_has_format_mod helper (Ville)
v3: Move variable declarations to loop scope (Ville)
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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The per-pipe plane position subtests are capable of running on
AMDGPU as long as they're not using i915 specific tiling formats.
The test setup already supports being invoked with different tiling
modes so this patch introduces the new 'tiled-none' subtest that runs
without any tiling.
The tiled-none tests are skipped on i915 to retain existing test
coverage and behavior on i915.
v2: Use igt_display_has_format_mod helpers (Ville)
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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The plane_scaling subtests are capable of running on AMDGPU when
not using i915 specific tiling formats and when the test only requires
one scaler per pipe.
This patch removes the forced i915 devid and gen checks from non i915
devices. It also adds logic for getting the number of scalers per pipe
in a way that doesn't only depend on devid. One scaler per pipe is
assumed for AMDGPU.
There isn't any specific reason that the x-tiled formats need to be
used on the non-rotation tests on i915 but this patch keeps the
existing test behavior. It's a little simpler to keep it this way for
the prepare_crtc helper that's shared between the scaling test
and the clipping/clamping test.
v2: Use igt_plane_has_format_mod helper (Ville)
v3: Use helpers to check x-tiled support (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Ensure that the hangcheck notices the hanging batch by using a
non-preemptible spin batch, as some future versions of hangcheck may
allow a preemptible GPU hog to survive.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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