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Cannonlake port clock programming tests and verifies DPLL legal dividers
P, Q, and K. This tests adds two reference clocks 19.2MHz and 24MHz to
test algorithm's capability to find P, Q, and K dividers as well as DCO
frequency for different symbol clock rates.
The test compares two algorithms, the reference with double precision and
i915 implementation with fixed point precision. In case of a difference in
computation the difference on dividers is printed out to the screen.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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