From e71f1d2ad46af09a61b0fd03f4b00514de5091e5 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Mon, 14 Jan 2013 19:13:19 +0000 Subject: assembler: Sync brw_instruction's header with mesa's Two changes there, a field has been renamed and one bit of padding is now used for compressed instructions. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) (limited to 'assembler/brw_structs.h') diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h index 3a3b1601..59b28fae 100644 --- a/assembler/brw_structs.h +++ b/assembler/brw_structs.h @@ -1043,21 +1043,25 @@ struct brw_instruction { struct { - GLuint opcode:7; /* 0x0000007f */ - GLuint pad:1; /* 0x00000080 */ /* reserved for Opcode */ - GLuint access_mode:1; /* 0x00000100 */ - GLuint mask_control:1; /* 0x00000200 */ - GLuint dependency_control:2; /* 0x00000c00 */ - GLuint compression_control:2; /* 0x00003000 */ - GLuint thread_control:2; /* 0x0000c000 */ - GLuint predicate_control:4; /* 0x000f0000 */ - GLuint predicate_inverse:1; /* 0x00100000 */ - GLuint execution_size:3; /* 0x00e00000 */ - GLuint sfid_destreg__conditionalmod:4; /* sfid - send on GEN6+, destreg - send on Prev GEN6, conditionalmod - others */ - GLuint acc_wr_control:1; /* 0x10000000 */ - GLuint pad0:1; /* 0x20000000 */ - GLuint debug_control:1; /* 0x40000000 */ - GLuint saturate:1; /* 0x80000000 */ + GLuint opcode:7; + GLuint pad:1; + GLuint access_mode:1; + GLuint mask_control:1; + GLuint dependency_control:2; + GLuint compression_control:2; /* gen6: quater control */ + GLuint thread_control:2; + GLuint predicate_control:4; + GLuint predicate_inverse:1; + GLuint execution_size:3; + /** + * Conditional Modifier for most instructions. On Gen6+, this is also + * used for the SEND instruction's Message Target/SFID. + */ + GLuint destreg__conditionalmod:4; + GLuint acc_wr_control:1; + GLuint cmpt_control:1; + GLuint debug_control:1; + GLuint saturate:1; } header; union { -- cgit v1.2.3