From dfe6adacc923336fa1e98b781ff67abaada29b95 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 30 Jan 2013 22:32:07 +0000 Subject: assembler: Gather all predicate data in its own structure Rather than user a full instruction for that. Also use set_instruction_predicate() for a case that coud not be done like that before the refactoring (because everyone now uses the same instruction structure). Signed-off-by: Damien Lespiau --- assembler/gen4asm.h | 7 +++++++ assembler/gram.y | 53 ++++++++++++++++++++++++++--------------------------- 2 files changed, 33 insertions(+), 27 deletions(-) (limited to 'assembler') diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h index 5673e2c9..00dd73a1 100644 --- a/assembler/gen4asm.h +++ b/assembler/gen4asm.h @@ -85,6 +85,13 @@ struct condition { int flag_subreg_nr; }; +struct predicate { + unsigned pred_control:4; + unsigned pred_inverse:1; + unsigned flag_reg_nr:1; + unsigned flag_subreg_nr:1; +}; + struct region { int vert_stride, width, horiz_stride; int is_default; diff --git a/assembler/gram.y b/assembler/gram.y index 9b90db90..23d7cfb1 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -101,7 +101,7 @@ static int set_instruction_src2_three_src(struct brw_program_instruction *instr, static void set_instruction_options(struct brw_program_instruction *instr, struct brw_program_instruction *options); static void set_instruction_predicate(struct brw_program_instruction *instr, - struct brw_program_instruction *p); + struct predicate *p); static void set_direct_dst_operand(struct brw_reg *dst, struct brw_reg *reg, int type); static void set_direct_src_operand(struct src_operand *src, struct brw_reg *reg, @@ -396,6 +396,7 @@ static void resolve_subnr(struct brw_reg *reg) struct regtype regtype; struct brw_reg reg; struct condition condition; + struct predicate predicate; struct declared_register symbol_reg; imm32_t imm32; @@ -475,7 +476,7 @@ static void resolve_subnr(struct brw_reg *reg) %type binaryaccinstruction trinaryinstruction sendinstruction %type syncinstruction %type msgtarget -%type instoptions instoption_list predicate +%type instoptions instoption_list %type mathinstruction %type nopinstruction %type relocatableinstruction breakinstruction @@ -487,6 +488,7 @@ static void resolve_subnr(struct brw_reg *reg) %type unaryop binaryop binaryaccop breakop %type trinaryop %type conditionalmodifier +%type predicate %type condition saturate negate abs chansel %type writemask_x writemask_y writemask_z writemask_w %type srcimmtype execsize dstregion immaddroffset @@ -956,8 +958,8 @@ unaryinstruction: if ($3.flag_subreg_nr != -1) { if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - (GEN(&$1)->bits2.da1.flag_reg_nr != $3.flag_reg_nr || - GEN(&$1)->bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + ($1.flag_reg_nr != $3.flag_reg_nr || + $1.flag_subreg_nr != $3.flag_subreg_nr)) warn(ALWAYS, &@3, "must use the same flag register if " "both prediction and conditional modifier are " "enabled\n"); @@ -997,8 +999,8 @@ binaryinstruction: if ($3.flag_subreg_nr != -1) { if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - (GEN(&$1)->bits2.da1.flag_reg_nr != $3.flag_reg_nr || - GEN(&$1)->bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + ($1.flag_reg_nr != $3.flag_reg_nr || + $1.flag_subreg_nr != $3.flag_subreg_nr)) warn(ALWAYS, &@3, "must use the same flag register if " "both prediction and conditional modifier are " "enabled\n"); @@ -1038,8 +1040,8 @@ binaryaccinstruction: if ($3.flag_subreg_nr != -1) { if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - (GEN(&$1)->bits2.da1.flag_reg_nr != $3.flag_reg_nr || - GEN(&$1)->bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + ($1.flag_reg_nr != $3.flag_reg_nr || + $1.flag_subreg_nr != $3.flag_subreg_nr)) warn(ALWAYS, &@3, "must use the same flag register if " "both prediction and conditional modifier are " "enabled\n"); @@ -1067,10 +1069,7 @@ trinaryinstruction: { memset(&$$, 0, sizeof($$)); - GEN(&$$)->header.predicate_control = GEN(&$1)->header.predicate_control; - GEN(&$$)->header.predicate_inverse = GEN(&$1)->header.predicate_inverse; - GEN(&$$)->bits1.da3src.flag_reg_nr = GEN(&$1)->bits2.da1.flag_reg_nr; - GEN(&$$)->bits1.da3src.flag_subreg_nr = GEN(&$1)->bits2.da1.flag_subreg_nr; + set_instruction_predicate(&$$, &$1); GEN(&$$)->header.opcode = $2; GEN(&$$)->header.destreg__conditionalmod = $3.cond; @@ -1089,8 +1088,8 @@ trinaryinstruction: if ($3.flag_subreg_nr != -1) { if (GEN(&$$)->header.predicate_control != BRW_PREDICATE_NONE && - (GEN(&$1)->bits2.da1.flag_reg_nr != $3.flag_reg_nr || - GEN(&$1)->bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + ($1.flag_reg_nr != $3.flag_reg_nr || + $1.flag_subreg_nr != $3.flag_subreg_nr)) warn(ALWAYS, &@3, "must use the same flag register if " "both prediction and conditional modifier are " "enabled\n"); @@ -2619,21 +2618,21 @@ imm32: exp { $$.r = imm32_d; $$.u.d = $1; } /* 1.4.12: Predication and modifiers */ predicate: /* empty */ { - GEN(&$$)->header.predicate_control = BRW_PREDICATE_NONE; - GEN(&$$)->bits2.da1.flag_reg_nr = 0; - GEN(&$$)->bits2.da1.flag_subreg_nr = 0; - GEN(&$$)->header.predicate_inverse = 0; + $$.pred_control = BRW_PREDICATE_NONE; + $$.flag_reg_nr = 0; + $$.flag_subreg_nr = 0; + $$.pred_inverse = 0; } | LPAREN predstate flagreg predctrl RPAREN { - GEN(&$$)->header.predicate_control = $4; + $$.pred_control = $4; /* XXX: Should deal with erroring when the user tries to * set a predicate for one flag register and conditional * modification on the other flag register. */ - GEN(&$$)->bits2.da1.flag_reg_nr = ($3.nr & 0xF); - GEN(&$$)->bits2.da1.flag_subreg_nr = $3.subnr; - GEN(&$$)->header.predicate_inverse = $2; + $$.flag_reg_nr = $3.nr; + $$.flag_subreg_nr = $3.subnr; + $$.pred_inverse = $2; } ; @@ -3076,12 +3075,12 @@ static void set_instruction_options(struct brw_program_instruction *instr, } static void set_instruction_predicate(struct brw_program_instruction *instr, - struct brw_program_instruction *p) + struct predicate *p) { - GEN(instr)->header.predicate_control = GEN(p)->header.predicate_control; - GEN(instr)->header.predicate_inverse = GEN(p)->header.predicate_inverse; - GEN(instr)->bits2.da1.flag_reg_nr = GEN(p)->bits2.da1.flag_reg_nr; - GEN(instr)->bits2.da1.flag_subreg_nr = GEN(p)->bits2.da1.flag_subreg_nr; + GEN(instr)->header.predicate_control = p->pred_control; + GEN(instr)->header.predicate_inverse = p->pred_inverse; + GEN(instr)->bits2.da1.flag_reg_nr = p->flag_reg_nr; + GEN(instr)->bits2.da1.flag_subreg_nr = p->flag_subreg_nr; } static void set_direct_dst_operand(struct brw_reg *dst, struct brw_reg *reg, -- cgit v1.2.3