From b4817052080fdc85e2376a5d63dafd8238e95d67 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sun, 1 May 2016 09:07:29 +0100 Subject: lib: Apply magic clflush serialisation On Baytrail, Braswell and Atoms beyond we see an issue where the mfence is insufficient to force the cacheline to be coherent (i.e. such that writes from the GPU are visible by the CPU after the call to clflush). A second clflush is ordered with an earlier clflush to the same address and this appears sufficient to give the coherency required for GPU/CPU interop. Testcase: igt/gem_exec_flush Signed-off-by: Chris Wilson Cc: Akash Goel --- lib/igt_gt.c | 1 + 1 file changed, 1 insertion(+) (limited to 'lib/igt_gt.c') diff --git a/lib/igt_gt.c b/lib/igt_gt.c index 0236518f..463f8b6d 100644 --- a/lib/igt_gt.c +++ b/lib/igt_gt.c @@ -425,6 +425,7 @@ void igt_clflush_range(void *addr, int size) __builtin_ia32_mfence(); for (; p < end; p += clflush_size) __builtin_ia32_clflush(p); + __builtin_ia32_clflush(end - 1); /* magic serialisation for byt+ */ __builtin_ia32_mfence(); #else fprintf(stderr, "igt_clflush_range() unsupported\n"); -- cgit v1.2.3