From 2aa3dc83399a16588ba06ec1718ed709f55bb8d9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 29 Jun 2016 12:11:28 +0100 Subject: intel_chipset: Replace lookup of GT size with computation Instead of a large if-chain for matching devid to GT, we can just compute it directly from the encoded devid. Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 109 +--------------------------------------------------- 1 file changed, 1 insertion(+), 108 deletions(-) (limited to 'lib/intel_chipset.h') diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index e3e97ff0..42343614 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -67,6 +67,7 @@ const struct intel_device_info { } *intel_device_info(uint16_t devid) __attribute__((pure)); unsigned intel_gen(uint16_t devid) __attribute__((pure)); +unsigned intel_gt(uint16_t devid) __attribute__((pure)); extern enum pch_type intel_pch; @@ -269,114 +270,6 @@ void intel_check_pch(void); #endif /* __GTK_DOC_IGNORE__ */ -#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ - (devid) == PCI_CHIP_HASWELL_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) -#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ - (devid) == PCI_CHIP_HASWELL_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) -#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ - (devid) == PCI_CHIP_HASWELL_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) - -#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT1) - -#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT2) - -#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) - -#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT4) - -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0|| \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1|| \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) - -#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) - -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0|| \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1|| \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) - -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) - #define IS_915G(devid) (intel_device_info(devid)->is_grantsdale) #define IS_915GM(devid) (intel_device_info(devid)->is_alviso) -- cgit v1.2.3