From 4fc76adf313f2792b7438f9372321ce3ea66c6c2 Mon Sep 17 00:00:00 2001 From: Vijay Purushothaman Date: Fri, 17 Aug 2012 18:06:52 +0530 Subject: tools: Added intel_dpio_read and intel_dpio_write In Valleyview the DPLL and lane control registers are accessible only through side band fabric called DPIO. Added two tools to read and write registers residing in this space. v2: Moved the core read/write functions to lib/intel_dpio.c based on Ben's feedback Signed-off-by: Vijay Purushothaman Signed-off-by: Daniel Vetter --- lib/intel_chipset.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'lib/intel_chipset.h') diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index a229ea17..9dd4c94c 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -196,6 +196,8 @@ dev == PCI_CHIP_IVYBRIDGE_S_GT2 || \ dev == PCI_CHIP_VALLEYVIEW_PO) +#define IS_VALLEYVIEW(devid) (devid == PCI_CHIP_VALLEYVIEW_PO) + #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ devid == PCI_CHIP_HASWELL_M_GT1 || \ devid == PCI_CHIP_HASWELL_S_GT1 || \ -- cgit v1.2.3