From ad5858e320625dd1ad1555ca0cb4da2cfad96fda Mon Sep 17 00:00:00 2001 From: Lukasz Kalamarz Date: Tue, 12 Jun 2018 14:10:00 +0200 Subject: lib/rendercopy: Use gen6 definitions if applicable Instead of using definitions duplicated in gen7_render header, we should use the oldest definition that is working with chosen gen. This patch reuses gen6 definitons if registers/fields/shifts that were reintroduced in other genX_render headers. v2: Fixed commit message v3: fixed typos in commit msg Signed-off-by: Lukasz Kalamarz Cc: Katarzyna Dec Cc: Antonio Argenziano Cc: Daniele Ceraolo Spurio Cc: Ewelina Musial Reviewed-by: Katarzyna Dec --- lib/rendercopy_gen7.c | 108 +++++++++++++++++++++++++------------------------- 1 file changed, 54 insertions(+), 54 deletions(-) (limited to 'lib/rendercopy_gen7.c') diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c index 82e33288..bdcf3c7b 100644 --- a/lib/rendercopy_gen7.c +++ b/lib/rendercopy_gen7.c @@ -101,35 +101,35 @@ gen7_bind_buf(struct intel_batchbuffer *batch, static void gen7_emit_vertex_elements(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_3DSTATE_VERTEX_ELEMENTS | + OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | ((2 * (1 + 2)) + 1 - 2)); - OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID | - SURFACEFORMAT_R32G32B32A32_FLOAT << GEN7_VE0_FORMAT_SHIFT | - 0 << GEN7_VE0_OFFSET_SHIFT); + OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | + 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_0_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_1_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* x,y */ - OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID | - SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT | - 0 << GEN7_VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT | - GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT | - GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | + 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ + OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); /* s,t */ - OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID | - SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT | - 4 << GEN7_VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT | - GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT | - GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | + 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ + OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); } static uint32_t @@ -166,11 +166,11 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch, int width, int height, uint32_t offset) { - OUT_BATCH(GEN7_3DSTATE_VERTEX_BUFFERS | (5 - 2)); - OUT_BATCH(0 << GEN7_VB0_BUFFER_INDEX_SHIFT | - GEN7_VB0_VERTEXDATA | + OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2)); + OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | + VB0_VERTEXDATA | GEN7_VB0_ADDRESS_MODIFY_ENABLE | - 4 * 2 << GEN7_VB0_BUFFER_PITCH_SHIFT); + 4 * 2 << VB0_BUFFER_PITCH_SHIFT); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset); OUT_BATCH(~0); @@ -207,7 +207,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch, static void gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst) { - OUT_BATCH(GEN7_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); OUT_BATCH(0); OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1)); OUT_BATCH(0); @@ -216,13 +216,13 @@ gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst static uint32_t gen7_create_blend_state(struct intel_batchbuffer *batch) { - struct gen7_blend_state *blend; + struct gen6_blend_state *blend; blend = intel_batchbuffer_subdata_alloc(batch, sizeof(*blend), 64); - blend->blend0.dest_blend_factor = GEN7_BLENDFACTOR_ZERO; - blend->blend0.source_blend_factor = GEN7_BLENDFACTOR_ONE; - blend->blend0.blend_func = GEN7_BLENDFUNCTION_ADD; + blend->blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO; + blend->blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE; + blend->blend0.blend_func = GEN6_BLENDFUNCTION_ADD; blend->blend1.post_blend_clamp_enable = 1; blend->blend1.pre_blend_clamp_enable = 1; @@ -232,7 +232,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch) static void gen7_emit_state_base_address(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2)); + OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(0); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); @@ -248,7 +248,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch) static uint32_t gen7_create_cc_viewport(struct intel_batchbuffer *batch) { - struct gen7_cc_viewport *vp; + struct gen6_cc_viewport *vp; vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32); vp->min_depth = -1.e35; @@ -275,12 +275,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch) ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 32); - ss->ss0.min_filter = GEN7_MAPFILTER_NEAREST; - ss->ss0.mag_filter = GEN7_MAPFILTER_NEAREST; + ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST; + ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST; - ss->ss3.r_wrap_mode = GEN7_TEXCOORDMODE_CLAMP; - ss->ss3.s_wrap_mode = GEN7_TEXCOORDMODE_CLAMP; - ss->ss3.t_wrap_mode = GEN7_TEXCOORDMODE_CLAMP; + ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; ss->ss3.non_normalized_coord = 1; @@ -297,13 +297,13 @@ gen7_emit_sampler(struct intel_batchbuffer *batch, uint32_t sampler_off) static void gen7_emit_multisample(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE | (4 - 2)); - OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | - GEN7_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ + OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (4 - 2)); + OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | + GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ OUT_BATCH(0); OUT_BATCH(0); - OUT_BATCH(GEN7_3DSTATE_SAMPLE_MASK | (2 - 2)); + OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); OUT_BATCH(1); } @@ -335,7 +335,7 @@ gen7_emit_urb(struct intel_batchbuffer *batch) static void gen7_emit_vs(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_3DSTATE_VS | (6 - 2)); + OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2)); OUT_BATCH(0); /* no VS kernel */ OUT_BATCH(0); OUT_BATCH(0); @@ -378,7 +378,7 @@ gen7_emit_ds(struct intel_batchbuffer *batch) static void gen7_emit_gs(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_3DSTATE_GS | (7 - 2)); + OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2)); OUT_BATCH(0); /* no GS kernel */ OUT_BATCH(0); OUT_BATCH(0); @@ -398,10 +398,10 @@ gen7_emit_streamout(struct intel_batchbuffer *batch) static void gen7_emit_sf(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_3DSTATE_SF | (7 - 2)); + OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2)); OUT_BATCH(0); - OUT_BATCH(GEN7_3DSTATE_SF_CULL_NONE); - OUT_BATCH(2 << GEN7_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); + OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); + OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); @@ -454,7 +454,7 @@ gen7_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel_off) static void gen7_emit_clip(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_3DSTATE_CLIP | (4 - 2)); + OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2)); OUT_BATCH(0); OUT_BATCH(0); /* pass-through */ OUT_BATCH(0); @@ -466,7 +466,7 @@ gen7_emit_clip(struct intel_batchbuffer *batch) static void gen7_emit_wm(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN7_3DSTATE_WM | (3 - 2)); + OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2)); OUT_BATCH(GEN7_WM_DISPATCH_ENABLE | GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); OUT_BATCH(0); @@ -476,8 +476,8 @@ static void gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch) { OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2)); - OUT_BATCH(SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | - GEN7_DEPTHFORMAT_D32_FLOAT << GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); + OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | + GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); OUT_BATCH(0); /* disable depth, stencil and hiz */ OUT_BATCH(0); OUT_BATCH(0); @@ -520,7 +520,7 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch, igt_assert(batch->ptr < &batch->buffer[4095]); batch->ptr = batch->buffer; - OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_3D); + OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); gen7_emit_state_base_address(batch); gen7_emit_multisample(batch); @@ -546,8 +546,8 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch, gen7_emit_binding_table(batch, src, dst, ps_binding_table); gen7_emit_drawing_rectangle(batch, dst); - OUT_BATCH(GEN7_3DPRIMITIVE | (7 - 2)); - OUT_BATCH(GEN7_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST); + OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2)); + OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST); OUT_BATCH(3); OUT_BATCH(0); OUT_BATCH(1); /* single instance */ -- cgit v1.2.3