From a2142371c1c58975726e2a259174b61070799ccf Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 7 Jun 2022 16:39:53 +0200 Subject: i915/gem_exec_balancer: Fix execution of parallel-submit on dg2+ From dg2, there are multiple compute engines which conflict with the parallel-submit restriction; check for the illegal engine class prior to running the test. And from dg2, MI_ATOMIC is only valid for use with system memory for INC, DEC and MOV operation, not the ADD used in the test workload. Replace the ADD+1 with an INC, so that the same workload runs on all platforms. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6157 Signed-off-by: Chris Wilson Reviewed-by: Nirmoy Das Signed-off-by: Nirmoy Das --- lib/intel_reg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/intel_reg.h b/lib/intel_reg.h index cb627288..e26ee82a 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -2645,8 +2645,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16)) /* Atomics */ -#define MI_ATOMIC ((0x2f << 23) | 2) +#define MI_ATOMIC ((0x2f << 23) | 1) #define MI_ATOMIC_INLINE_DATA (1 << 18) +#define MI_ATOMIC_INC (0x5 << 8) #define MI_ATOMIC_ADD (0x7 << 8) /* Batch */ -- cgit v1.2.3