diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2021-10-08 14:56:31 -0700 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2022-01-06 13:50:37 +0200 |
| commit | ee89365613084ad33059259d78cd350827950e6b (patch) | |
| tree | c357fd87ec04175be914532c43b1f1d45b9d1996 | |
| parent | f56c41968d902ad1be2bce1f1259494dbbd58511 (diff) | |
drm/i915/xehp: Determine which tile raised an interrupt
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then we read the
usual interrupt registers from the appropriate tile.
Note that this is just the first step of handling interrupts properly on
multi-tile platforms. Subsequent patches will convert other parts of
the interrupt handling flow.
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 21f75b069fa8..810df3b3ffbc 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2772,37 +2772,38 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) { struct drm_i915_private * const i915 = arg; struct intel_gt *gt = to_gt(i915); - void __iomem * const regs = gt->uncore->regs; + void __iomem * const t0_regs = gt->uncore->regs; u32 master_tile_ctl, master_ctl; - u32 gu_misc_iir; + u32 gu_misc_iir = 0; + unsigned int i; if (!intel_irqs_enabled(i915)) return IRQ_NONE; - master_tile_ctl = dg1_master_intr_disable(regs); + master_tile_ctl = dg1_master_intr_disable(t0_regs); if (!master_tile_ctl) { - dg1_master_intr_enable(regs); + dg1_master_intr_enable(t0_regs); return IRQ_NONE; } - /* FIXME: we only support tile 0 for now. */ - if (master_tile_ctl & DG1_MSTR_TILE(0)) { + for_each_gt(gt, i915, i) { + void __iomem *const regs = gt->uncore->regs; + + if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0) + continue; + master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); - } else { - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl); - dg1_master_intr_enable(regs); - return IRQ_NONE; - } - gen11_gt_irq_handler(gt, master_ctl); + gen11_gt_irq_handler(gt, master_ctl); + + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); + } if (master_ctl & GEN11_DISPLAY_IRQ) gen11_display_irq_handler(i915); - gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl); - - dg1_master_intr_enable(regs); + dg1_master_intr_enable(t0_regs); gen11_gu_misc_irq_handler(gt, gu_misc_iir); |