diff options
| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2017-02-17 14:32:21 +1100 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2017-02-17 14:32:21 +1100 |
| commit | 2edf2b0ec804fb66250e5998a75c8e43df329ac8 (patch) | |
| tree | 251be7fdd8c16aa13bbed428a5b81ded3da194be | |
| parent | d5f1dc97dbf3a671ca8d19a4a2ade2bc4f4616ac (diff) | |
| parent | 2039834c86f3b1e1eb6b1484d9f3b29857bf6adf (diff) | |
Merge remote-tracking branch 'pinctrl/for-next'
83 files changed, 9874 insertions, 2622 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index de1378b4efad..7c85dca4221a 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -23,6 +23,7 @@ Required properties: "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" "allwinner,sun50i-a64-pinctrl" + "allwinner,sun50i-h5-r-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt index 457b2c68d47b..8c5d27c5b562 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -19,7 +19,7 @@ iomuxc: iomuxc@30330000 { reg = <0x30330000 0x10000>; }; -Pheriparials using pads from iomuxc-lpsr support low state retention power +Peripherals using pads from iomuxc-lpsr support low state retention power state, under LPSR mode GPIO's state of pads are retain. Please refer to fsl,imx-pinctrl.txt in this directory for common binding part diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt new file mode 100644 index 000000000000..97aef67ee769 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt @@ -0,0 +1,46 @@ +* Marvell 98dx3236 pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage + +Required properties: +- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl" +- reg: register specifier of MPP registers + +This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants + +name pins functions +================================================================================ +mpp0 0 gpo, spi0(mosi), dev(ad8) +mpp1 1 gpio, spi0(miso), dev(ad9) +mpp2 2 gpo, spi0(sck), dev(ad10) +mpp3 3 gpio, spi0(cs0), dev(ad11) +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0) +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs) +mpp6 6 gpo, sd0(clk), dev(a2) +mpp7 7 gpio, sd0(d0), dev(ale0) +mpp8 8 gpio, sd0(d1), dev(ale1) +mpp9 9 gpio, sd0(d2), dev(ready0) +mpp10 10 gpio, sd0(d3), dev(ad12) +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13) +mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14) +mpp13 13 gpio, intr(out), dev(ad15) +mpp14 14 gpio, i2c0(sck) +mpp15 15 gpio, i2c0(sda) +mpp16 16 gpo, dev(oe) +mpp17 17 gpo, dev(clkout) +mpp18 18 gpio, uart1(txd) +mpp19 19 gpio, uart1(rxd), dev(rb) +mpp20 20 gpo, dev(we0) +mpp21 21 gpo, dev(ad0) +mpp22 22 gpo, dev(ad1) +mpp23 23 gpo, dev(ad2) +mpp24 24 gpo, dev(ad3) +mpp25 25 gpo, dev(ad4) +mpp26 26 gpo, dev(ad5) +mpp27 27 gpo, dev(ad6) +mpp28 28 gpo, dev(ad7) +mpp29 29 gpo, dev(a0) +mpp30 30 gpo, dev(a1) +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1) +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt index 730444a9a4de..6c0ea155b708 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt @@ -44,16 +44,16 @@ mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) mpp17 17 gpio, sdio(d3) mpp18 18 gpo, nand(io0) mpp19 19 gpo, nand(io1) -mpp20 20 gpio, mii(rxerr) -mpp21 21 gpio, audio(spdifi) -mpp22 22 gpio, audio(spdifo) -mpp23 23 gpio, audio(rmclk) -mpp24 24 gpio, audio(bclk) -mpp25 25 gpio, audio(sdo) -mpp26 26 gpio, audio(lrclk) -mpp27 27 gpio, audio(mclk) -mpp28 28 gpio, audio(sdi) -mpp29 29 gpio, audio(extclk) +mpp35 35 gpio, mii(rxerr) +mpp36 36 gpio, audio(spdifi) +mpp37 37 gpio, audio(spdifo) +mpp38 38 gpio, audio(rmclk) +mpp39 39 gpio, audio(bclk) +mpp40 40 gpio, audio(sdo) +mpp41 41 gpio, audio(lrclk) +mpp42 42 gpio, audio(mclk) +mpp43 43 gpio, audio(sdi) +mpp44 44 gpio, audio(extclk) * Marvell Kirkwood 88f6190 diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt index 2ad18c4ea55c..b98e6f030da8 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -1,25 +1,38 @@ +====================== Aspeed Pin Controllers ----------------------- +====================== The Aspeed SoCs vary in functionality inside a generation but have a common mux device register layout. -Required properties: -- compatible : Should be any one of the following: - "aspeed,ast2400-pinctrl" - "aspeed,g4-pinctrl" - "aspeed,ast2500-pinctrl" - "aspeed,g5-pinctrl" +Required properties for g4: +- compatible : Should be one of the following: + "aspeed,ast2400-pinctrl" + "aspeed,g4-pinctrl" -The pin controller node should be a child of a syscon node with the required +Required properties for g5: +- compatible : Should be one of the following: + "aspeed,ast2500-pinctrl" + "aspeed,g5-pinctrl" + +- aspeed,external-nodes: A cell of phandles to external controller nodes: + 0: compatible with "aspeed,ast2500-gfx", "syscon" + 1: compatible with "aspeed,ast2500-lhc", "syscon" + +The pin controller node should be the child of a syscon node with the required property: -- compatible: "syscon", "simple-mfd" + +- compatible : Should be one of the following: + "aspeed,ast2400-scu", "syscon", "simple-mfd" + "aspeed,g4-scu", "syscon", "simple-mfd" + "aspeed,ast2500-scu", "syscon", "simple-mfd" + "aspeed,g5-scu", "syscon", "simple-mfd" Refer to the the bindings described in Documentation/devicetree/bindings/mfd/syscon.txt Subnode Format --------------- +============== The required properties of child nodes are (as defined in pinctrl-bindings): - function @@ -31,26 +44,43 @@ supported: aspeed,ast2400-pinctrl, aspeed,g4-pinctrl: -ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 -I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1 -MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3 -NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16 -ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3 -TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30 -VPO12 VPO24 +ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 +ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2 +GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 +I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1 +MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 +NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0 +PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1 +ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK +SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ +SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4 +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS +VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: -GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 -I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 -RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6 -TIMER7 TIMER8 VGABIOSROM - - -Examples: +ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6 +ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4 +GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 +I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME +LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 +NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2 +NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4 +PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10 +SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9 +SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ +SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0 +SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 +TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2 + +Examples +======== + +g4 Example +---------- syscon: scu@1e6e2000 { - compatible = "syscon", "simple-mfd"; + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; pinctrl: pinctrl { @@ -63,5 +93,56 @@ syscon: scu@1e6e2000 { }; }; +g5 Example +---------- + +ahb { + apb { + syscon: scu@1e6e2000 { + compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl { + compatible = "aspeed,g5-pinctrl"; + aspeed,external-nodes = <&gfx &lhc>; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + }; + }; + + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + }; + }; + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>; + + lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; + }; + }; + }; +}; + Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices. diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 1baf19eecabf..5e00a21de2bf 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -13,6 +13,7 @@ Required Properties: - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, + - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. diff --git a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt new file mode 100644 index 000000000000..c3ed1232b6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt @@ -0,0 +1,47 @@ +* Pin configuration for TI IODELAY controller + +TI dra7 based SoCs such as am57xx have a controller for setting the IO delay +for each pin. For most part the IO delay values are programmed by the bootloader, +but some pins need to be configured dynamically by the kernel such as the +MMC pins. + +Required Properties: + + - compatible: Must be "ti,dra7-iodelay" + - reg: Base address and length of the memory resource used + - #address-cells: Number of address cells + - #size-cells: Size of cells + - #pinctrl-cells: Number of pinctrl cells, must be 2. See also + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example +------- + +In the SoC specific dtsi file: + + dra7_iodelay_core: padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + }; + +In board-specific file: + +&dra7_iodelay_core { + mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + >; + }; +}; diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index 0d3b9ce0a0b9..54bd5faa8782 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -79,9 +79,7 @@ int __init foo_probe(void) { struct pinctrl_dev *pctl; - pctl = pinctrl_register(&foo_desc, <PARENT>, NULL); - if (!pctl) - pr_err("could not register foo pin driver\n"); + return pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl); } To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 29fc95f19bb5..748cfb8d5212 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -57,7 +57,6 @@ struct exynos_wkup_irq { struct exynos_pm_data { const struct exynos_wkup_irq *wkup_irq; unsigned int wake_disable_mask; - const unsigned int *release_ret_regs; void (*pm_prepare)(void); void (*pm_resume_prepare)(void); @@ -95,47 +94,6 @@ static const struct exynos_wkup_irq exynos5250_wkup_irq[] = { { /* sentinel */ }, }; -static const unsigned int exynos_release_ret_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - REG_TABLE_END, -}; - -static const unsigned int exynos3250_release_ret_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - S5P_PAD_RET_MMC2_OPTION, - S5P_PAD_RET_SPI_OPTION, - REG_TABLE_END, -}; - -static const unsigned int exynos5420_release_ret_regs[] = { - EXYNOS_PAD_RET_DRAM_OPTION, - EXYNOS_PAD_RET_MAUDIO_OPTION, - EXYNOS_PAD_RET_JTAG_OPTION, - EXYNOS5420_PAD_RET_GPIO_OPTION, - EXYNOS5420_PAD_RET_UART_OPTION, - EXYNOS5420_PAD_RET_MMCA_OPTION, - EXYNOS5420_PAD_RET_MMCB_OPTION, - EXYNOS5420_PAD_RET_MMCC_OPTION, - EXYNOS5420_PAD_RET_HSI_OPTION, - EXYNOS_PAD_RET_EBIA_OPTION, - EXYNOS_PAD_RET_EBIB_OPTION, - EXYNOS5420_PAD_RET_SPI_OPTION, - EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, - REG_TABLE_END, -}; - static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) { const struct exynos_wkup_irq *wkup_irq; @@ -441,15 +399,6 @@ static int exynos5420_pm_suspend(void) return 0; } -static void exynos_pm_release_retention(void) -{ - unsigned int i; - - for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) - pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, - pm_data->release_ret_regs[i]); -} - static void exynos_pm_resume(void) { u32 cpuid = read_cpuid_part(); @@ -457,9 +406,6 @@ static void exynos_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - if (cpuid == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); @@ -481,9 +427,6 @@ static void exynos3250_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); if (call_firmware_op(resume) == -ENOSYS @@ -521,9 +464,6 @@ static void exynos5420_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); early_wakeup: @@ -636,7 +576,6 @@ static const struct platform_suspend_ops exynos_suspend_ops = { static const struct exynos_pm_data exynos3250_pm_data = { .wkup_irq = exynos3250_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos3250_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos3250_pm_resume, .pm_prepare = exynos3250_pm_prepare, @@ -646,7 +585,6 @@ static const struct exynos_pm_data exynos3250_pm_data = { static const struct exynos_pm_data exynos4_pm_data = { .wkup_irq = exynos4_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos_pm_resume, .pm_prepare = exynos_pm_prepare, @@ -656,7 +594,6 @@ static const struct exynos_pm_data exynos4_pm_data = { static const struct exynos_pm_data exynos5250_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos_pm_resume, .pm_prepare = exynos_pm_prepare, @@ -666,7 +603,6 @@ static const struct exynos_pm_data exynos5250_pm_data = { static const struct exynos_pm_data exynos5420_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = (0x7F << 7) | (0x1F << 1), - .release_ret_regs = exynos5420_release_ret_regs, .pm_resume_prepare = exynos5420_prepare_pm_resume, .pm_resume = exynos5420_pm_resume, .pm_suspend = exynos5420_pm_suspend, diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 2d5f08015e34..07cee14a363b 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -155,13 +155,6 @@ static const struct platform_suspend_ops s5pv210_suspend_ops = { */ static void s5pv210_pm_resume(void) { - u32 tmp; - - tmp = __raw_readl(S5P_OTHERS); - tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\ - S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART); - __raw_writel(tmp , S5P_OTHERS); - s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); } diff --git a/arch/arm/mach-s5pv210/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h index 4640f0f03c12..fb3eb77412db 100644 --- a/arch/arm/mach-s5pv210/regs-clock.h +++ b/arch/arm/mach-s5pv210/regs-clock.h @@ -188,10 +188,6 @@ #define S5P_SLEEP_CFG_USBOSC_EN (1 << 1) /* OTHERS Resgister */ -#define S5P_OTHERS_RET_IO (1 << 31) -#define S5P_OTHERS_RET_CF (1 << 30) -#define S5P_OTHERS_RET_MMC (1 << 29) -#define S5P_OTHERS_RET_UART (1 << 28) #define S5P_OTHERS_USB_SIG_MASK (1 << 16) /* S5P_DAC_CONTROL */ diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 03a5925a423c..6e4b278a82f1 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -15,58 +15,76 @@ #include <linux/io.h> #include <linux/spinlock.h> #include <linux/platform_device.h> +#include <linux/gpio.h> #include <linux/gpio/driver.h> #include <linux/pinctrl/consumer.h> +struct aspeed_bank_props { + unsigned int bank; + u32 input; + u32 output; +}; + +struct aspeed_gpio_config { + unsigned int nr_gpios; + const struct aspeed_bank_props *props; +}; + struct aspeed_gpio { struct gpio_chip chip; spinlock_t lock; void __iomem *base; int irq; + const struct aspeed_gpio_config *config; }; struct aspeed_gpio_bank { uint16_t val_regs; uint16_t irq_regs; - const char names[4]; + const char names[4][3]; }; static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { { .val_regs = 0x0000, .irq_regs = 0x0008, - .names = { 'A', 'B', 'C', 'D' }, + .names = { "A", "B", "C", "D" }, }, { .val_regs = 0x0020, .irq_regs = 0x0028, - .names = { 'E', 'F', 'G', 'H' }, + .names = { "E", "F", "G", "H" }, }, { .val_regs = 0x0070, .irq_regs = 0x0098, - .names = { 'I', 'J', 'K', 'L' }, + .names = { "I", "J", "K", "L" }, }, { .val_regs = 0x0078, .irq_regs = 0x00e8, - .names = { 'M', 'N', 'O', 'P' }, + .names = { "M", "N", "O", "P" }, }, { .val_regs = 0x0080, .irq_regs = 0x0118, - .names = { 'Q', 'R', 'S', 'T' }, + .names = { "Q", "R", "S", "T" }, }, { .val_regs = 0x0088, .irq_regs = 0x0148, - .names = { 'U', 'V', 'W', 'X' }, + .names = { "U", "V", "W", "X" }, + }, + { + .val_regs = 0x01E0, + .irq_regs = 0x0178, + .names = { "Y", "Z", "AA", "AB" }, + }, + { + .val_regs = 0x01E8, + .irq_regs = 0x01A8, + .names = { "AC", "", "", "" }, }, - /* - * A bank exists for { 'Y', 'Z', "AA", "AB" }, but is not implemented. - * Only half of GPIOs Y support interrupt configuration, and none of Z, - * AA or AB do as they are output only. - */ }; #define GPIO_BANK(x) ((x) >> 5) @@ -90,6 +108,51 @@ static const struct aspeed_gpio_bank *to_bank(unsigned int offset) return &aspeed_gpio_banks[bank]; } +static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) +{ + return !(props->input || props->output); +} + +static inline const struct aspeed_bank_props *find_bank_props( + struct aspeed_gpio *gpio, unsigned int offset) +{ + const struct aspeed_bank_props *props = gpio->config->props; + + while (!is_bank_props_sentinel(props)) { + if (props->bank == GPIO_BANK(offset)) + return props; + props++; + } + + return NULL; +} + +static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) +{ + const struct aspeed_bank_props *props = find_bank_props(gpio, offset); + const struct aspeed_gpio_bank *bank = to_bank(offset); + unsigned int group = GPIO_OFFSET(offset) / 8; + + return bank->names[group][0] != '\0' && + (!props || ((props->input | props->output) & GPIO_BIT(offset))); +} + +static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) +{ + const struct aspeed_bank_props *props = find_bank_props(gpio, offset); + + return !props || (props->input & GPIO_BIT(offset)); +} + +#define have_irq(g, o) have_input((g), (o)) + +static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) +{ + const struct aspeed_bank_props *props = find_bank_props(gpio, offset); + + return !props || (props->output & GPIO_BIT(offset)); +} + static void __iomem *bank_val_reg(struct aspeed_gpio *gpio, const struct aspeed_gpio_bank *bank, unsigned int reg) @@ -152,6 +215,9 @@ static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) unsigned long flags; u32 reg; + if (!have_input(gpio, offset)) + return -ENOTSUPP; + spin_lock_irqsave(&gpio->lock, flags); reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); @@ -170,6 +236,9 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc, unsigned long flags; u32 reg; + if (!have_output(gpio, offset)) + return -ENOTSUPP; + spin_lock_irqsave(&gpio->lock, flags); reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); @@ -189,6 +258,12 @@ static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) unsigned long flags; u32 val; + if (!have_input(gpio, offset)) + return GPIOF_DIR_OUT; + + if (!have_output(gpio, offset)) + return GPIOF_DIR_IN; + spin_lock_irqsave(&gpio->lock, flags); val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset); @@ -205,10 +280,17 @@ static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, u32 *bit) { int offset; + struct aspeed_gpio *internal; offset = irqd_to_hwirq(d); - *gpio = irq_data_get_irq_chip_data(d); + internal = irq_data_get_irq_chip_data(d); + + /* This might be a bit of a questionable place to check */ + if (!have_irq(internal, offset)) + return -ENOTSUPP; + + *gpio = internal; *bank = to_bank(offset); *bit = GPIO_BIT(offset); @@ -364,6 +446,28 @@ static struct irq_chip aspeed_gpio_irqchip = { .irq_set_type = aspeed_gpio_set_type, }; +static void set_irq_valid_mask(struct aspeed_gpio *gpio) +{ + const struct aspeed_bank_props *props = gpio->config->props; + + while (!is_bank_props_sentinel(props)) { + unsigned int offset; + const unsigned long int input = props->input; + + /* Pretty crummy approach, but similar to GPIO core */ + for_each_clear_bit(offset, &input, 32) { + unsigned int i = props->bank * 32 + offset; + + if (i >= gpio->config->nr_gpios) + break; + + clear_bit(i, gpio->chip.irq_valid_mask); + } + + props++; + } +} + static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, struct platform_device *pdev) { @@ -375,6 +479,8 @@ static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, gpio->irq = rc; + set_irq_valid_mask(gpio); + rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, 0, handle_bad_irq, IRQ_TYPE_NONE); if (rc) { @@ -390,6 +496,9 @@ static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) { + if (!have_gpio(gpiochip_get_data(chip), offset)) + return -ENODEV; + return pinctrl_request_gpio(chip->base + offset); } @@ -398,8 +507,46 @@ static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) pinctrl_free_gpio(chip->base + offset); } +/* + * Any banks not specified in a struct aspeed_bank_props array are assumed to + * have the properties: + * + * { .input = 0xffffffff, .output = 0xffffffff } + */ + +static const struct aspeed_bank_props ast2400_bank_props[] = { + /* input output */ + { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ + { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ + { }, +}; + +static const struct aspeed_gpio_config ast2400_config = + /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ + { .nr_gpios = 220, .props = ast2400_bank_props, }; + +static const struct aspeed_bank_props ast2500_bank_props[] = { + /* input output */ + { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ + { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ + { 7, 0x000000ff, 0x000000ff }, /* AC */ + { }, +}; + +static const struct aspeed_gpio_config ast2500_config = + /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ + { .nr_gpios = 232, .props = ast2500_bank_props, }; + +static const struct of_device_id aspeed_gpio_of_table[] = { + { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, + { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, + {} +}; +MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); + static int __init aspeed_gpio_probe(struct platform_device *pdev) { + const struct of_device_id *gpio_id; struct aspeed_gpio *gpio; struct resource *res; int rc; @@ -415,8 +562,13 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) spin_lock_init(&gpio->lock); - gpio->chip.ngpio = ARRAY_SIZE(aspeed_gpio_banks) * 32; + gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); + if (!gpio_id) + return -EINVAL; + + gpio->config = gpio_id->data; + gpio->chip.ngpio = gpio->config->nr_gpios; gpio->chip.parent = &pdev->dev; gpio->chip.direction_input = aspeed_gpio_dir_in; gpio->chip.direction_output = aspeed_gpio_dir_out; @@ -427,6 +579,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) gpio->chip.set = aspeed_gpio_set; gpio->chip.label = dev_name(&pdev->dev); gpio->chip.base = -1; + gpio->chip.irq_need_valid_mask = true; rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); if (rc < 0) @@ -435,13 +588,6 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) return aspeed_gpio_setup_irqs(gpio, pdev); } -static const struct of_device_id aspeed_gpio_of_table[] = { - { .compatible = "aspeed,ast2400-gpio" }, - { .compatible = "aspeed,ast2500-gpio" }, - {} -}; -MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); - static struct platform_driver aspeed_gpio_driver = { .driver = { .name = KBUILD_MODNAME, diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 54044a8ecbd7..8f8c2af45781 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -8,9 +8,16 @@ config PINCTRL menu "Pin controllers" depends on PINCTRL +config GENERIC_PINCTRL_GROUPS + bool + config PINMUX bool "Support pin multiplexing controllers" if COMPILE_TEST +config GENERIC_PINMUX_FUNCTIONS + bool + select PINMUX + config PINCONF bool "Support pin configuration controllers" if COMPILE_TEST @@ -159,8 +166,8 @@ config PINCTRL_ROCKCHIP config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF - select PINMUX - select PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help This selects the device tree based generic pinctrl driver. @@ -293,6 +300,7 @@ source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/stm32/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" +source "drivers/pinctrl/ti/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 25d50a86981d..a251f439626f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_PINCTRL_MTK) += mediatek/ diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index a21b071ff290..7de596e2b9d4 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -43,9 +43,18 @@ * Not all pins have their signals defined (yet). */ +#define D6 0 +SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); + +#define B5 1 +SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); + #define A4 2 SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); +#define E6 3 +SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); + #define I2C9_DESC SIG_DESC_SET(SCU90, 22) #define C5 4 @@ -80,6 +89,26 @@ MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); FUNC_GROUP_DECL(TIMER8, D5); FUNC_GROUP_DECL(MDIO2, A3, D5); +#define J21 8 +SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8)); + +#define J20 9 +SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9)); + +#define H18 10 +SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10)); + +#define F18 11 +SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11)); + +#define E19 12 +SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); +SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); +SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS); +SS_PIN_DECL(E19, GPIOB4, LPCRST); + +FUNC_GROUP_DECL(LPCRST, E19); + #define H19 13 #define H19_DESC SIG_DESC_SET(SCU80, 13) SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); @@ -92,6 +121,19 @@ FUNC_GROUP_DECL(LPCSMI, H19); #define H20 14 SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); +#define E18 15 +SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST, + SIG_DESC_SET(SCU80, 15), + SIG_DESC_BIT(SCU90, 31, 0), + SIG_DESC_SET(SCU3C, 3)); +SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1, + SIG_DESC_SET(SCU80, 15), + SIG_DESC_SET(SCU90, 31)); +MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1); + +FUNC_GROUP_DECL(EXTRST, E18); +FUNC_GROUP_DECL(SPICS1, E18); + #define SD1_DESC SIG_DESC_SET(SCU90, 0) #define I2C10_DESC SIG_DESC_SET(SCU90, 23) @@ -170,6 +212,62 @@ MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); FUNC_GROUP_DECL(GPID0, A18, D16); +#define GPID2_DESC SIG_DESC_SET(SCU8C, 9) + +#define B17 26 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); +SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); +MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN); + +#define A17 27 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); +SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); +MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT); + +FUNC_GROUP_DECL(GPID2, B17, A17); + +#define GPID4_DESC SIG_DESC_SET(SCU8C, 10) + +#define C16 28 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); +MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN); + +#define B16 29 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); +MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT); + +FUNC_GROUP_DECL(GPID4, C16, B16); + +#define GPID6_DESC SIG_DESC_SET(SCU8C, 11) + +#define A16 30 +SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); +MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN); + +#define E15 31 +SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); +MS_PIN_DECL(E15, GPIOD7, SD2WP, GPID6OUT); + +FUNC_GROUP_DECL(GPID6, A16, E15); +FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15); +FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15); + #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) @@ -266,6 +364,15 @@ MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); FUNC_GROUP_DECL(NDCD4, B19); FUNC_GROUP_DECL(SIOPBI, B19); +#define A20 42 +SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL(SIOPWRGD, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); +MS_PIN_DECL(A20, GPIOF2, NDSR4, SIOPWRGD); +FUNC_GROUP_DECL(NDSR4, A20); +FUNC_GROUP_DECL(SIOPWRGD, A20); + #define D17 43 SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); @@ -275,7 +382,17 @@ MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); FUNC_GROUP_DECL(NRI4, D17); FUNC_GROUP_DECL(SIOPBO, D17); -FUNC_GROUP_DECL(ACPI, B19, D17); +#define B18 44 +SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28)); + +#define A19 45 +SIG_EXPR_LIST_DECL_SINGLE(NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); +SIG_EXPR_DECL(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); +SIG_EXPR_DECL(SIOSCI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); +MS_PIN_DECL(A19, GPIOF5, NDTS4, SIOSCI); +FUNC_GROUP_DECL(NDTS4, A19); +FUNC_GROUP_DECL(SIOSCI, A19); #define E16 46 SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); @@ -283,6 +400,34 @@ SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); #define C17 47 SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); +#define A14 48 +SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0)); + +#define E13 49 +SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1)); + +#define D13 50 +SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2)); + +#define C13 51 +SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3)); + +#define B13 52 +SIG_EXPR_LIST_DECL_SINGLE(OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); +MS_PIN_DECL(B13, GPIOG4, OSCCLK, WDTRST1); + +FUNC_GROUP_DECL(OSCCLK, B13); +FUNC_GROUP_DECL(WDTRST1, B13); + +#define Y21 53 +SIG_EXPR_LIST_DECL_SINGLE(USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); +MS_PIN_DECL(Y21, GPIOG5, USBCKI, WDTRST2); + +FUNC_GROUP_DECL(USBCKI, Y21); +FUNC_GROUP_DECL(WDTRST2, Y21); + #define AA22 54 SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6)); @@ -292,7 +437,7 @@ SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); #define UART6_DESC SIG_DESC_SET(SCU90, 7) #define ROM16_DESC SIG_DESC_SET(SCU90, 6) #define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4) -#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 } +#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 } #define A8 56 SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); @@ -352,6 +497,93 @@ MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); +#define SPI1_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } +#define SPI1DEBUG_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } +#define SPI1PASSTHRU_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } + +#define C22 64 +SIG_EXPR_DECL(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(C22, GPIOI0, SYSCS); + +#define G18 65 +SIG_EXPR_DECL(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(G18, GPIOI1, SYSCK); + +#define D19 66 +SIG_EXPR_DECL(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSDO, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(D19, GPIOI2, SYSDO); + +#define C20 67 +SIG_EXPR_DECL(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(SYSDI, SPI1DEBUG, SPI1PASSTHRU); +SS_PIN_DECL(C20, GPIOI3, SYSDI); + +#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) + +#define B22 68 +SIG_EXPR_DECL(SPI1CS0, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), + SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), + SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(B22, GPIOI4, SPI1CS0, VBCS); + +#define G19 69 +SIG_EXPR_DECL(SPI1CK, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), + SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), + SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(G19, GPIOI5, SPI1CK, VBCK); + +#define C18 70 +SIG_EXPR_DECL(SPI1DO, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DO, SIG_EXPR_PTR(SPI1DO, SPI1), + SIG_EXPR_PTR(SPI1DO, SPI1DEBUG), + SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBDO, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(C18, GPIOI6, SPI1DO, VBDO); + +#define E20 71 +SIG_EXPR_DECL(SPI1DI, SPI1, SPI1_DESC); +SIG_EXPR_DECL(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DI, SIG_EXPR_PTR(SPI1DI, SPI1), + SIG_EXPR_PTR(SPI1DI, SPI1DEBUG), + SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU)); +SIG_EXPR_LIST_DECL_SINGLE(VBDI, VGABIOS_ROM, VB_DESC); +MS_PIN_DECL(E20, GPIOI7, SPI1DI, VBDI); + +FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20); +FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20); +FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20); +FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20); + +#define J5 72 +SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8)); + +#define J4 73 +SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9)); + +#define K5 74 +SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10)); + #define J3 75 SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); @@ -418,9 +650,9 @@ FUNC_GROUP_DECL(I2C8, G5, F3); #define U1 88 SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); -#define VPI18_DESC { SCU90, GENMASK(5, 4), 1, 0 } -#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } -#define VPI30_DESC { SCU90, GENMASK(5, 4), 3, 0 } +#define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } +#define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } #define T5 89 #define T5_DESC SIG_DESC_SET(SCU84, 17) @@ -496,6 +728,102 @@ SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC); MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1); FUNC_GROUP_DECL(RXD1, U5); +#define V3 96 +#define V3_DESC SIG_DESC_SET(SCU84, 24) +SIG_EXPR_DECL(VPIOB2, VPI18, VPI18_DESC, V3_DESC); +SIG_EXPR_DECL(VPIOB2, VPI24, VPI24_DESC, V3_DESC); +SIG_EXPR_DECL(VPIOB2, VPI30, VPI30_DESC, V3_DESC); +SIG_EXPR_LIST_DECL(VPIOB2, SIG_EXPR_PTR(VPIOB2, VPI18), + SIG_EXPR_PTR(VPIOB2, VPI24), + SIG_EXPR_PTR(VPIOB2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, V3_DESC); +MS_PIN_DECL(V3, GPIOM0, VPIOB2, NCTS2); +FUNC_GROUP_DECL(NCTS2, V3); + +#define W2 97 +#define W2_DESC SIG_DESC_SET(SCU84, 25) +SIG_EXPR_DECL(VPIOB3, VPI18, VPI18_DESC, W2_DESC); +SIG_EXPR_DECL(VPIOB3, VPI24, VPI24_DESC, W2_DESC); +SIG_EXPR_DECL(VPIOB3, VPI30, VPI30_DESC, W2_DESC); +SIG_EXPR_LIST_DECL(VPIOB3, SIG_EXPR_PTR(VPIOB3, VPI18), + SIG_EXPR_PTR(VPIOB3, VPI24), + SIG_EXPR_PTR(VPIOB3, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, W2_DESC); +MS_PIN_DECL(W2, GPIOM1, VPIOB3, NDCD2); +FUNC_GROUP_DECL(NDCD2, W2); + +#define Y1 98 +#define Y1_DESC SIG_DESC_SET(SCU84, 26) +SIG_EXPR_DECL(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); +SIG_EXPR_DECL(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); +SIG_EXPR_DECL(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); +SIG_EXPR_LIST_DECL(VPIOB4, SIG_EXPR_PTR(VPIOB4, VPI18), + SIG_EXPR_PTR(VPIOB4, VPI24), + SIG_EXPR_PTR(VPIOB4, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, Y1_DESC); +MS_PIN_DECL(Y1, GPIOM2, VPIOB4, NDSR2); +FUNC_GROUP_DECL(NDSR2, Y1); + +#define V4 99 +#define V4_DESC SIG_DESC_SET(SCU84, 27) +SIG_EXPR_DECL(VPIOB5, VPI18, VPI18_DESC, V4_DESC); +SIG_EXPR_DECL(VPIOB5, VPI24, VPI24_DESC, V4_DESC); +SIG_EXPR_DECL(VPIOB5, VPI30, VPI30_DESC, V4_DESC); +SIG_EXPR_LIST_DECL(VPIOB5, SIG_EXPR_PTR(VPIOB5, VPI18), + SIG_EXPR_PTR(VPIOB5, VPI24), + SIG_EXPR_PTR(VPIOB5, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, V4_DESC); +MS_PIN_DECL(V4, GPIOM3, VPIOB5, NRI2); +FUNC_GROUP_DECL(NRI2, V4); + +#define W3 100 +#define W3_DESC SIG_DESC_SET(SCU84, 28) +SIG_EXPR_DECL(VPIOB6, VPI18, VPI18_DESC, W3_DESC); +SIG_EXPR_DECL(VPIOB6, VPI24, VPI24_DESC, W3_DESC); +SIG_EXPR_DECL(VPIOB6, VPI30, VPI30_DESC, W3_DESC); +SIG_EXPR_LIST_DECL(VPIOB6, SIG_EXPR_PTR(VPIOB6, VPI18), + SIG_EXPR_PTR(VPIOB6, VPI24), + SIG_EXPR_PTR(VPIOB6, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, W3_DESC); +MS_PIN_DECL(W3, GPIOM4, VPIOB6, NDTR2); +FUNC_GROUP_DECL(NDTR2, W3); + +#define Y2 101 +#define Y2_DESC SIG_DESC_SET(SCU84, 29) +SIG_EXPR_DECL(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); +SIG_EXPR_DECL(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); +SIG_EXPR_DECL(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); +SIG_EXPR_LIST_DECL(VPIOB7, SIG_EXPR_PTR(VPIOB7, VPI18), + SIG_EXPR_PTR(VPIOB7, VPI24), + SIG_EXPR_PTR(VPIOB7, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, Y2_DESC); +MS_PIN_DECL(Y2, GPIOM5, VPIOB7, NRTS2); +FUNC_GROUP_DECL(NRTS2, Y2); + +#define AA1 102 +#define AA1_DESC SIG_DESC_SET(SCU84, 30) +SIG_EXPR_DECL(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); +SIG_EXPR_DECL(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); +SIG_EXPR_DECL(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); +SIG_EXPR_LIST_DECL(VPIOB8, SIG_EXPR_PTR(VPIOB8, VPI18), + SIG_EXPR_PTR(VPIOB8, VPI24), + SIG_EXPR_PTR(VPIOB8, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, AA1_DESC); +MS_PIN_DECL(AA1, GPIOM6, VPIOB8, TXD2); +FUNC_GROUP_DECL(TXD2, AA1); + +#define V5 103 +#define V5_DESC SIG_DESC_SET(SCU84, 31) +SIG_EXPR_DECL(VPIOB9, VPI18, VPI18_DESC, V5_DESC); +SIG_EXPR_DECL(VPIOB9, VPI24, VPI24_DESC, V5_DESC); +SIG_EXPR_DECL(VPIOB9, VPI30, VPI30_DESC, V5_DESC); +SIG_EXPR_LIST_DECL(VPIOB9, SIG_EXPR_PTR(VPIOB9, VPI18), + SIG_EXPR_PTR(VPIOB9, VPI24), + SIG_EXPR_PTR(VPIOB9, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, V5_DESC); +MS_PIN_DECL(V5, GPIOM7, VPIOB9, RXD2); +FUNC_GROUP_DECL(RXD2, V5); + #define W4 104 #define W4_DESC SIG_DESC_SET(SCU88, 0) SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC); @@ -580,10 +908,57 @@ SS_PIN_DECL(V6, GPIOO0, VPIG8); SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); SS_PIN_DECL(Y5, GPIOO1, VPIG9); -FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2); -FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5); -FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3, - AB2); +#define AA4 114 +SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10)); +SS_PIN_DECL(AA4, GPIOO2, VPIR0); + +#define AB3 115 +SIG_EXPR_LIST_DECL_SINGLE(VPIR1, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 11)); +SS_PIN_DECL(AB3, GPIOO3, VPIR1); + +#define W6 116 +SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12)); +SS_PIN_DECL(W6, GPIOO4, VPIR2); + +#define AA5 117 +SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13)); +SS_PIN_DECL(AA5, GPIOO5, VPIR3); + +#define AB4 118 +SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14)); +SS_PIN_DECL(AB4, GPIOO6, VPIR4); + +#define V7 119 +SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15)); +SS_PIN_DECL(V7, GPIOO7, VPIR5); + +#define Y6 120 +SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16)); +SS_PIN_DECL(Y6, GPIOP0, VPIR6); + +#define AB5 121 +SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17)); +SS_PIN_DECL(AB5, GPIOP1, VPIR7); + +#define W7 122 +SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18)); +SS_PIN_DECL(W7, GPIOP2, VPIR8); + +#define AA6 123 +SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19)); +SS_PIN_DECL(AA6, GPIOP3, VPIR9); + +FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, + AA22, W5, Y4, AA3, AB2); +FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, + AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7, + AA6); +FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1, + V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3); + +#define AB6 124 +SIG_EXPR_LIST_DECL_SINGLE(GPIOP4, GPIOP4); +MS_PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(GPIOP4)); #define Y7 125 SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5); @@ -619,6 +994,18 @@ SS_PIN_DECL(F5, GPIOQ3, SDA4); FUNC_GROUP_DECL(I2C4, B1, F5); +#define I2C14_DESC SIG_DESC_SET(SCU90, 27) + +#define H4 132 +SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); +SS_PIN_DECL(H4, GPIOQ4, SCL14); + +#define H3 133 +SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); +SS_PIN_DECL(H3, GPIOQ5, SDA14); + +FUNC_GROUP_DECL(I2C14, H4, H3); + #define DASH9028_DESC SIG_DESC_SET(SCU90, 28) #define H2 134 @@ -641,11 +1028,11 @@ SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26)); #define U19 139 SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); -#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 } -#define VPO12_DESC { SCU94, GENMASK(1, 0), 1, 0 } -#define VPO24_DESC { SCU94, GENMASK(1, 0), 2, 0 } -#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 3, 0 } -#define VPO_OFF_12 { SCU94, 0x2, 0, 0 } +#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } +#define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } +#define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } +#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } +#define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 } #define VPO_24_OFF SIG_DESC_SET(SCU94, 1) #define V21 140 @@ -776,13 +1163,6 @@ SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8), SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF); MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5); -FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, - U19); -FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18, - A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19); -FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20); -FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22); - #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) #define A12 152 @@ -827,6 +1207,50 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13), SIG_EXPR_LIST_PTR(RGMII1TXD3)); +#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) + +#define D9 158 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); +MS_PIN_DECL_(D9, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2TXEN), + SIG_EXPR_LIST_PTR(RGMII2TXCK)); + +#define E9 159 +SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); +SIG_EXPR_LIST_DECL_SINGLE(DASHE9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); +MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(DASHE9), + SIG_EXPR_LIST_PTR(RGMII2TXCTL)); + +#define A10 160 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); +MS_PIN_DECL_(A10, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), + SIG_EXPR_LIST_PTR(RGMII2TXD0)); + +#define B10 161 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); +MS_PIN_DECL_(B10, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), + SIG_EXPR_LIST_PTR(RGMII2TXD1)); + +#define C10 162 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); +SIG_EXPR_LIST_DECL_SINGLE(DASHC10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); +MS_PIN_DECL_(C10, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(DASHC10), + SIG_EXPR_LIST_PTR(RGMII2TXD2)); + +#define D10 163 +SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); +SIG_EXPR_LIST_DECL_SINGLE(DASHD10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); +MS_PIN_DECL_(D10, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(DASHD10), + SIG_EXPR_LIST_PTR(RGMII2TXD3)); + #define E11 164 SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC); @@ -869,11 +1293,419 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), SIG_EXPR_LIST_PTR(RGMII1RXD3)); +#define C9 170 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLK, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); +MS_PIN_DECL_(C9, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLK), + SIG_EXPR_LIST_PTR(RGMII2RXCK)); + +#define B9 171 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); +SIG_EXPR_LIST_DECL_SINGLE(DASHB9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); +MS_PIN_DECL_(B9, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(DASHB9), + SIG_EXPR_LIST_PTR(RGMII2RXCTL)); + +#define A9 172 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); +MS_PIN_DECL_(A9, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), + SIG_EXPR_LIST_PTR(RGMII2RXD0)); + +#define E8 173 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); +MS_PIN_DECL_(E8, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), + SIG_EXPR_LIST_PTR(RGMII2RXD1)); + +#define D8 174 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); +MS_PIN_DECL_(D8, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), + SIG_EXPR_LIST_PTR(RGMII2RXD2)); + +#define C8 175 +SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); +SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); +MS_PIN_DECL_(C8, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), + SIG_EXPR_LIST_PTR(RGMII2RXD3)); + FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, E10); FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, E10); +FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); +FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); + +#define L5 176 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); +MS_PIN_DECL_(L5, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +FUNC_GROUP_DECL(ADC0, L5); + +#define L4 177 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); +MS_PIN_DECL_(L4, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +FUNC_GROUP_DECL(ADC1, L4); + +#define L3 178 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); +MS_PIN_DECL_(L3, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +FUNC_GROUP_DECL(ADC2, L3); + +#define L2 179 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); +MS_PIN_DECL_(L2, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +FUNC_GROUP_DECL(ADC3, L2); + +#define L1 180 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); +MS_PIN_DECL_(L1, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +FUNC_GROUP_DECL(ADC4, L1); + +#define M5 181 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); +MS_PIN_DECL_(M5, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +FUNC_GROUP_DECL(ADC5, M5); + +#define M4 182 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); +MS_PIN_DECL_(M4, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +FUNC_GROUP_DECL(ADC6, M4); + +#define M3 183 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); +MS_PIN_DECL_(M3, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +FUNC_GROUP_DECL(ADC7, M3); + +#define M2 184 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); +MS_PIN_DECL_(M2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +FUNC_GROUP_DECL(ADC8, M2); + +#define M1 185 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); +MS_PIN_DECL_(M1, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +FUNC_GROUP_DECL(ADC9, M1); + +#define N5 186 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); +MS_PIN_DECL_(N5, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +FUNC_GROUP_DECL(ADC10, N5); + +#define N4 187 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); +MS_PIN_DECL_(N4, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +FUNC_GROUP_DECL(ADC11, N4); + +#define N3 188 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); +MS_PIN_DECL_(N3, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +FUNC_GROUP_DECL(ADC12, N3); + +#define N2 189 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); +MS_PIN_DECL_(N2, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +FUNC_GROUP_DECL(ADC13, N2); + +#define N1 190 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); +MS_PIN_DECL_(N1, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +FUNC_GROUP_DECL(ADC14, N1); + +#define P5 191 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); +MS_PIN_DECL_(P5, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +FUNC_GROUP_DECL(ADC15, P5); + +#define C21 192 +SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); +SS_PIN_DECL(C21, GPIOY0, SIOS3); +FUNC_GROUP_DECL(SIOS3, C21); + +#define F20 193 +SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); +SS_PIN_DECL(F20, GPIOY1, SIOS5); +FUNC_GROUP_DECL(SIOS5, F20); + +#define G20 194 +SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); +SS_PIN_DECL(G20, GPIOY2, SIOPWREQ); +FUNC_GROUP_DECL(SIOPWREQ, G20); + +#define K20 195 +SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); +SS_PIN_DECL(K20, GPIOY3, SIOONCTRL); +FUNC_GROUP_DECL(SIOONCTRL, K20); + +FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20); + +#define R22 200 +#define R22_DESC SIG_DESC_SET(SCUA4, 16) +SIG_EXPR_DECL(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA2, ROM8, ROM16); +SIG_EXPR_DECL(VPOB0, VPO12, R22_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB0, VPO24, R22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB0, SIG_EXPR_PTR(VPOB0, VPO12), + SIG_EXPR_PTR(VPOB0, VPO24), SIG_EXPR_PTR(VPOB0, VPOOFF1)); +MS_PIN_DECL(R22, GPIOZ0, ROMA2, VPOB0); + +#define P18 201 +#define P18_DESC SIG_DESC_SET(SCUA4, 17) +SIG_EXPR_DECL(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA3, ROM8, ROM16); +SIG_EXPR_DECL(VPOB1, VPO12, P18_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB1, VPO24, P18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB1, SIG_EXPR_PTR(VPOB1, VPO12), + SIG_EXPR_PTR(VPOB1, VPO24), SIG_EXPR_PTR(VPOB1, VPOOFF1)); +MS_PIN_DECL(P18, GPIOZ1, ROMA3, VPOB1); + +#define P19 202 +#define P19_DESC SIG_DESC_SET(SCUA4, 18) +SIG_EXPR_DECL(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA4, ROM8, ROM16); +SIG_EXPR_DECL(VPOB2, VPO12, P19_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB2, VPO24, P19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO12), + SIG_EXPR_PTR(VPOB2, VPO24), SIG_EXPR_PTR(VPOB2, VPOOFF1)); +MS_PIN_DECL(P19, GPIOZ2, ROMA4, VPOB2); + +#define P20 203 +#define P20_DESC SIG_DESC_SET(SCUA4, 19) +SIG_EXPR_DECL(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA5, ROM8, ROM16); +SIG_EXPR_DECL(VPOB3, VPO12, P20_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB3, VPO24, P20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO12), + SIG_EXPR_PTR(VPOB3, VPO24), SIG_EXPR_PTR(VPOB3, VPOOFF1)); +MS_PIN_DECL(P20, GPIOZ3, ROMA5, VPOB3); + +#define P21 204 +#define P21_DESC SIG_DESC_SET(SCUA4, 20) +SIG_EXPR_DECL(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA6, ROM8, ROM16); +SIG_EXPR_DECL(VPOB4, VPO12, P21_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB4, VPO24, P21_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO12), + SIG_EXPR_PTR(VPOB4, VPO24), SIG_EXPR_PTR(VPOB4, VPOOFF1)); +MS_PIN_DECL(P21, GPIOZ4, ROMA6, VPOB4); + +#define P22 205 +#define P22_DESC SIG_DESC_SET(SCUA4, 21) +SIG_EXPR_DECL(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA7, ROM8, ROM16); +SIG_EXPR_DECL(VPOB5, VPO12, P22_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB5, VPO24, P22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO12), + SIG_EXPR_PTR(VPOB5, VPO24), SIG_EXPR_PTR(VPOB5, VPOOFF1)); +MS_PIN_DECL(P22, GPIOZ5, ROMA7, VPOB5); + +#define M19 206 +#define M19_DESC SIG_DESC_SET(SCUA4, 22) +SIG_EXPR_DECL(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA8, ROM8, ROM16); +SIG_EXPR_DECL(VPOB6, VPO12, M19_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB6, VPO24, M19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO12), + SIG_EXPR_PTR(VPOB6, VPO24), SIG_EXPR_PTR(VPOB6, VPOOFF1)); +MS_PIN_DECL(M19, GPIOZ6, ROMA8, VPOB6); + +#define M20 207 +#define M20_DESC SIG_DESC_SET(SCUA4, 23) +SIG_EXPR_DECL(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA9, ROM8, ROM16); +SIG_EXPR_DECL(VPOB7, VPO12, M20_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOB7, VPO24, M20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO12), + SIG_EXPR_PTR(VPOB7, VPO24), SIG_EXPR_PTR(VPOB7, VPOOFF1)); +MS_PIN_DECL(M20, GPIOZ7, ROMA9, VPOB7); + +#define M21 208 +#define M21_DESC SIG_DESC_SET(SCUA4, 24) +SIG_EXPR_DECL(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA10, ROM8, ROM16); +SIG_EXPR_DECL(VPOG0, VPO12, M21_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG0, VPO24, M21_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG0, SIG_EXPR_PTR(VPOG0, VPO12), + SIG_EXPR_PTR(VPOG0, VPO24), SIG_EXPR_PTR(VPOG0, VPOOFF1)); +MS_PIN_DECL(M21, GPIOAA0, ROMA10, VPOG0); + +#define M22 209 +#define M22_DESC SIG_DESC_SET(SCUA4, 25) +SIG_EXPR_DECL(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA11, ROM8, ROM16); +SIG_EXPR_DECL(VPOG1, VPO12, M22_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG1, VPO24, M22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG1, SIG_EXPR_PTR(VPOG1, VPO12), + SIG_EXPR_PTR(VPOG1, VPO24), SIG_EXPR_PTR(VPOG1, VPOOFF1)); +MS_PIN_DECL(M22, GPIOAA1, ROMA11, VPOG1); + +#define L18 210 +#define L18_DESC SIG_DESC_SET(SCUA4, 26) +SIG_EXPR_DECL(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA12, ROM8, ROM16); +SIG_EXPR_DECL(VPOG2, VPO12, L18_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG2, VPO24, L18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO12), + SIG_EXPR_PTR(VPOG2, VPO24), SIG_EXPR_PTR(VPOG2, VPOOFF1)); +MS_PIN_DECL(L18, GPIOAA2, ROMA12, VPOG2); + +#define L19 211 +#define L19_DESC SIG_DESC_SET(SCUA4, 27) +SIG_EXPR_DECL(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(ROMA13, ROM8, ROM16); +SIG_EXPR_DECL(VPOG3, VPO12, L19_DESC, VPO12_DESC); +SIG_EXPR_DECL(VPOG3, VPO24, L19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO12), + SIG_EXPR_PTR(VPOG3, VPO24), SIG_EXPR_PTR(VPOG3, VPOOFF1)); +MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3); + +#define L20 212 +#define L20_DESC SIG_DESC_SET(SCUA4, 28) +SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16); +SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG4, VPO24, VPOOFF1); +MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4); + +#define L21 213 +#define L21_DESC SIG_DESC_SET(SCUA4, 29) +SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16); +SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG5, VPO24, VPOOFF1); +MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5); + +#define T18 214 +#define T18_DESC SIG_DESC_SET(SCUA4, 30) +SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16); +SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG6, VPO24, VPOOFF1); +MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6); + +#define N18 215 +#define N18_DESC SIG_DESC_SET(SCUA4, 31) +SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16); +SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOG7, VPO24, VPOOFF1); +MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7); + +#define N19 216 +#define N19_DESC SIG_DESC_SET(SCUA8, 0) +SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16); +SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR0, VPO24, VPOOFF1); +MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0); + +#define M18 217 +#define M18_DESC SIG_DESC_SET(SCUA8, 1) +SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16); +SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR1, VPO24, VPOOFF1); +MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1); + +#define N22 218 +#define N22_DESC SIG_DESC_SET(SCUA8, 2) +SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16); +SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR2, VPO24, VPOOFF1); +MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2); + +#define N20 219 +#define N20_DESC SIG_DESC_SET(SCUA8, 3) +SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16); +SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC); +SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(VPOR3, VPO24, VPOOFF1); +MS_PIN_DECL(N20, GPIOAB3, ROMA21, VPOR3); + +FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, + U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, + L19, L20, L21, T18, N18, N19, M18, N22, N20); +FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18, + A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19, + P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18, + N18, N19, M18, N22, N20); +FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19, + M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22, + N20); +FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, + P20, P21, P22, M19, M20, M21, M22, L18, L19); + /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216 * pins becomes 220. */ @@ -883,84 +1715,180 @@ FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(A1), + ASPEED_PINCTRL_PIN(A10), ASPEED_PINCTRL_PIN(A11), ASPEED_PINCTRL_PIN(A12), ASPEED_PINCTRL_PIN(A13), + ASPEED_PINCTRL_PIN(A14), ASPEED_PINCTRL_PIN(A15), + ASPEED_PINCTRL_PIN(A16), + ASPEED_PINCTRL_PIN(A17), ASPEED_PINCTRL_PIN(A18), + ASPEED_PINCTRL_PIN(A19), ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A20), ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A4), ASPEED_PINCTRL_PIN(A5), ASPEED_PINCTRL_PIN(A6), ASPEED_PINCTRL_PIN(A7), ASPEED_PINCTRL_PIN(A8), + ASPEED_PINCTRL_PIN(A9), + ASPEED_PINCTRL_PIN(AA1), ASPEED_PINCTRL_PIN(AA2), ASPEED_PINCTRL_PIN(AA22), ASPEED_PINCTRL_PIN(AA3), + ASPEED_PINCTRL_PIN(AA4), + ASPEED_PINCTRL_PIN(AA5), + ASPEED_PINCTRL_PIN(AA6), ASPEED_PINCTRL_PIN(AA7), ASPEED_PINCTRL_PIN(AB1), ASPEED_PINCTRL_PIN(AB2), + ASPEED_PINCTRL_PIN(AB3), + ASPEED_PINCTRL_PIN(AB4), + ASPEED_PINCTRL_PIN(AB5), + ASPEED_PINCTRL_PIN(AB6), ASPEED_PINCTRL_PIN(AB7), ASPEED_PINCTRL_PIN(B1), + ASPEED_PINCTRL_PIN(B10), ASPEED_PINCTRL_PIN(B11), ASPEED_PINCTRL_PIN(B12), + ASPEED_PINCTRL_PIN(B13), ASPEED_PINCTRL_PIN(B14), ASPEED_PINCTRL_PIN(B15), + ASPEED_PINCTRL_PIN(B16), + ASPEED_PINCTRL_PIN(B17), + ASPEED_PINCTRL_PIN(B18), ASPEED_PINCTRL_PIN(B19), ASPEED_PINCTRL_PIN(B2), + ASPEED_PINCTRL_PIN(B22), ASPEED_PINCTRL_PIN(B3), ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(B5), ASPEED_PINCTRL_PIN(B6), ASPEED_PINCTRL_PIN(B7), + ASPEED_PINCTRL_PIN(B9), ASPEED_PINCTRL_PIN(C1), + ASPEED_PINCTRL_PIN(C10), ASPEED_PINCTRL_PIN(C11), ASPEED_PINCTRL_PIN(C12), + ASPEED_PINCTRL_PIN(C13), ASPEED_PINCTRL_PIN(C14), ASPEED_PINCTRL_PIN(C15), + ASPEED_PINCTRL_PIN(C16), ASPEED_PINCTRL_PIN(C17), + ASPEED_PINCTRL_PIN(C18), ASPEED_PINCTRL_PIN(C2), + ASPEED_PINCTRL_PIN(C20), + ASPEED_PINCTRL_PIN(C21), + ASPEED_PINCTRL_PIN(C22), ASPEED_PINCTRL_PIN(C3), ASPEED_PINCTRL_PIN(C4), ASPEED_PINCTRL_PIN(C5), ASPEED_PINCTRL_PIN(C6), ASPEED_PINCTRL_PIN(C7), + ASPEED_PINCTRL_PIN(C8), + ASPEED_PINCTRL_PIN(C9), ASPEED_PINCTRL_PIN(D1), + ASPEED_PINCTRL_PIN(D10), ASPEED_PINCTRL_PIN(D11), ASPEED_PINCTRL_PIN(D12), + ASPEED_PINCTRL_PIN(D13), ASPEED_PINCTRL_PIN(D14), ASPEED_PINCTRL_PIN(D15), ASPEED_PINCTRL_PIN(D16), ASPEED_PINCTRL_PIN(D17), ASPEED_PINCTRL_PIN(D18), + ASPEED_PINCTRL_PIN(D19), ASPEED_PINCTRL_PIN(D2), ASPEED_PINCTRL_PIN(D3), ASPEED_PINCTRL_PIN(D4), ASPEED_PINCTRL_PIN(D5), + ASPEED_PINCTRL_PIN(D6), ASPEED_PINCTRL_PIN(D7), + ASPEED_PINCTRL_PIN(D8), + ASPEED_PINCTRL_PIN(D9), ASPEED_PINCTRL_PIN(E10), ASPEED_PINCTRL_PIN(E11), ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(E13), ASPEED_PINCTRL_PIN(E14), + ASPEED_PINCTRL_PIN(E15), ASPEED_PINCTRL_PIN(E16), + ASPEED_PINCTRL_PIN(E18), + ASPEED_PINCTRL_PIN(E19), ASPEED_PINCTRL_PIN(E2), + ASPEED_PINCTRL_PIN(E20), ASPEED_PINCTRL_PIN(E3), ASPEED_PINCTRL_PIN(E5), + ASPEED_PINCTRL_PIN(E6), ASPEED_PINCTRL_PIN(E7), + ASPEED_PINCTRL_PIN(E8), + ASPEED_PINCTRL_PIN(E9), + ASPEED_PINCTRL_PIN(F18), + ASPEED_PINCTRL_PIN(F20), ASPEED_PINCTRL_PIN(F3), ASPEED_PINCTRL_PIN(F4), ASPEED_PINCTRL_PIN(F5), + ASPEED_PINCTRL_PIN(G18), + ASPEED_PINCTRL_PIN(G19), + ASPEED_PINCTRL_PIN(G20), ASPEED_PINCTRL_PIN(G5), ASPEED_PINCTRL_PIN(H1), + ASPEED_PINCTRL_PIN(H18), ASPEED_PINCTRL_PIN(H19), ASPEED_PINCTRL_PIN(H2), ASPEED_PINCTRL_PIN(H20), + ASPEED_PINCTRL_PIN(H3), + ASPEED_PINCTRL_PIN(H4), + ASPEED_PINCTRL_PIN(J20), + ASPEED_PINCTRL_PIN(J21), ASPEED_PINCTRL_PIN(J3), + ASPEED_PINCTRL_PIN(J4), + ASPEED_PINCTRL_PIN(J5), ASPEED_PINCTRL_PIN(K18), + ASPEED_PINCTRL_PIN(K20), + ASPEED_PINCTRL_PIN(K5), + ASPEED_PINCTRL_PIN(L1), + ASPEED_PINCTRL_PIN(L18), + ASPEED_PINCTRL_PIN(L19), + ASPEED_PINCTRL_PIN(L2), + ASPEED_PINCTRL_PIN(L20), + ASPEED_PINCTRL_PIN(L21), ASPEED_PINCTRL_PIN(L22), + ASPEED_PINCTRL_PIN(L3), + ASPEED_PINCTRL_PIN(L4), + ASPEED_PINCTRL_PIN(L5), + ASPEED_PINCTRL_PIN(M1), + ASPEED_PINCTRL_PIN(M18), + ASPEED_PINCTRL_PIN(M19), + ASPEED_PINCTRL_PIN(M2), + ASPEED_PINCTRL_PIN(M20), + ASPEED_PINCTRL_PIN(M21), + ASPEED_PINCTRL_PIN(M22), + ASPEED_PINCTRL_PIN(M3), + ASPEED_PINCTRL_PIN(M4), + ASPEED_PINCTRL_PIN(M5), + ASPEED_PINCTRL_PIN(N1), + ASPEED_PINCTRL_PIN(N18), + ASPEED_PINCTRL_PIN(N19), + ASPEED_PINCTRL_PIN(N2), + ASPEED_PINCTRL_PIN(N20), ASPEED_PINCTRL_PIN(N21), + ASPEED_PINCTRL_PIN(N22), + ASPEED_PINCTRL_PIN(N3), + ASPEED_PINCTRL_PIN(N4), + ASPEED_PINCTRL_PIN(N5), + ASPEED_PINCTRL_PIN(P18), + ASPEED_PINCTRL_PIN(P19), + ASPEED_PINCTRL_PIN(P20), + ASPEED_PINCTRL_PIN(P21), + ASPEED_PINCTRL_PIN(P22), + ASPEED_PINCTRL_PIN(P5), ASPEED_PINCTRL_PIN(R18), + ASPEED_PINCTRL_PIN(R22), ASPEED_PINCTRL_PIN(T1), + ASPEED_PINCTRL_PIN(T18), ASPEED_PINCTRL_PIN(T19), ASPEED_PINCTRL_PIN(T2), ASPEED_PINCTRL_PIN(T4), @@ -979,28 +1907,61 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(V20), ASPEED_PINCTRL_PIN(V21), ASPEED_PINCTRL_PIN(V22), + ASPEED_PINCTRL_PIN(V3), + ASPEED_PINCTRL_PIN(V4), + ASPEED_PINCTRL_PIN(V5), ASPEED_PINCTRL_PIN(V6), + ASPEED_PINCTRL_PIN(V7), ASPEED_PINCTRL_PIN(W1), + ASPEED_PINCTRL_PIN(W2), ASPEED_PINCTRL_PIN(W21), ASPEED_PINCTRL_PIN(W22), + ASPEED_PINCTRL_PIN(W3), ASPEED_PINCTRL_PIN(W4), ASPEED_PINCTRL_PIN(W5), + ASPEED_PINCTRL_PIN(W6), + ASPEED_PINCTRL_PIN(W7), + ASPEED_PINCTRL_PIN(Y1), + ASPEED_PINCTRL_PIN(Y2), + ASPEED_PINCTRL_PIN(Y21), ASPEED_PINCTRL_PIN(Y22), ASPEED_PINCTRL_PIN(Y3), ASPEED_PINCTRL_PIN(Y4), ASPEED_PINCTRL_PIN(Y5), + ASPEED_PINCTRL_PIN(Y6), ASPEED_PINCTRL_PIN(Y7), }; static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(ACPI), + ASPEED_PINCTRL_GROUP(ADC0), + ASPEED_PINCTRL_GROUP(ADC1), + ASPEED_PINCTRL_GROUP(ADC10), + ASPEED_PINCTRL_GROUP(ADC11), + ASPEED_PINCTRL_GROUP(ADC12), + ASPEED_PINCTRL_GROUP(ADC13), + ASPEED_PINCTRL_GROUP(ADC14), + ASPEED_PINCTRL_GROUP(ADC15), + ASPEED_PINCTRL_GROUP(ADC2), + ASPEED_PINCTRL_GROUP(ADC3), + ASPEED_PINCTRL_GROUP(ADC4), + ASPEED_PINCTRL_GROUP(ADC5), + ASPEED_PINCTRL_GROUP(ADC6), + ASPEED_PINCTRL_GROUP(ADC7), + ASPEED_PINCTRL_GROUP(ADC8), + ASPEED_PINCTRL_GROUP(ADC9), ASPEED_PINCTRL_GROUP(BMCINT), ASPEED_PINCTRL_GROUP(DDCCLK), ASPEED_PINCTRL_GROUP(DDCDAT), + ASPEED_PINCTRL_GROUP(EXTRST), ASPEED_PINCTRL_GROUP(FLACK), ASPEED_PINCTRL_GROUP(FLBUSY), ASPEED_PINCTRL_GROUP(FLWP), + ASPEED_PINCTRL_GROUP(GPID), ASPEED_PINCTRL_GROUP(GPID0), + ASPEED_PINCTRL_GROUP(GPID2), + ASPEED_PINCTRL_GROUP(GPID4), + ASPEED_PINCTRL_GROUP(GPID6), ASPEED_PINCTRL_GROUP(GPIE0), ASPEED_PINCTRL_GROUP(GPIE2), ASPEED_PINCTRL_GROUP(GPIE4), @@ -1009,6 +1970,7 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(I2C11), ASPEED_PINCTRL_GROUP(I2C12), ASPEED_PINCTRL_GROUP(I2C13), + ASPEED_PINCTRL_GROUP(I2C14), ASPEED_PINCTRL_GROUP(I2C3), ASPEED_PINCTRL_GROUP(I2C4), ASPEED_PINCTRL_GROUP(I2C5), @@ -1018,25 +1980,37 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(I2C9), ASPEED_PINCTRL_GROUP(LPCPD), ASPEED_PINCTRL_GROUP(LPCPME), - ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCRST), ASPEED_PINCTRL_GROUP(LPCSMI), + ASPEED_PINCTRL_GROUP(MAC1LINK), + ASPEED_PINCTRL_GROUP(MAC2LINK), ASPEED_PINCTRL_GROUP(MDIO1), ASPEED_PINCTRL_GROUP(MDIO2), ASPEED_PINCTRL_GROUP(NCTS1), + ASPEED_PINCTRL_GROUP(NCTS2), ASPEED_PINCTRL_GROUP(NCTS3), ASPEED_PINCTRL_GROUP(NCTS4), ASPEED_PINCTRL_GROUP(NDCD1), + ASPEED_PINCTRL_GROUP(NDCD2), ASPEED_PINCTRL_GROUP(NDCD3), ASPEED_PINCTRL_GROUP(NDCD4), ASPEED_PINCTRL_GROUP(NDSR1), + ASPEED_PINCTRL_GROUP(NDSR2), ASPEED_PINCTRL_GROUP(NDSR3), + ASPEED_PINCTRL_GROUP(NDSR4), ASPEED_PINCTRL_GROUP(NDTR1), + ASPEED_PINCTRL_GROUP(NDTR2), ASPEED_PINCTRL_GROUP(NDTR3), + ASPEED_PINCTRL_GROUP(NDTR4), + ASPEED_PINCTRL_GROUP(NDTS4), ASPEED_PINCTRL_GROUP(NRI1), + ASPEED_PINCTRL_GROUP(NRI2), ASPEED_PINCTRL_GROUP(NRI3), ASPEED_PINCTRL_GROUP(NRI4), ASPEED_PINCTRL_GROUP(NRTS1), + ASPEED_PINCTRL_GROUP(NRTS2), ASPEED_PINCTRL_GROUP(NRTS3), + ASPEED_PINCTRL_GROUP(OSCCLK), ASPEED_PINCTRL_GROUP(PWM0), ASPEED_PINCTRL_GROUP(PWM1), ASPEED_PINCTRL_GROUP(PWM2), @@ -1046,7 +2020,9 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(PWM6), ASPEED_PINCTRL_GROUP(PWM7), ASPEED_PINCTRL_GROUP(RGMII1), + ASPEED_PINCTRL_GROUP(RGMII2), ASPEED_PINCTRL_GROUP(RMII1), + ASPEED_PINCTRL_GROUP(RMII2), ASPEED_PINCTRL_GROUP(ROM16), ASPEED_PINCTRL_GROUP(ROM8), ASPEED_PINCTRL_GROUP(ROMCS1), @@ -1054,21 +2030,48 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(ROMCS3), ASPEED_PINCTRL_GROUP(ROMCS4), ASPEED_PINCTRL_GROUP(RXD1), + ASPEED_PINCTRL_GROUP(RXD2), ASPEED_PINCTRL_GROUP(RXD3), ASPEED_PINCTRL_GROUP(RXD4), + ASPEED_PINCTRL_GROUP(SALT1), + ASPEED_PINCTRL_GROUP(SALT2), + ASPEED_PINCTRL_GROUP(SALT3), + ASPEED_PINCTRL_GROUP(SALT4), ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SD2), + ASPEED_PINCTRL_GROUP(SGPMCK), ASPEED_PINCTRL_GROUP(SGPMI), + ASPEED_PINCTRL_GROUP(SGPMLD), + ASPEED_PINCTRL_GROUP(SGPMO), + ASPEED_PINCTRL_GROUP(SGPSCK), + ASPEED_PINCTRL_GROUP(SGPSI0), + ASPEED_PINCTRL_GROUP(SGPSI1), + ASPEED_PINCTRL_GROUP(SGPSLD), + ASPEED_PINCTRL_GROUP(SIOONCTRL), ASPEED_PINCTRL_GROUP(SIOPBI), ASPEED_PINCTRL_GROUP(SIOPBO), + ASPEED_PINCTRL_GROUP(SIOPWREQ), + ASPEED_PINCTRL_GROUP(SIOPWRGD), + ASPEED_PINCTRL_GROUP(SIOS3), + ASPEED_PINCTRL_GROUP(SIOS5), + ASPEED_PINCTRL_GROUP(SIOSCI), + ASPEED_PINCTRL_GROUP(SPI1), + ASPEED_PINCTRL_GROUP(SPI1DEBUG), + ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), + ASPEED_PINCTRL_GROUP(SPICS1), ASPEED_PINCTRL_GROUP(TIMER3), + ASPEED_PINCTRL_GROUP(TIMER4), ASPEED_PINCTRL_GROUP(TIMER5), ASPEED_PINCTRL_GROUP(TIMER6), ASPEED_PINCTRL_GROUP(TIMER7), ASPEED_PINCTRL_GROUP(TIMER8), ASPEED_PINCTRL_GROUP(TXD1), + ASPEED_PINCTRL_GROUP(TXD2), ASPEED_PINCTRL_GROUP(TXD3), ASPEED_PINCTRL_GROUP(TXD4), ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USBCKI), + ASPEED_PINCTRL_GROUP(VGABIOS_ROM), ASPEED_PINCTRL_GROUP(VGAHS), ASPEED_PINCTRL_GROUP(VGAVS), ASPEED_PINCTRL_GROUP(VPI18), @@ -1076,17 +2079,40 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(VPI30), ASPEED_PINCTRL_GROUP(VPO12), ASPEED_PINCTRL_GROUP(VPO24), + ASPEED_PINCTRL_GROUP(WDTRST1), + ASPEED_PINCTRL_GROUP(WDTRST2), }; static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(ACPI), + ASPEED_PINCTRL_FUNC(ADC0), + ASPEED_PINCTRL_FUNC(ADC1), + ASPEED_PINCTRL_FUNC(ADC10), + ASPEED_PINCTRL_FUNC(ADC11), + ASPEED_PINCTRL_FUNC(ADC12), + ASPEED_PINCTRL_FUNC(ADC13), + ASPEED_PINCTRL_FUNC(ADC14), + ASPEED_PINCTRL_FUNC(ADC15), + ASPEED_PINCTRL_FUNC(ADC2), + ASPEED_PINCTRL_FUNC(ADC3), + ASPEED_PINCTRL_FUNC(ADC4), + ASPEED_PINCTRL_FUNC(ADC5), + ASPEED_PINCTRL_FUNC(ADC6), + ASPEED_PINCTRL_FUNC(ADC7), + ASPEED_PINCTRL_FUNC(ADC8), + ASPEED_PINCTRL_FUNC(ADC9), ASPEED_PINCTRL_FUNC(BMCINT), ASPEED_PINCTRL_FUNC(DDCCLK), ASPEED_PINCTRL_FUNC(DDCDAT), + ASPEED_PINCTRL_FUNC(EXTRST), ASPEED_PINCTRL_FUNC(FLACK), ASPEED_PINCTRL_FUNC(FLBUSY), ASPEED_PINCTRL_FUNC(FLWP), + ASPEED_PINCTRL_FUNC(GPID), ASPEED_PINCTRL_FUNC(GPID0), + ASPEED_PINCTRL_FUNC(GPID2), + ASPEED_PINCTRL_FUNC(GPID4), + ASPEED_PINCTRL_FUNC(GPID6), ASPEED_PINCTRL_FUNC(GPIE0), ASPEED_PINCTRL_FUNC(GPIE2), ASPEED_PINCTRL_FUNC(GPIE4), @@ -1095,6 +2121,7 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(I2C11), ASPEED_PINCTRL_FUNC(I2C12), ASPEED_PINCTRL_FUNC(I2C13), + ASPEED_PINCTRL_FUNC(I2C14), ASPEED_PINCTRL_FUNC(I2C3), ASPEED_PINCTRL_FUNC(I2C4), ASPEED_PINCTRL_FUNC(I2C5), @@ -1104,24 +2131,37 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(I2C9), ASPEED_PINCTRL_FUNC(LPCPD), ASPEED_PINCTRL_FUNC(LPCPME), + ASPEED_PINCTRL_FUNC(LPCRST), ASPEED_PINCTRL_FUNC(LPCSMI), + ASPEED_PINCTRL_FUNC(MAC1LINK), + ASPEED_PINCTRL_FUNC(MAC2LINK), ASPEED_PINCTRL_FUNC(MDIO1), ASPEED_PINCTRL_FUNC(MDIO2), ASPEED_PINCTRL_FUNC(NCTS1), + ASPEED_PINCTRL_FUNC(NCTS2), ASPEED_PINCTRL_FUNC(NCTS3), ASPEED_PINCTRL_FUNC(NCTS4), ASPEED_PINCTRL_FUNC(NDCD1), + ASPEED_PINCTRL_FUNC(NDCD2), ASPEED_PINCTRL_FUNC(NDCD3), ASPEED_PINCTRL_FUNC(NDCD4), ASPEED_PINCTRL_FUNC(NDSR1), + ASPEED_PINCTRL_FUNC(NDSR2), ASPEED_PINCTRL_FUNC(NDSR3), + ASPEED_PINCTRL_FUNC(NDSR4), ASPEED_PINCTRL_FUNC(NDTR1), + ASPEED_PINCTRL_FUNC(NDTR2), ASPEED_PINCTRL_FUNC(NDTR3), + ASPEED_PINCTRL_FUNC(NDTR4), + ASPEED_PINCTRL_FUNC(NDTS4), ASPEED_PINCTRL_FUNC(NRI1), + ASPEED_PINCTRL_FUNC(NRI2), ASPEED_PINCTRL_FUNC(NRI3), ASPEED_PINCTRL_FUNC(NRI4), ASPEED_PINCTRL_FUNC(NRTS1), + ASPEED_PINCTRL_FUNC(NRTS2), ASPEED_PINCTRL_FUNC(NRTS3), + ASPEED_PINCTRL_FUNC(OSCCLK), ASPEED_PINCTRL_FUNC(PWM0), ASPEED_PINCTRL_FUNC(PWM1), ASPEED_PINCTRL_FUNC(PWM2), @@ -1131,7 +2171,9 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(PWM6), ASPEED_PINCTRL_FUNC(PWM7), ASPEED_PINCTRL_FUNC(RGMII1), + ASPEED_PINCTRL_FUNC(RGMII2), ASPEED_PINCTRL_FUNC(RMII1), + ASPEED_PINCTRL_FUNC(RMII2), ASPEED_PINCTRL_FUNC(ROM16), ASPEED_PINCTRL_FUNC(ROM8), ASPEED_PINCTRL_FUNC(ROMCS1), @@ -1139,21 +2181,48 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(ROMCS3), ASPEED_PINCTRL_FUNC(ROMCS4), ASPEED_PINCTRL_FUNC(RXD1), + ASPEED_PINCTRL_FUNC(RXD2), ASPEED_PINCTRL_FUNC(RXD3), ASPEED_PINCTRL_FUNC(RXD4), + ASPEED_PINCTRL_FUNC(SALT1), + ASPEED_PINCTRL_FUNC(SALT2), + ASPEED_PINCTRL_FUNC(SALT3), + ASPEED_PINCTRL_FUNC(SALT4), ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SD2), + ASPEED_PINCTRL_FUNC(SGPMCK), ASPEED_PINCTRL_FUNC(SGPMI), + ASPEED_PINCTRL_FUNC(SGPMLD), + ASPEED_PINCTRL_FUNC(SGPMO), + ASPEED_PINCTRL_FUNC(SGPSCK), + ASPEED_PINCTRL_FUNC(SGPSI0), + ASPEED_PINCTRL_FUNC(SGPSI1), + ASPEED_PINCTRL_FUNC(SGPSLD), + ASPEED_PINCTRL_FUNC(SIOONCTRL), ASPEED_PINCTRL_FUNC(SIOPBI), ASPEED_PINCTRL_FUNC(SIOPBO), + ASPEED_PINCTRL_FUNC(SIOPWREQ), + ASPEED_PINCTRL_FUNC(SIOPWRGD), + ASPEED_PINCTRL_FUNC(SIOS3), + ASPEED_PINCTRL_FUNC(SIOS5), + ASPEED_PINCTRL_FUNC(SIOSCI), + ASPEED_PINCTRL_FUNC(SPI1), + ASPEED_PINCTRL_FUNC(SPI1DEBUG), + ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), + ASPEED_PINCTRL_FUNC(SPICS1), ASPEED_PINCTRL_FUNC(TIMER3), + ASPEED_PINCTRL_FUNC(TIMER4), ASPEED_PINCTRL_FUNC(TIMER5), ASPEED_PINCTRL_FUNC(TIMER6), ASPEED_PINCTRL_FUNC(TIMER7), ASPEED_PINCTRL_FUNC(TIMER8), ASPEED_PINCTRL_FUNC(TXD1), + ASPEED_PINCTRL_FUNC(TXD2), ASPEED_PINCTRL_FUNC(TXD3), ASPEED_PINCTRL_FUNC(TXD4), ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USBCKI), + ASPEED_PINCTRL_FUNC(VGABIOS_ROM), ASPEED_PINCTRL_FUNC(VGAHS), ASPEED_PINCTRL_FUNC(VGAVS), ASPEED_PINCTRL_FUNC(VPI18), @@ -1161,6 +2230,8 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(VPI30), ASPEED_PINCTRL_FUNC(VPO12), ASPEED_PINCTRL_FUNC(VPO24), + ASPEED_PINCTRL_FUNC(WDTRST1), + ASPEED_PINCTRL_FUNC(WDTRST2), }; static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 87b46390b695..43221a3c7e23 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -10,6 +10,7 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/mfd/syscon.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -24,14 +25,28 @@ #include "../pinctrl-utils.h" #include "pinctrl-aspeed.h" -#define ASPEED_G5_NR_PINS 228 +#define ASPEED_G5_NR_PINS 232 -#define COND1 { SCU90, BIT(6), 0, 0 } -#define COND2 { SCU94, GENMASK(1, 0), 0, 0 } +#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } +#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } + +/* LHCR0 is offset from the end of the H8S/2168-compatible registers */ +#define LHCR0 0x20 +#define GFX064 0x64 #define B14 0 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); +#define D14 1 +SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); + +#define D13 2 +SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); +SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); +MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3); +FUNC_GROUP_DECL(SPI1CS1, D13); +FUNC_GROUP_DECL(TIMER3, D13); + #define E13 3 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); @@ -71,6 +86,32 @@ FUNC_GROUP_DECL(TIMER8, B13); FUNC_GROUP_DECL(MDIO2, C13, B13); +#define K19 8 +GPIO_PIN_DECL(K19, GPIOB0); + +#define L19 9 +GPIO_PIN_DECL(L19, GPIOB1); + +#define L18 10 +GPIO_PIN_DECL(L18, GPIOB2); + +#define K18 11 +GPIO_PIN_DECL(K18, GPIOB3); + +#define J20 12 +SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); + +#define H21 13 +#define H21_DESC SIG_DESC_SET(SCU80, 13) +SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC); +MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI); +FUNC_GROUP_DECL(LPCPD, H21); +FUNC_GROUP_DECL(LPCSMI, H21); + +#define H22 14 +SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); + #define H20 15 GPIO_PIN_DECL(H20, GPIOB7); @@ -167,7 +208,44 @@ MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT); FUNC_GROUP_DECL(GPID2, F20, D20); -#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21) +#define GPID4_DESC SIG_DESC_SET(SCU8C, 10) + +#define D21 28 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); +MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN); + +#define E20 29 +SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); +MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT); + +FUNC_GROUP_DECL(GPID4, D21, E20); + +#define GPID6_DESC SIG_DESC_SET(SCU8C, 11) + +#define G18 30 +SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); +MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN); + +#define C21 31 +SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); +MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT); + +FUNC_GROUP_DECL(GPID6, G18, C21); +FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); + +#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) #define B20 32 @@ -176,6 +254,7 @@ SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); +FUNC_GROUP_DECL(NCTS3, B20); #define C20 33 SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); @@ -183,12 +262,233 @@ SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); +FUNC_GROUP_DECL(NDCD3, C20); FUNC_GROUP_DECL(GPIE0, B20, C20); -#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 } -#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 } -#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 } +#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) + +#define F18 34 +SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); +MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN); +FUNC_GROUP_DECL(NDSR3, F18); + + +#define F17 35 +SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); +MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT); +FUNC_GROUP_DECL(NRI3, F17); + +FUNC_GROUP_DECL(GPIE2, F18, F17); + +#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) + +#define E18 36 +SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); +MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN); +FUNC_GROUP_DECL(NDTR3, E18); + +#define D19 37 +SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); +MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT); +FUNC_GROUP_DECL(NRTS3, D19); + +FUNC_GROUP_DECL(GPIE4, E18, D19); + +#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) + +#define A20 38 +SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); +MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN); +FUNC_GROUP_DECL(TXD3, A20); + +#define B19 39 +SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); +MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT); +FUNC_GROUP_DECL(RXD3, B19); + +FUNC_GROUP_DECL(GPIE6, A20, B19); + +#define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0) +#define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30) + +#define J19 40 +SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); +MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4); +FUNC_GROUP_DECL(NCTS4, J19); + +#define J18 41 +SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4); +FUNC_GROUP_DECL(NDCD4, J18); + +#define B22 42 +SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4); +FUNC_GROUP_DECL(NDSR4, B22); + +#define B21 43 +SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4); +FUNC_GROUP_DECL(NRI4, B21); + +#define A21 44 +SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); +MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4); +FUNC_GROUP_DECL(NDTR4, A21); + +#define H19 45 +SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); +MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4); +FUNC_GROUP_DECL(NRTS4, H19); + +#define G17 46 +SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); +MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4); +FUNC_GROUP_DECL(TXD4, G17); + +#define H18 47 +SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); +MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4); +FUNC_GROUP_DECL(RXD4, H18); + +FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18); +FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18); + +#define A19 48 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); +SS_PIN_DECL(A19, GPIOG0, SGPS1CK); + +#define E19 49 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); +SS_PIN_DECL(E19, GPIOG1, SGPS1LD); + +#define C19 50 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); +SS_PIN_DECL(C19, GPIOG2, SGPS1I0); + +#define E16 51 +SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); +SS_PIN_DECL(E16, GPIOG3, SGPS1I1); + +FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16); + +#define SGPS2_DESC SIG_DESC_SET(SCU94, 12) + +#define E17 52 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); +MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1); +FUNC_GROUP_DECL(SALT1, E17); + +#define D16 53 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); +MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2); +FUNC_GROUP_DECL(SALT2, D16); + +#define D15 54 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); +MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3); +FUNC_GROUP_DECL(SALT3, D15); + +#define E14 55 +SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); +MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4); +FUNC_GROUP_DECL(SALT4, E14); + +FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); + +#define UART6_DESC SIG_DESC_SET(SCU90, 7) + +#define A18 56 +SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6); + +#define B18 57 +SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6); + +#define D17 58 +SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6); + +#define C17 59 +SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6); + +#define A17 60 +SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6); + +#define B17 61 +SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC); +MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6); + +#define A16 62 +SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC); +SS_PIN_DECL(A16, GPIOH6, TXD6); + +#define D18 63 +SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC); +SS_PIN_DECL(D18, GPIOH7, RXD6); + +FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); + +#define SPI1_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } +#define SPI1DEBUG_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } +#define SPI1PASSTHRU_DESC \ + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } #define C18 64 SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); @@ -277,6 +577,30 @@ SS_PIN_DECL(N3, GPIOJ2, SGPMO); SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); SS_PIN_DECL(N4, GPIOJ3, SGPMI); +#define N5 76 +SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); +SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); +MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5); +FUNC_GROUP_DECL(VGAHS, N5); + +#define R4 77 +SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); +SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); +MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4); +FUNC_GROUP_DECL(VGAVS, R4); + +#define R3 78 +SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); +SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); +MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3); +FUNC_GROUP_DECL(DDCCLK, R3); + +#define T3 79 +SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); +SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); +MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3); +FUNC_GROUP_DECL(DDCDAT, T3); + #define I2C5_DESC SIG_DESC_SET(SCU90, 18) #define L3 80 @@ -325,10 +649,119 @@ SS_PIN_DECL(R1, GPIOK7, SDA8); FUNC_GROUP_DECL(I2C8, P2, R1); -#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 } -#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 } -#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } -#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 } +#define T2 88 +SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); + +#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 } +#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } +#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } +#define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5) + +#define T1 89 +#define T1_DESC SIG_DESC_SET(SCU84, 17) +SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2); +MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1); +FUNC_GROUP_DECL(NDCD1, T1); + +#define U1 90 +#define U1_DESC SIG_DESC_SET(SCU84, 18) +SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC); +MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1); +FUNC_GROUP_DECL(NDSR1, U1); + +#define U2 91 +#define U2_DESC SIG_DESC_SET(SCU84, 19) +SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2); +MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1); +FUNC_GROUP_DECL(NRI1, U2); + +#define P4 92 +#define P4_DESC SIG_DESC_SET(SCU84, 20) +SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2); +MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1); +FUNC_GROUP_DECL(NDTR1, P4); + +#define P3 93 +#define P3_DESC SIG_DESC_SET(SCU84, 21) +SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2); +MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1); +FUNC_GROUP_DECL(NRTS1, P3); + +#define V1 94 +#define V1_DESC SIG_DESC_SET(SCU84, 22) +SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2); +MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1); +FUNC_GROUP_DECL(TXD1, V1); + +#define W1 95 +#define W1_DESC SIG_DESC_SET(SCU84, 23) +SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2); +MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1); +FUNC_GROUP_DECL(RXD1, W1); + +#define Y1 96 +#define Y1_DESC SIG_DESC_SET(SCU84, 24) +SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2); +MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2); +FUNC_GROUP_DECL(NCTS2, Y1); + +#define AB2 97 +#define AB2_DESC SIG_DESC_SET(SCU84, 25) +SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2); +MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2); +FUNC_GROUP_DECL(NDCD2, AB2); + +#define AA1 98 +#define AA1_DESC SIG_DESC_SET(SCU84, 26) +SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2); +MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2); +FUNC_GROUP_DECL(NDSR2, AA1); + +#define Y2 99 +#define Y2_DESC SIG_DESC_SET(SCU84, 27) +SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2); +MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2); +FUNC_GROUP_DECL(NRI2, Y2); + +#define AA2 100 +#define AA2_DESC SIG_DESC_SET(SCU84, 28) +SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2); +MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2); +FUNC_GROUP_DECL(NDTR2, AA2); + +#define P5 101 +#define P5_DESC SIG_DESC_SET(SCU84, 29) +SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2); +MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2); +FUNC_GROUP_DECL(NRTS2, P5); + +#define R5 102 +#define R5_DESC SIG_DESC_SET(SCU84, 30) +SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2); +MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2); +FUNC_GROUP_DECL(TXD2, R5); + +#define T5 103 +#define T5_DESC SIG_DESC_SET(SCU84, 31) +SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2); +MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2); +FUNC_GROUP_DECL(RXD2, T5); #define V2 104 #define V2_DESC SIG_DESC_SET(SCU88, 0) @@ -394,9 +827,88 @@ SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); FUNC_GROUP_DECL(PWM7, T4); +#define U5 112 +SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), + COND2); +SS_PIN_DECL(U5, GPIOO0, VPIG8); + +#define U4 113 +SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), + COND2); +SS_PIN_DECL(U4, GPIOO1, VPIG9); + +#define V5 114 +SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC, + SIG_DESC_SET(SCU88, 10)); +SS_PIN_DECL(V5, GPIOO2, DASHV5); + +#define AB4 115 +SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC, + SIG_DESC_SET(SCU88, 11)); +SS_PIN_DECL(AB4, GPIOO3, DASHAB4); + +#define AB3 116 +SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12), + COND2); +SS_PIN_DECL(AB3, GPIOO4, VPIR2); + +#define Y4 117 +SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13), + COND2); +SS_PIN_DECL(Y4, GPIOO5, VPIR3); + +#define AA4 118 +SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14), + COND2); +SS_PIN_DECL(AA4, GPIOO6, VPIR4); + +#define W4 119 +SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15), + COND2); +SS_PIN_DECL(W4, GPIOO7, VPIR5); + +#define V4 120 +SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16), + COND2); +SS_PIN_DECL(V4, GPIOP0, VPIR6); + +#define W5 121 +SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17), + COND2); +SS_PIN_DECL(W5, GPIOP1, VPIR7); + +#define AA5 122 +SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18), + COND2); +SS_PIN_DECL(AA5, GPIOP2, VPIR8); + +#define AB5 123 +SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19), + COND2); +SS_PIN_DECL(AB5, GPIOP3, VPIR9); + +FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3, + U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5, + AB5); + +#define Y6 124 +SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), + SIG_DESC_SET(SCU88, 20)); +SS_PIN_DECL(Y6, GPIOP4, DASHY6); + +#define Y5 125 +SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), + SIG_DESC_SET(SCU88, 21)); +SS_PIN_DECL(Y5, GPIOP5, DASHY5); + +#define W6 126 +SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), + SIG_DESC_SET(SCU88, 22)); +SS_PIN_DECL(W6, GPIOP6, DASHW6); + #define V6 127 SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), - SIG_DESC_SET(SCU88, 23)); + SIG_DESC_SET(SCU88, 23)); SS_PIN_DECL(V6, GPIOP7, DASHV6); #define I2C3_DESC SIG_DESC_SET(SCU90, 16) @@ -441,6 +953,24 @@ SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1)); #define N20 135 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29)); +#define AA19 136 +SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2); + +#define T19 137 +SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2); + +#define T17 138 +SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2); + +#define Y19 139 +SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2); + +#define W19 140 +SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2); + +#define V19 141 +SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2); + #define D8 142 SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); SS_PIN_DECL(D8, GPIOR6, MDC1); @@ -451,6 +981,93 @@ SS_PIN_DECL(E10, GPIOR7, MDIO1); FUNC_GROUP_DECL(MDIO1, D8, E10); +#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } +#define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } +#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } +#define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } + +#define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7) + +#define V20 144 +#define V20_DESC SIG_DESC_SET(SCU8C, 0) +SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO), + SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC); +MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1); +FUNC_GROUP_DECL(SPI2CS1, V20); + +#define U19 145 +#define U19_DESC SIG_DESC_SET(SCU8C, 1) +SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO), + SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC); +MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT); +FUNC_GROUP_DECL(BMCINT, U19); + +#define R18 146 +#define R18_DESC SIG_DESC_SET(SCU8C, 2) +SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO), + SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC); +MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5); +FUNC_GROUP_DECL(SALT5, R18); + +#define P18 147 +#define P18_DESC SIG_DESC_SET(SCU8C, 3) +SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO), + SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC); +MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6); +FUNC_GROUP_DECL(SALT6, P18); + +#define R19 148 +#define R19_DESC SIG_DESC_SET(SCU8C, 4) +SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO), + SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2)); +SS_PIN_DECL(R19, GPIOS4, VPOB6); + +#define W20 149 +#define W20_DESC SIG_DESC_SET(SCU8C, 5) +SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO), + SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2)); +SS_PIN_DECL(W20, GPIOS5, VPOB7); + +#define U20 150 +#define U20_DESC SIG_DESC_SET(SCU8C, 6) +SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO), + SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2)); +SS_PIN_DECL(U20, GPIOS6, VPOB8); + +#define AA20 151 +#define AA20_DESC SIG_DESC_SET(SCU8C, 7) +SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO), + SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2)); +SS_PIN_DECL(AA20, GPIOS7, VPOB9); + /* RGMII1/RMII1 */ #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) @@ -632,6 +1249,481 @@ MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); +#define F4 176 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); +MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +FUNC_GROUP_DECL(ADC0, F4); + +#define F5 177 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); +MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +FUNC_GROUP_DECL(ADC1, F5); + +#define E2 178 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); +MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +FUNC_GROUP_DECL(ADC2, E2); + +#define E1 179 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); +MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +FUNC_GROUP_DECL(ADC3, E1); + +#define F3 180 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); +MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +FUNC_GROUP_DECL(ADC4, F3); + +#define E3 181 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); +MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +FUNC_GROUP_DECL(ADC5, E3); + +#define G5 182 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); +MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +FUNC_GROUP_DECL(ADC6, G5); + +#define G4 183 +SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); +MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +FUNC_GROUP_DECL(ADC7, G4); + +#define F2 184 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); +MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +FUNC_GROUP_DECL(ADC8, F2); + +#define G3 185 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); +MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +FUNC_GROUP_DECL(ADC9, G3); + +#define G2 186 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); +MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +FUNC_GROUP_DECL(ADC10, G2); + +#define F1 187 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); +MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +FUNC_GROUP_DECL(ADC11, F1); + +#define H5 188 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); +MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +FUNC_GROUP_DECL(ADC12, H5); + +#define G1 189 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); +MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +FUNC_GROUP_DECL(ADC13, G1); + +#define H3 190 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); +MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +FUNC_GROUP_DECL(ADC14, H3); + +#define H4 191 +SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); +MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +FUNC_GROUP_DECL(ADC15, H4); + +#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19) + +#define R22 192 +SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); +MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22); +FUNC_GROUP_DECL(SIOS3, R22); + +#define R21 193 +SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); +MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21); +FUNC_GROUP_DECL(SIOS5, R21); + +#define P22 194 +SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); +MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22); +FUNC_GROUP_DECL(SIOPWREQ, P22); + +#define P21 195 +SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); +MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21); +FUNC_GROUP_DECL(SIOONCTRL, P21); + +#define M18 196 +SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12)); + +#define M19 197 +SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13)); + +#define M20 198 +SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14)); + +#define P20 199 +SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15)); + +#define PNOR_DESC SIG_DESC_SET(SCU90, 31) + +#define Y20 200 +#define Y20_DESC SIG_DESC_SET(SCUA4, 16) +SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO), + SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2)); +SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC); +SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0); +MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI), + SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0)); +FUNC_GROUP_DECL(SIOPBI, Y20); + +#define AB20 201 +#define AB20_DESC SIG_DESC_SET(SCUA4, 17) +SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO), + SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2)); +SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC); +SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1); +MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD), + SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1)); +FUNC_GROUP_DECL(SIOPWRGD, AB20); + +#define AB21 202 +#define AB21_DESC SIG_DESC_SET(SCUA4, 18) +SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO), + SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2)); +SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC); +SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2); +MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO), + SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2)); +FUNC_GROUP_DECL(SIOPBO, AB21); + +#define AA21 203 +#define AA21_DESC SIG_DESC_SET(SCUA4, 19) +SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO), + SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2)); +SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC); +SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3); +MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI), + SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3)); +FUNC_GROUP_DECL(SIOSCI, AA21); + +FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); + +/* CRT DVO disabled, configured for single-edge mode */ +#define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 } + +/* CRT DVO disabled, configured for dual-edge mode */ +#define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 } + +/* CRT DVO enabled, configured for single-edge mode */ +#define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 } + +/* CRT DVO enabled, configured for dual-edge mode */ +#define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 } + +#define U21 204 +#define U21_DESC SIG_DESC_SET(SCUA4, 20) +SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO), + SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC); +MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4); + +#define W22 205 +#define W22_DESC SIG_DESC_SET(SCUA4, 21) +SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO), + SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC); +MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5); + +#define V22 206 +#define V22_DESC SIG_DESC_SET(SCUA4, 22) +SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO), + SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC); +MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6); + +#define W21 207 +#define W21_DESC SIG_DESC_SET(SCUA4, 23) +SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO), + SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC); +MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7); + +#define Y21 208 +#define Y21_DESC SIG_DESC_SET(SCUA4, 24) +SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO), + SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0); +MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7), + SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0)); +FUNC_GROUP_DECL(SALT7, Y21); + +#define V21 209 +#define V21_DESC SIG_DESC_SET(SCUA4, 25) +SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO), + SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1); +MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8), + SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1)); +FUNC_GROUP_DECL(SALT8, V21); + +#define Y22 210 +#define Y22_DESC SIG_DESC_SET(SCUA4, 26) +SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO), + SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2); +MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9), + SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2)); +FUNC_GROUP_DECL(SALT9, Y22); + +#define AA22 211 +#define AA22_DESC SIG_DESC_SET(SCUA4, 27) +SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO), + SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3); +MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10), + SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3)); +FUNC_GROUP_DECL(SALT10, AA22); + +#define U22 212 +#define U22_DESC SIG_DESC_SET(SCUA4, 28) +SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO), + SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4); +MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11), + SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4)); +FUNC_GROUP_DECL(SALT11, U22); + +#define T20 213 +#define T20_DESC SIG_DESC_SET(SCUA4, 29) +SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO), + SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5); +MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12), + SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5)); +FUNC_GROUP_DECL(SALT12, T20); + +#define N18 214 +#define N18_DESC SIG_DESC_SET(SCUA4, 30) +SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO), + SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6); +MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13), + SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6)); +FUNC_GROUP_DECL(SALT13, N18); + +#define P19 215 +#define P19_DESC SIG_DESC_SET(SCUA4, 31) +SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO), + SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7); +MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14), + SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7)); +FUNC_GROUP_DECL(SALT14, P19); + +#define N19 216 +#define N19_DESC SIG_DESC_SET(SCUA8, 0) +SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO), + SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC); +MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE); + +#define T21 217 +#define T21_DESC SIG_DESC_SET(SCUA8, 1) +SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO), + SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC); +MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE); + +FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, + AA22, U22, T20, N18, P19, N19, T21); + +#define T22 218 +#define T22_DESC SIG_DESC_SET(SCUA8, 2) +SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO), + SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC); +MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1); +FUNC_GROUP_DECL(WDTRST1, T22); + +#define R20 219 +#define R20_DESC SIG_DESC_SET(SCUA8, 3) +SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO), + SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2)); +SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC); +MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2); +FUNC_GROUP_DECL(WDTRST2, R20); + +FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, + AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20, + N18, P19, N19, T21, T22, R20); + +#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25) + +#define G21 224 +SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); +MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0); +FUNC_GROUP_DECL(LAD0, G21); + +#define G20 225 +SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); +MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1); +FUNC_GROUP_DECL(LAD1, G20); + +#define D22 226 +SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); +MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2); +FUNC_GROUP_DECL(LAD2, D22); + +#define E22 227 +SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); +MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3); +FUNC_GROUP_DECL(LAD3, E22); + +#define C22 228 +SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); +MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK); +FUNC_GROUP_DECL(LCLK, C22); + +#define F21 229 +SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); +MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME); +FUNC_GROUP_DECL(LFRAME, F21); + +#define F22 230 +SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); +MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ); +FUNC_GROUP_DECL(LSIRQ, F22); + +#define G22 231 +SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); +MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST); +FUNC_GROUP_DECL(LPCRST, G22); + +FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { @@ -641,12 +1733,32 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(A13), ASPEED_PINCTRL_PIN(A14), ASPEED_PINCTRL_PIN(A15), + ASPEED_PINCTRL_PIN(A16), + ASPEED_PINCTRL_PIN(A17), + ASPEED_PINCTRL_PIN(A18), + ASPEED_PINCTRL_PIN(A19), ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A20), + ASPEED_PINCTRL_PIN(A21), ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A4), ASPEED_PINCTRL_PIN(A5), ASPEED_PINCTRL_PIN(A9), + ASPEED_PINCTRL_PIN(AA1), + ASPEED_PINCTRL_PIN(AA19), + ASPEED_PINCTRL_PIN(AA2), + ASPEED_PINCTRL_PIN(AA20), + ASPEED_PINCTRL_PIN(AA21), + ASPEED_PINCTRL_PIN(AA22), ASPEED_PINCTRL_PIN(AA3), + ASPEED_PINCTRL_PIN(AA4), + ASPEED_PINCTRL_PIN(AA5), + ASPEED_PINCTRL_PIN(AB2), + ASPEED_PINCTRL_PIN(AB20), + ASPEED_PINCTRL_PIN(AB21), + ASPEED_PINCTRL_PIN(AB3), + ASPEED_PINCTRL_PIN(AB4), + ASPEED_PINCTRL_PIN(AB5), ASPEED_PINCTRL_PIN(B1), ASPEED_PINCTRL_PIN(B10), ASPEED_PINCTRL_PIN(B11), @@ -655,8 +1767,13 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(B14), ASPEED_PINCTRL_PIN(B15), ASPEED_PINCTRL_PIN(B16), + ASPEED_PINCTRL_PIN(B17), + ASPEED_PINCTRL_PIN(B18), + ASPEED_PINCTRL_PIN(B19), ASPEED_PINCTRL_PIN(B2), ASPEED_PINCTRL_PIN(B20), + ASPEED_PINCTRL_PIN(B21), + ASPEED_PINCTRL_PIN(B22), ASPEED_PINCTRL_PIN(B3), ASPEED_PINCTRL_PIN(B4), ASPEED_PINCTRL_PIN(B5), @@ -668,62 +1785,210 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(C14), ASPEED_PINCTRL_PIN(C15), ASPEED_PINCTRL_PIN(C16), + ASPEED_PINCTRL_PIN(C17), ASPEED_PINCTRL_PIN(C18), + ASPEED_PINCTRL_PIN(C19), ASPEED_PINCTRL_PIN(C2), ASPEED_PINCTRL_PIN(C20), + ASPEED_PINCTRL_PIN(C21), + ASPEED_PINCTRL_PIN(C22), ASPEED_PINCTRL_PIN(C3), ASPEED_PINCTRL_PIN(C4), ASPEED_PINCTRL_PIN(C5), ASPEED_PINCTRL_PIN(D1), ASPEED_PINCTRL_PIN(D10), + ASPEED_PINCTRL_PIN(D13), + ASPEED_PINCTRL_PIN(D14), + ASPEED_PINCTRL_PIN(D15), + ASPEED_PINCTRL_PIN(D16), + ASPEED_PINCTRL_PIN(D17), + ASPEED_PINCTRL_PIN(D18), + ASPEED_PINCTRL_PIN(D19), ASPEED_PINCTRL_PIN(D2), ASPEED_PINCTRL_PIN(D20), + ASPEED_PINCTRL_PIN(D21), + ASPEED_PINCTRL_PIN(D22), ASPEED_PINCTRL_PIN(D4), ASPEED_PINCTRL_PIN(D5), ASPEED_PINCTRL_PIN(D6), ASPEED_PINCTRL_PIN(D7), ASPEED_PINCTRL_PIN(D8), ASPEED_PINCTRL_PIN(D9), + ASPEED_PINCTRL_PIN(E1), ASPEED_PINCTRL_PIN(E10), ASPEED_PINCTRL_PIN(E12), ASPEED_PINCTRL_PIN(E13), + ASPEED_PINCTRL_PIN(E14), ASPEED_PINCTRL_PIN(E15), + ASPEED_PINCTRL_PIN(E16), + ASPEED_PINCTRL_PIN(E17), + ASPEED_PINCTRL_PIN(E18), + ASPEED_PINCTRL_PIN(E19), + ASPEED_PINCTRL_PIN(E2), + ASPEED_PINCTRL_PIN(E20), ASPEED_PINCTRL_PIN(E21), + ASPEED_PINCTRL_PIN(E22), + ASPEED_PINCTRL_PIN(E3), ASPEED_PINCTRL_PIN(E6), ASPEED_PINCTRL_PIN(E7), ASPEED_PINCTRL_PIN(E9), + ASPEED_PINCTRL_PIN(F1), + ASPEED_PINCTRL_PIN(F17), + ASPEED_PINCTRL_PIN(F18), ASPEED_PINCTRL_PIN(F19), + ASPEED_PINCTRL_PIN(F2), ASPEED_PINCTRL_PIN(F20), + ASPEED_PINCTRL_PIN(F21), + ASPEED_PINCTRL_PIN(F22), + ASPEED_PINCTRL_PIN(F3), + ASPEED_PINCTRL_PIN(F4), + ASPEED_PINCTRL_PIN(F5), ASPEED_PINCTRL_PIN(F9), + ASPEED_PINCTRL_PIN(G1), + ASPEED_PINCTRL_PIN(G17), + ASPEED_PINCTRL_PIN(G18), + ASPEED_PINCTRL_PIN(G2), + ASPEED_PINCTRL_PIN(G20), + ASPEED_PINCTRL_PIN(G21), + ASPEED_PINCTRL_PIN(G22), + ASPEED_PINCTRL_PIN(G3), + ASPEED_PINCTRL_PIN(G4), + ASPEED_PINCTRL_PIN(G5), + ASPEED_PINCTRL_PIN(H18), + ASPEED_PINCTRL_PIN(H19), ASPEED_PINCTRL_PIN(H20), + ASPEED_PINCTRL_PIN(H21), + ASPEED_PINCTRL_PIN(H22), + ASPEED_PINCTRL_PIN(H3), + ASPEED_PINCTRL_PIN(H4), + ASPEED_PINCTRL_PIN(H5), + ASPEED_PINCTRL_PIN(J18), + ASPEED_PINCTRL_PIN(J19), + ASPEED_PINCTRL_PIN(J20), + ASPEED_PINCTRL_PIN(K18), + ASPEED_PINCTRL_PIN(K19), ASPEED_PINCTRL_PIN(L1), + ASPEED_PINCTRL_PIN(L18), + ASPEED_PINCTRL_PIN(L19), ASPEED_PINCTRL_PIN(L2), ASPEED_PINCTRL_PIN(L3), ASPEED_PINCTRL_PIN(L4), + ASPEED_PINCTRL_PIN(M18), + ASPEED_PINCTRL_PIN(M19), + ASPEED_PINCTRL_PIN(M20), ASPEED_PINCTRL_PIN(N1), + ASPEED_PINCTRL_PIN(N18), + ASPEED_PINCTRL_PIN(N19), ASPEED_PINCTRL_PIN(N2), ASPEED_PINCTRL_PIN(N20), ASPEED_PINCTRL_PIN(N21), ASPEED_PINCTRL_PIN(N22), ASPEED_PINCTRL_PIN(N3), ASPEED_PINCTRL_PIN(N4), + ASPEED_PINCTRL_PIN(N5), ASPEED_PINCTRL_PIN(P1), + ASPEED_PINCTRL_PIN(P18), + ASPEED_PINCTRL_PIN(P19), ASPEED_PINCTRL_PIN(P2), + ASPEED_PINCTRL_PIN(P20), + ASPEED_PINCTRL_PIN(P21), + ASPEED_PINCTRL_PIN(P22), + ASPEED_PINCTRL_PIN(P3), + ASPEED_PINCTRL_PIN(P4), + ASPEED_PINCTRL_PIN(P5), ASPEED_PINCTRL_PIN(R1), + ASPEED_PINCTRL_PIN(R18), + ASPEED_PINCTRL_PIN(R19), + ASPEED_PINCTRL_PIN(R2), + ASPEED_PINCTRL_PIN(R20), + ASPEED_PINCTRL_PIN(R21), + ASPEED_PINCTRL_PIN(R22), + ASPEED_PINCTRL_PIN(R3), + ASPEED_PINCTRL_PIN(R4), + ASPEED_PINCTRL_PIN(R5), + ASPEED_PINCTRL_PIN(T1), + ASPEED_PINCTRL_PIN(T17), + ASPEED_PINCTRL_PIN(T19), + ASPEED_PINCTRL_PIN(T2), + ASPEED_PINCTRL_PIN(T20), + ASPEED_PINCTRL_PIN(T21), + ASPEED_PINCTRL_PIN(T22), + ASPEED_PINCTRL_PIN(T3), ASPEED_PINCTRL_PIN(T4), + ASPEED_PINCTRL_PIN(T5), + ASPEED_PINCTRL_PIN(U1), + ASPEED_PINCTRL_PIN(U19), + ASPEED_PINCTRL_PIN(U2), + ASPEED_PINCTRL_PIN(U20), + ASPEED_PINCTRL_PIN(U21), + ASPEED_PINCTRL_PIN(U22), ASPEED_PINCTRL_PIN(U3), + ASPEED_PINCTRL_PIN(U4), + ASPEED_PINCTRL_PIN(U5), + ASPEED_PINCTRL_PIN(V1), + ASPEED_PINCTRL_PIN(V19), ASPEED_PINCTRL_PIN(V2), + ASPEED_PINCTRL_PIN(V20), + ASPEED_PINCTRL_PIN(V21), + ASPEED_PINCTRL_PIN(V22), ASPEED_PINCTRL_PIN(V3), + ASPEED_PINCTRL_PIN(V4), + ASPEED_PINCTRL_PIN(V5), ASPEED_PINCTRL_PIN(V6), + ASPEED_PINCTRL_PIN(W1), + ASPEED_PINCTRL_PIN(W19), ASPEED_PINCTRL_PIN(W2), + ASPEED_PINCTRL_PIN(W20), + ASPEED_PINCTRL_PIN(W21), + ASPEED_PINCTRL_PIN(W22), ASPEED_PINCTRL_PIN(W3), + ASPEED_PINCTRL_PIN(W4), + ASPEED_PINCTRL_PIN(W5), + ASPEED_PINCTRL_PIN(W6), + ASPEED_PINCTRL_PIN(Y1), + ASPEED_PINCTRL_PIN(Y19), + ASPEED_PINCTRL_PIN(Y2), + ASPEED_PINCTRL_PIN(Y20), + ASPEED_PINCTRL_PIN(Y21), + ASPEED_PINCTRL_PIN(Y22), ASPEED_PINCTRL_PIN(Y3), + ASPEED_PINCTRL_PIN(Y4), + ASPEED_PINCTRL_PIN(Y5), + ASPEED_PINCTRL_PIN(Y6), }; static const struct aspeed_pin_group aspeed_g5_groups[] = { + ASPEED_PINCTRL_GROUP(ACPI), + ASPEED_PINCTRL_GROUP(ADC0), + ASPEED_PINCTRL_GROUP(ADC1), + ASPEED_PINCTRL_GROUP(ADC10), + ASPEED_PINCTRL_GROUP(ADC11), + ASPEED_PINCTRL_GROUP(ADC12), + ASPEED_PINCTRL_GROUP(ADC13), + ASPEED_PINCTRL_GROUP(ADC14), + ASPEED_PINCTRL_GROUP(ADC15), + ASPEED_PINCTRL_GROUP(ADC2), + ASPEED_PINCTRL_GROUP(ADC3), + ASPEED_PINCTRL_GROUP(ADC4), + ASPEED_PINCTRL_GROUP(ADC5), + ASPEED_PINCTRL_GROUP(ADC6), + ASPEED_PINCTRL_GROUP(ADC7), + ASPEED_PINCTRL_GROUP(ADC8), + ASPEED_PINCTRL_GROUP(ADC9), + ASPEED_PINCTRL_GROUP(BMCINT), + ASPEED_PINCTRL_GROUP(DDCCLK), + ASPEED_PINCTRL_GROUP(DDCDAT), + ASPEED_PINCTRL_GROUP(ESPI), + ASPEED_PINCTRL_GROUP(FWSPICS1), + ASPEED_PINCTRL_GROUP(FWSPICS2), ASPEED_PINCTRL_GROUP(GPID0), ASPEED_PINCTRL_GROUP(GPID2), + ASPEED_PINCTRL_GROUP(GPID4), + ASPEED_PINCTRL_GROUP(GPID6), ASPEED_PINCTRL_GROUP(GPIE0), + ASPEED_PINCTRL_GROUP(GPIE2), + ASPEED_PINCTRL_GROUP(GPIE4), + ASPEED_PINCTRL_GROUP(GPIE6), ASPEED_PINCTRL_GROUP(I2C10), ASPEED_PINCTRL_GROUP(I2C11), ASPEED_PINCTRL_GROUP(I2C12), @@ -736,11 +2001,50 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ASPEED_PINCTRL_GROUP(I2C7), ASPEED_PINCTRL_GROUP(I2C8), ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(LAD0), + ASPEED_PINCTRL_GROUP(LAD1), + ASPEED_PINCTRL_GROUP(LAD2), + ASPEED_PINCTRL_GROUP(LAD3), + ASPEED_PINCTRL_GROUP(LCLK), + ASPEED_PINCTRL_GROUP(LFRAME), + ASPEED_PINCTRL_GROUP(LPCHC), + ASPEED_PINCTRL_GROUP(LPCPD), + ASPEED_PINCTRL_GROUP(LPCPLUS), + ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCRST), + ASPEED_PINCTRL_GROUP(LPCSMI), + ASPEED_PINCTRL_GROUP(LSIRQ), ASPEED_PINCTRL_GROUP(MAC1LINK), + ASPEED_PINCTRL_GROUP(MAC2LINK), ASPEED_PINCTRL_GROUP(MDIO1), ASPEED_PINCTRL_GROUP(MDIO2), + ASPEED_PINCTRL_GROUP(NCTS1), + ASPEED_PINCTRL_GROUP(NCTS2), + ASPEED_PINCTRL_GROUP(NCTS3), + ASPEED_PINCTRL_GROUP(NCTS4), + ASPEED_PINCTRL_GROUP(NDCD1), + ASPEED_PINCTRL_GROUP(NDCD2), + ASPEED_PINCTRL_GROUP(NDCD3), + ASPEED_PINCTRL_GROUP(NDCD4), + ASPEED_PINCTRL_GROUP(NDSR1), + ASPEED_PINCTRL_GROUP(NDSR2), + ASPEED_PINCTRL_GROUP(NDSR3), + ASPEED_PINCTRL_GROUP(NDSR4), + ASPEED_PINCTRL_GROUP(NDTR1), + ASPEED_PINCTRL_GROUP(NDTR2), + ASPEED_PINCTRL_GROUP(NDTR3), + ASPEED_PINCTRL_GROUP(NDTR4), + ASPEED_PINCTRL_GROUP(NRI1), + ASPEED_PINCTRL_GROUP(NRI2), + ASPEED_PINCTRL_GROUP(NRI3), + ASPEED_PINCTRL_GROUP(NRI4), + ASPEED_PINCTRL_GROUP(NRTS1), + ASPEED_PINCTRL_GROUP(NRTS2), + ASPEED_PINCTRL_GROUP(NRTS3), + ASPEED_PINCTRL_GROUP(NRTS4), ASPEED_PINCTRL_GROUP(OSCCLK), ASPEED_PINCTRL_GROUP(PEWAKE), + ASPEED_PINCTRL_GROUP(PNOR), ASPEED_PINCTRL_GROUP(PWM0), ASPEED_PINCTRL_GROUP(PWM1), ASPEED_PINCTRL_GROUP(PWM2), @@ -753,22 +2057,102 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ASPEED_PINCTRL_GROUP(RGMII2), ASPEED_PINCTRL_GROUP(RMII1), ASPEED_PINCTRL_GROUP(RMII2), + ASPEED_PINCTRL_GROUP(RXD1), + ASPEED_PINCTRL_GROUP(RXD2), + ASPEED_PINCTRL_GROUP(RXD3), + ASPEED_PINCTRL_GROUP(RXD4), + ASPEED_PINCTRL_GROUP(SALT1), + ASPEED_PINCTRL_GROUP(SALT10), + ASPEED_PINCTRL_GROUP(SALT11), + ASPEED_PINCTRL_GROUP(SALT12), + ASPEED_PINCTRL_GROUP(SALT13), + ASPEED_PINCTRL_GROUP(SALT14), + ASPEED_PINCTRL_GROUP(SALT2), + ASPEED_PINCTRL_GROUP(SALT3), + ASPEED_PINCTRL_GROUP(SALT4), + ASPEED_PINCTRL_GROUP(SALT5), + ASPEED_PINCTRL_GROUP(SALT6), + ASPEED_PINCTRL_GROUP(SALT7), + ASPEED_PINCTRL_GROUP(SALT8), + ASPEED_PINCTRL_GROUP(SALT9), + ASPEED_PINCTRL_GROUP(SCL1), + ASPEED_PINCTRL_GROUP(SCL2), ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SD2), + ASPEED_PINCTRL_GROUP(SDA1), + ASPEED_PINCTRL_GROUP(SDA2), + ASPEED_PINCTRL_GROUP(SGPS1), + ASPEED_PINCTRL_GROUP(SGPS2), + ASPEED_PINCTRL_GROUP(SIOONCTRL), + ASPEED_PINCTRL_GROUP(SIOPBI), + ASPEED_PINCTRL_GROUP(SIOPBO), + ASPEED_PINCTRL_GROUP(SIOPWREQ), + ASPEED_PINCTRL_GROUP(SIOPWRGD), + ASPEED_PINCTRL_GROUP(SIOS3), + ASPEED_PINCTRL_GROUP(SIOS5), + ASPEED_PINCTRL_GROUP(SIOSCI), ASPEED_PINCTRL_GROUP(SPI1), + ASPEED_PINCTRL_GROUP(SPI1CS1), ASPEED_PINCTRL_GROUP(SPI1DEBUG), ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), + ASPEED_PINCTRL_GROUP(SPI2CK), + ASPEED_PINCTRL_GROUP(SPI2CS0), + ASPEED_PINCTRL_GROUP(SPI2CS1), + ASPEED_PINCTRL_GROUP(SPI2MISO), + ASPEED_PINCTRL_GROUP(SPI2MOSI), + ASPEED_PINCTRL_GROUP(TIMER3), ASPEED_PINCTRL_GROUP(TIMER4), ASPEED_PINCTRL_GROUP(TIMER5), ASPEED_PINCTRL_GROUP(TIMER6), ASPEED_PINCTRL_GROUP(TIMER7), ASPEED_PINCTRL_GROUP(TIMER8), + ASPEED_PINCTRL_GROUP(TXD1), + ASPEED_PINCTRL_GROUP(TXD2), + ASPEED_PINCTRL_GROUP(TXD3), + ASPEED_PINCTRL_GROUP(TXD4), + ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USBCKI), ASPEED_PINCTRL_GROUP(VGABIOSROM), + ASPEED_PINCTRL_GROUP(VGAHS), + ASPEED_PINCTRL_GROUP(VGAVS), + ASPEED_PINCTRL_GROUP(VPI24), + ASPEED_PINCTRL_GROUP(VPO), + ASPEED_PINCTRL_GROUP(WDTRST1), + ASPEED_PINCTRL_GROUP(WDTRST2), }; static const struct aspeed_pin_function aspeed_g5_functions[] = { + ASPEED_PINCTRL_FUNC(ACPI), + ASPEED_PINCTRL_FUNC(ADC0), + ASPEED_PINCTRL_FUNC(ADC1), + ASPEED_PINCTRL_FUNC(ADC10), + ASPEED_PINCTRL_FUNC(ADC11), + ASPEED_PINCTRL_FUNC(ADC12), + ASPEED_PINCTRL_FUNC(ADC13), + ASPEED_PINCTRL_FUNC(ADC14), + ASPEED_PINCTRL_FUNC(ADC15), + ASPEED_PINCTRL_FUNC(ADC2), + ASPEED_PINCTRL_FUNC(ADC3), + ASPEED_PINCTRL_FUNC(ADC4), + ASPEED_PINCTRL_FUNC(ADC5), + ASPEED_PINCTRL_FUNC(ADC6), + ASPEED_PINCTRL_FUNC(ADC7), + ASPEED_PINCTRL_FUNC(ADC8), + ASPEED_PINCTRL_FUNC(ADC9), + ASPEED_PINCTRL_FUNC(BMCINT), + ASPEED_PINCTRL_FUNC(DDCCLK), + ASPEED_PINCTRL_FUNC(DDCDAT), + ASPEED_PINCTRL_FUNC(ESPI), + ASPEED_PINCTRL_FUNC(FWSPICS1), + ASPEED_PINCTRL_FUNC(FWSPICS2), ASPEED_PINCTRL_FUNC(GPID0), ASPEED_PINCTRL_FUNC(GPID2), + ASPEED_PINCTRL_FUNC(GPID4), + ASPEED_PINCTRL_FUNC(GPID6), ASPEED_PINCTRL_FUNC(GPIE0), + ASPEED_PINCTRL_FUNC(GPIE2), + ASPEED_PINCTRL_FUNC(GPIE4), + ASPEED_PINCTRL_FUNC(GPIE6), ASPEED_PINCTRL_FUNC(I2C10), ASPEED_PINCTRL_FUNC(I2C11), ASPEED_PINCTRL_FUNC(I2C12), @@ -781,11 +2165,50 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ASPEED_PINCTRL_FUNC(I2C7), ASPEED_PINCTRL_FUNC(I2C8), ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(LAD0), + ASPEED_PINCTRL_FUNC(LAD1), + ASPEED_PINCTRL_FUNC(LAD2), + ASPEED_PINCTRL_FUNC(LAD3), + ASPEED_PINCTRL_FUNC(LCLK), + ASPEED_PINCTRL_FUNC(LFRAME), + ASPEED_PINCTRL_FUNC(LPCHC), + ASPEED_PINCTRL_FUNC(LPCPD), + ASPEED_PINCTRL_FUNC(LPCPLUS), + ASPEED_PINCTRL_FUNC(LPCPME), + ASPEED_PINCTRL_FUNC(LPCRST), + ASPEED_PINCTRL_FUNC(LPCSMI), + ASPEED_PINCTRL_FUNC(LSIRQ), ASPEED_PINCTRL_FUNC(MAC1LINK), + ASPEED_PINCTRL_FUNC(MAC2LINK), ASPEED_PINCTRL_FUNC(MDIO1), ASPEED_PINCTRL_FUNC(MDIO2), + ASPEED_PINCTRL_FUNC(NCTS1), + ASPEED_PINCTRL_FUNC(NCTS2), + ASPEED_PINCTRL_FUNC(NCTS3), + ASPEED_PINCTRL_FUNC(NCTS4), + ASPEED_PINCTRL_FUNC(NDCD1), + ASPEED_PINCTRL_FUNC(NDCD2), + ASPEED_PINCTRL_FUNC(NDCD3), + ASPEED_PINCTRL_FUNC(NDCD4), + ASPEED_PINCTRL_FUNC(NDSR1), + ASPEED_PINCTRL_FUNC(NDSR2), + ASPEED_PINCTRL_FUNC(NDSR3), + ASPEED_PINCTRL_FUNC(NDSR4), + ASPEED_PINCTRL_FUNC(NDTR1), + ASPEED_PINCTRL_FUNC(NDTR2), + ASPEED_PINCTRL_FUNC(NDTR3), + ASPEED_PINCTRL_FUNC(NDTR4), + ASPEED_PINCTRL_FUNC(NRI1), + ASPEED_PINCTRL_FUNC(NRI2), + ASPEED_PINCTRL_FUNC(NRI3), + ASPEED_PINCTRL_FUNC(NRI4), + ASPEED_PINCTRL_FUNC(NRTS1), + ASPEED_PINCTRL_FUNC(NRTS2), + ASPEED_PINCTRL_FUNC(NRTS3), + ASPEED_PINCTRL_FUNC(NRTS4), ASPEED_PINCTRL_FUNC(OSCCLK), ASPEED_PINCTRL_FUNC(PEWAKE), + ASPEED_PINCTRL_FUNC(PNOR), ASPEED_PINCTRL_FUNC(PWM0), ASPEED_PINCTRL_FUNC(PWM1), ASPEED_PINCTRL_FUNC(PWM2), @@ -798,16 +2221,68 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ASPEED_PINCTRL_FUNC(RGMII2), ASPEED_PINCTRL_FUNC(RMII1), ASPEED_PINCTRL_FUNC(RMII2), + ASPEED_PINCTRL_FUNC(RXD1), + ASPEED_PINCTRL_FUNC(RXD2), + ASPEED_PINCTRL_FUNC(RXD3), + ASPEED_PINCTRL_FUNC(RXD4), + ASPEED_PINCTRL_FUNC(SALT1), + ASPEED_PINCTRL_FUNC(SALT10), + ASPEED_PINCTRL_FUNC(SALT11), + ASPEED_PINCTRL_FUNC(SALT12), + ASPEED_PINCTRL_FUNC(SALT13), + ASPEED_PINCTRL_FUNC(SALT14), + ASPEED_PINCTRL_FUNC(SALT2), + ASPEED_PINCTRL_FUNC(SALT3), + ASPEED_PINCTRL_FUNC(SALT4), + ASPEED_PINCTRL_FUNC(SALT5), + ASPEED_PINCTRL_FUNC(SALT6), + ASPEED_PINCTRL_FUNC(SALT7), + ASPEED_PINCTRL_FUNC(SALT8), + ASPEED_PINCTRL_FUNC(SALT9), + ASPEED_PINCTRL_FUNC(SCL1), + ASPEED_PINCTRL_FUNC(SCL2), ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SD2), + ASPEED_PINCTRL_FUNC(SDA1), + ASPEED_PINCTRL_FUNC(SDA2), + ASPEED_PINCTRL_FUNC(SGPS1), + ASPEED_PINCTRL_FUNC(SGPS2), + ASPEED_PINCTRL_FUNC(SIOONCTRL), + ASPEED_PINCTRL_FUNC(SIOPBI), + ASPEED_PINCTRL_FUNC(SIOPBO), + ASPEED_PINCTRL_FUNC(SIOPWREQ), + ASPEED_PINCTRL_FUNC(SIOPWRGD), + ASPEED_PINCTRL_FUNC(SIOS3), + ASPEED_PINCTRL_FUNC(SIOS5), + ASPEED_PINCTRL_FUNC(SIOSCI), ASPEED_PINCTRL_FUNC(SPI1), + ASPEED_PINCTRL_FUNC(SPI1CS1), ASPEED_PINCTRL_FUNC(SPI1DEBUG), ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), + ASPEED_PINCTRL_FUNC(SPI2CK), + ASPEED_PINCTRL_FUNC(SPI2CS0), + ASPEED_PINCTRL_FUNC(SPI2CS1), + ASPEED_PINCTRL_FUNC(SPI2MISO), + ASPEED_PINCTRL_FUNC(SPI2MOSI), + ASPEED_PINCTRL_FUNC(TIMER3), ASPEED_PINCTRL_FUNC(TIMER4), ASPEED_PINCTRL_FUNC(TIMER5), ASPEED_PINCTRL_FUNC(TIMER6), ASPEED_PINCTRL_FUNC(TIMER7), ASPEED_PINCTRL_FUNC(TIMER8), + ASPEED_PINCTRL_FUNC(TXD1), + ASPEED_PINCTRL_FUNC(TXD2), + ASPEED_PINCTRL_FUNC(TXD3), + ASPEED_PINCTRL_FUNC(TXD4), + ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USBCKI), ASPEED_PINCTRL_FUNC(VGABIOSROM), + ASPEED_PINCTRL_FUNC(VGAHS), + ASPEED_PINCTRL_FUNC(VGAVS), + ASPEED_PINCTRL_FUNC(VPI24), + ASPEED_PINCTRL_FUNC(VPO), + ASPEED_PINCTRL_FUNC(WDTRST1), + ASPEED_PINCTRL_FUNC(WDTRST2), }; static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { @@ -848,10 +2323,35 @@ static struct pinctrl_desc aspeed_g5_pinctrl_desc = { static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) { int i; + struct regmap *map; + struct device_node *node; for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) aspeed_g5_pins[i].number = i; + node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0); + map = syscon_node_to_regmap(node); + of_node_put(node); + if (IS_ERR(map)) { + dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n"); + map = NULL; + } + aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX] = map; + + node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1); + if (node) { + map = syscon_node_to_regmap(node->parent); + if (IS_ERR(map)) { + dev_warn(&pdev->dev, "LHC parent is not a syscon, some mux configurations may fail\n"); + map = NULL; + } + } else { + dev_warn(&pdev->dev, "No LHC phandle found, some mux configurations may fail\n"); + map = NULL; + } + of_node_put(node); + aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPC] = map; + return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, &aspeed_g5_pinctrl_data); } diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 49aeba912531..76f62bd45f02 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -14,6 +14,12 @@ #include "../core.h" #include "pinctrl-aspeed.h" +static const char *const aspeed_pinmux_ips[] = { + [ASPEED_IP_SCU] = "SCU", + [ASPEED_IP_GFX] = "GFX", + [ASPEED_IP_LPC] = "LPC", +}; + int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) { struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); @@ -78,7 +84,8 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, static inline void aspeed_sig_desc_print_val( const struct aspeed_sig_desc *desc, bool enable, u32 rv) { - pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg, + pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n", + aspeed_pinmux_ips[desc->ip], desc->reg, desc->mask, enable ? desc->enable : desc->disable, (rv & desc->mask) >> __ffs(desc->mask), rv); } @@ -88,10 +95,11 @@ static inline void aspeed_sig_desc_print_val( * * @desc: The signal descriptor of interest * @enabled: True to query the enabled state, false to query disabled state - * @regmap: The SCU regmap instance + * @regmap: The IP block's regmap instance * - * @return True if the descriptor's bitfield is configured to the state - * selected by @enabled, false otherwise + * Return: 1 if the descriptor's bitfield is configured to the state + * selected by @enabled, 0 if not, and less than zero if an unrecoverable + * failure occurred * * Evaluation of descriptor state is non-trivial in that it is not a binary * outcome: The bitfields can be greater than one bit in size and thus can take @@ -99,14 +107,19 @@ static inline void aspeed_sig_desc_print_val( * descriptor (typically this means a different function to the one of interest * is enabled). Thus we must explicitly test for either condition as required. */ -static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, +static int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled, struct regmap *map) { + int ret; unsigned int raw; u32 want; - if (regmap_read(map, desc->reg, &raw) < 0) - return false; + if (!map) + return -ENODEV; + + ret = regmap_read(map, desc->reg, &raw); + if (ret) + return ret; aspeed_sig_desc_print_val(desc, enabled, raw); want = enabled ? desc->enable : desc->disable; @@ -119,10 +132,10 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, * * @expr: An expression controlling the signal for a mux function on a pin * @enabled: True to query the enabled state, false to query disabled state - * @regmap: The SCU regmap instance + * @maps: The list of regmap instances * - * @return True if the expression composed by @enabled evaluates true, false - * otherwise + * Return: 1 if the expression composed by @enabled evaluates true, 0 if not, + * and less than zero if an unrecoverable failure occurred. * * A mux function is enabled or disabled if the function's signal expression * for each pin in the function's pin group evaluates true for the desired @@ -135,19 +148,21 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, * neither the enabled nor disabled state. Thus we must explicitly test for * either condition as required. */ -static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, - bool enabled, struct regmap *map) +static int aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, + bool enabled, struct regmap * const *maps) { int i; + int ret; for (i = 0; i < expr->ndescs; i++) { const struct aspeed_sig_desc *desc = &expr->descs[i]; - if (!aspeed_sig_desc_eval(desc, enabled, map)) - return false; + ret = aspeed_sig_desc_eval(desc, enabled, maps[desc->ip]); + if (ret <= 0) + return ret; } - return true; + return 1; } /** @@ -158,19 +173,24 @@ static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr, * configured * @enable: true to enable an function's signal through a pin's signal * expression, false to disable the function's signal - * @map: The SCU's regmap instance for pinmux register access. + * @maps: The list of regmap instances for pinmux register access. * - * @return true if the expression is configured as requested, false otherwise + * Return: 0 if the expression is configured as requested and a negative error + * code otherwise */ -static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, - bool enable, struct regmap *map) +static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, + bool enable, struct regmap * const *maps) { + int ret; int i; for (i = 0; i < expr->ndescs; i++) { - bool ret; const struct aspeed_sig_desc *desc = &expr->descs[i]; u32 pattern = enable ? desc->enable : desc->disable; + u32 val = (pattern << __ffs(desc->mask)); + + if (!maps[desc->ip]) + return -ENODEV; /* * Strap registers are configured in hardware or by early-boot @@ -179,64 +199,79 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, * deconfigured and is the reason we re-evaluate after writing * all descriptor bits. */ - if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) + if ((desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) && + desc->ip == ASPEED_IP_SCU) continue; - ret = regmap_update_bits(map, desc->reg, desc->mask, - pattern << __ffs(desc->mask)) == 0; + ret = regmap_update_bits(maps[desc->ip], desc->reg, + desc->mask, val); - if (!ret) + if (ret) return ret; } - return aspeed_sig_expr_eval(expr, enable, map); + ret = aspeed_sig_expr_eval(expr, enable, maps); + if (ret < 0) + return ret; + + if (!ret) + return -EPERM; + + return 0; } -static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr, - struct regmap *map) +static int aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr, + struct regmap * const *maps) { - if (aspeed_sig_expr_eval(expr, true, map)) - return true; + int ret; + + ret = aspeed_sig_expr_eval(expr, true, maps); + if (ret < 0) + return ret; + + if (!ret) + return aspeed_sig_expr_set(expr, true, maps); - return aspeed_sig_expr_set(expr, true, map); + return 0; } -static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, - struct regmap *map) +static int aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr, + struct regmap * const *maps) { - if (!aspeed_sig_expr_eval(expr, true, map)) - return true; + int ret; + + ret = aspeed_sig_expr_eval(expr, true, maps); + if (ret < 0) + return ret; + + if (ret) + return aspeed_sig_expr_set(expr, false, maps); - return aspeed_sig_expr_set(expr, false, map); + return 0; } /** * Disable a signal on a pin by disabling all provided signal expressions. * * @exprs: The list of signal expressions (from a priority level on a pin) - * @map: The SCU's regmap instance for pinmux register access. + * @maps: The list of regmap instances for pinmux register access. * - * @return true if all expressions in the list are successfully disabled, false - * otherwise + * Return: 0 if all expressions are disabled, otherwise a negative error code */ -static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs, - struct regmap *map) +static int aspeed_disable_sig(const struct aspeed_sig_expr **exprs, + struct regmap * const *maps) { - bool disabled = true; + int ret = 0; if (!exprs) return true; - while (*exprs) { - bool ret; - - ret = aspeed_sig_expr_disable(*exprs, map); - disabled = disabled && ret; - + while (*exprs && !ret) { + ret = aspeed_sig_expr_disable(*exprs, maps); exprs++; } - return disabled; + return ret; } /** @@ -246,8 +281,8 @@ static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs, * @exprs: List of signal expressions (haystack) * @name: The name of the requested function (needle) * - * @return A pointer to the signal expression whose function tag matches the - * provided name, otherwise NULL. + * Return: A pointer to the signal expression whose function tag matches the + * provided name, otherwise NULL. * */ static const struct aspeed_sig_expr *aspeed_find_expr_by_name( @@ -330,6 +365,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { int i; + int ret; const struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); const struct aspeed_pin_group *pgroup = &pdata->groups[group]; @@ -343,6 +379,8 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, const struct aspeed_sig_expr **funcs; const struct aspeed_sig_expr ***prios; + pr_debug("Muxing pin %d for %s\n", pin, pfunc->name); + if (!pdesc) return -EINVAL; @@ -358,8 +396,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, if (expr) break; - if (!aspeed_disable_sig(funcs, pdata->map)) - return -EPERM; + ret = aspeed_disable_sig(funcs, pdata->maps); + if (ret) + return ret; prios++; } @@ -377,8 +416,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, return -ENXIO; } - if (!aspeed_sig_expr_enable(expr, pdata->map)) - return -EPERM; + ret = aspeed_sig_expr_enable(expr, pdata->maps); + if (ret) + return ret; } return 0; @@ -414,6 +454,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) { + int ret; const struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data; @@ -432,8 +473,9 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, if (aspeed_gpio_in_exprs(funcs)) break; - if (!aspeed_disable_sig(funcs, pdata->map)) - return -EPERM; + ret = aspeed_disable_sig(funcs, pdata->maps); + if (ret) + return ret; prios++; } @@ -462,10 +504,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, * If GPIO is not the lowest priority signal type, assume there is only * one expression defined to enable the GPIO function */ - if (!aspeed_sig_expr_enable(expr, pdata->map)) - return -EPERM; - - return 0; + return aspeed_sig_expr_enable(expr, pdata->maps); } int aspeed_pinctrl_probe(struct platform_device *pdev, @@ -481,10 +520,10 @@ int aspeed_pinctrl_probe(struct platform_device *pdev, return -ENODEV; } - pdata->map = syscon_node_to_regmap(parent->of_node); - if (IS_ERR(pdata->map)) { + pdata->maps[ASPEED_IP_SCU] = syscon_node_to_regmap(parent->of_node); + if (IS_ERR(pdata->maps[ASPEED_IP_SCU])) { dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n"); - return PTR_ERR(pdata->map); + return PTR_ERR(pdata->maps[ASPEED_IP_SCU]); } pctl = pinctrl_register(pdesc, &pdev->dev, pdata); diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 3e72ef8c54bf..08a10d4db229 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -232,6 +232,11 @@ * group. */ +#define ASPEED_IP_SCU 0 +#define ASPEED_IP_GFX 1 +#define ASPEED_IP_LPC 2 +#define ASPEED_NR_PINMUX_IPS 3 + /* * The "Multi-function Pins Mapping and Control" table in the SoC datasheet * references registers by the device/offset mnemonic. The register macros @@ -255,13 +260,16 @@ #define SCUA0 0xA0 /* Multi-function Pin Control #7 */ #define SCUA4 0xA4 /* Multi-function Pin Control #8 */ #define SCUA8 0xA8 /* Multi-function Pin Control #9 */ +#define SCUAC 0xAC /* Multi-function Pin Control #10 */ #define HW_STRAP2 0xD0 /* Strapping */ /** * A signal descriptor, which describes the register, bits and the * enable/disable values that should be compared or written. * - * @reg: The register offset from base in bytes + * @ip: The IP block identifier, used as an index into the regmap array in + * struct aspeed_pinctrl_data + * @reg: The register offset with respect to the base address of the IP block * @mask: The mask to apply to the register. The lowest set bit of the mask is * used to derive the shift value. * @enable: The value that enables the function. Value should be in the LSBs, @@ -270,6 +278,7 @@ * LSBs, not at the position of the mask. */ struct aspeed_sig_desc { + unsigned int ip; unsigned int reg; u32 mask; u32 enable; @@ -313,24 +322,30 @@ struct aspeed_pin_desc { /* Macro hell */ +#define SIG_DESC_IP_BIT(ip, reg, idx, val) \ + { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } + /** - * Short-hand macro for describing a configuration enabled by the state of one - * bit. The disable value is derived. + * Short-hand macro for describing an SCU descriptor enabled by the state of + * one bit. The disable value is derived. * * @reg: The signal's associated register, offset from base * @idx: The signal's bit index in the register * @val: The value (0 or 1) that enables the function */ #define SIG_DESC_BIT(reg, idx, val) \ - { reg, BIT_MASK(idx), val, (((val) + 1) & 1) } + SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) + +#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1) /** - * A further short-hand macro describing a configuration enabled with a set bit. + * A further short-hand macro expanding to an SCU descriptor enabled by a set + * bit. * - * @reg: The configuration's associated register, offset from base - * @idx: The configuration's bit index in the register + * @reg: The register, offset from base + * @idx: The bit index in the register */ -#define SIG_DESC_SET(reg, idx) SIG_DESC_BIT(reg, idx, 1) +#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func #define SIG_DESC_LIST_DECL(sig, func, ...) \ @@ -500,7 +515,7 @@ struct aspeed_pin_desc { MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) struct aspeed_pinctrl_data { - struct regmap *map; + struct regmap *maps[ASPEED_NR_PINMUX_IPS]; const struct pinctrl_pin_desc *pins; const unsigned int npins; diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 597d4641e348..d69046537b75 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -237,10 +237,8 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, } pindesc = kzalloc(sizeof(*pindesc), GFP_KERNEL); - if (pindesc == NULL) { - dev_err(pctldev->dev, "failed to alloc struct pin_desc\n"); + if (!pindesc) return -ENOMEM; - } /* Set owner */ pindesc->pctldev = pctldev; @@ -540,6 +538,182 @@ void pinctrl_remove_gpio_range(struct pinctrl_dev *pctldev, } EXPORT_SYMBOL_GPL(pinctrl_remove_gpio_range); +#ifdef CONFIG_GENERIC_PINCTRL_GROUPS + +/** + * pinctrl_generic_get_group_count() - returns the number of pin groups + * @pctldev: pin controller device + */ +int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev) +{ + return pctldev->num_groups; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_count); + +/** + * pinctrl_generic_get_group_name() - returns the name of a pin group + * @pctldev: pin controller device + * @selector: group number + */ +const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct group_desc *group; + + group = radix_tree_lookup(&pctldev->pin_group_tree, + selector); + if (!group) + return NULL; + + return group->name; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_name); + +/** + * pinctrl_generic_get_group_pins() - gets the pin group pins + * @pctldev: pin controller device + * @selector: group number + * @pins: pins in the group + * @num_pins: number of pins in the group + */ +int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct group_desc *group; + + group = radix_tree_lookup(&pctldev->pin_group_tree, + selector); + if (!group) { + dev_err(pctldev->dev, "%s could not find pingroup%i\n", + __func__, selector); + return -EINVAL; + } + + *pins = group->pins; + *num_pins = group->num_pins; + + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_get_group_pins); + +/** + * pinctrl_generic_get_group() - returns a pin group based on the number + * @pctldev: pin controller device + * @gselector: group number + */ +struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct group_desc *group; + + group = radix_tree_lookup(&pctldev->pin_group_tree, + selector); + if (!group) + return NULL; + + return group; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_get_group); + +/** + * pinctrl_generic_add_group() - adds a new pin group + * @pctldev: pin controller device + * @name: name of the pin group + * @pins: pins in the pin group + * @num_pins: number of pins in the pin group + * @data: pin controller driver specific data + * + * Note that the caller must take care of locking. + */ +int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, + int *pins, int num_pins, void *data) +{ + struct group_desc *group; + + group = devm_kzalloc(pctldev->dev, sizeof(*group), GFP_KERNEL); + if (!group) + return -ENOMEM; + + group->name = name; + group->pins = pins; + group->num_pins = num_pins; + group->data = data; + + radix_tree_insert(&pctldev->pin_group_tree, pctldev->num_groups, + group); + + pctldev->num_groups++; + + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_add_group); + +/** + * pinctrl_generic_remove_group() - removes a numbered pin group + * @pctldev: pin controller device + * @selector: group number + * + * Note that the caller must take care of locking. + */ +int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct group_desc *group; + + group = radix_tree_lookup(&pctldev->pin_group_tree, + selector); + if (!group) + return -ENOENT; + + radix_tree_delete(&pctldev->pin_group_tree, selector); + devm_kfree(pctldev->dev, group); + + pctldev->num_groups--; + + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_generic_remove_group); + +/** + * pinctrl_generic_free_groups() - removes all pin groups + * @pctldev: pin controller device + * + * Note that the caller must take care of locking. + */ +static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev) +{ + struct radix_tree_iter iter; + struct group_desc *group; + unsigned long *indices; + void **slot; + int i = 0; + + indices = devm_kzalloc(pctldev->dev, sizeof(*indices) * + pctldev->num_groups, GFP_KERNEL); + if (!indices) + return; + + radix_tree_for_each_slot(slot, &pctldev->pin_group_tree, &iter, 0) + indices[i++] = iter.index; + + for (i = 0; i < pctldev->num_groups; i++) { + group = radix_tree_lookup(&pctldev->pin_group_tree, + indices[i]); + radix_tree_delete(&pctldev->pin_group_tree, indices[i]); + devm_kfree(pctldev->dev, group); + } + + pctldev->num_groups = 0; +} + +#else +static inline void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev) +{ +} +#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */ + /** * pinctrl_get_group_selector() - returns the group selector for a group * @pctldev: the pin controller handling the group @@ -735,11 +909,8 @@ static struct pinctrl_state *create_state(struct pinctrl *p, struct pinctrl_state *state; state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state == NULL) { - dev_err(p->dev, - "failed to alloc struct pinctrl_state\n"); + if (!state) return ERR_PTR(-ENOMEM); - } state->name = name; INIT_LIST_HEAD(&state->settings); @@ -749,7 +920,8 @@ static struct pinctrl_state *create_state(struct pinctrl *p, return state; } -static int add_setting(struct pinctrl *p, struct pinctrl_map const *map) +static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev, + struct pinctrl_map const *map) { struct pinctrl_state *state; struct pinctrl_setting *setting; @@ -765,15 +937,16 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map) return 0; setting = kzalloc(sizeof(*setting), GFP_KERNEL); - if (setting == NULL) { - dev_err(p->dev, - "failed to alloc struct pinctrl_setting\n"); + if (!setting) return -ENOMEM; - } setting->type = map->type; - setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); + if (pctldev) + setting->pctldev = pctldev; + else + setting->pctldev = + get_pinctrl_dev_from_devname(map->ctrl_dev_name); if (setting->pctldev == NULL) { kfree(setting); /* Do not defer probing of hogs (circular loop) */ @@ -829,7 +1002,8 @@ static struct pinctrl *find_pinctrl(struct device *dev) static void pinctrl_free(struct pinctrl *p, bool inlist); -static struct pinctrl *create_pinctrl(struct device *dev) +static struct pinctrl *create_pinctrl(struct device *dev, + struct pinctrl_dev *pctldev) { struct pinctrl *p; const char *devname; @@ -844,15 +1018,13 @@ static struct pinctrl *create_pinctrl(struct device *dev) * a pin control handle with pinctrl_get() */ p = kzalloc(sizeof(*p), GFP_KERNEL); - if (p == NULL) { - dev_err(dev, "failed to alloc struct pinctrl\n"); + if (!p) return ERR_PTR(-ENOMEM); - } p->dev = dev; INIT_LIST_HEAD(&p->states); INIT_LIST_HEAD(&p->dt_maps); - ret = pinctrl_dt_to_map(p); + ret = pinctrl_dt_to_map(p, pctldev); if (ret < 0) { kfree(p); return ERR_PTR(ret); @@ -867,7 +1039,7 @@ static struct pinctrl *create_pinctrl(struct device *dev) if (strcmp(map->dev_name, devname)) continue; - ret = add_setting(p, map); + ret = add_setting(p, pctldev, map); /* * At this point the adding of a setting may: * @@ -928,7 +1100,7 @@ struct pinctrl *pinctrl_get(struct device *dev) return p; } - return create_pinctrl(dev); + return create_pinctrl(dev, NULL); } EXPORT_SYMBOL_GPL(pinctrl_get); @@ -1204,10 +1376,8 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, } maps_node = kzalloc(sizeof(*maps_node), GFP_KERNEL); - if (!maps_node) { - pr_err("failed to alloc struct pinctrl_maps\n"); + if (!maps_node) return -ENOMEM; - } maps_node->num_maps = num_maps; if (dup) { @@ -1760,20 +1930,18 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev) !ops->get_group_name) return -EINVAL; - if (ops->dt_node_to_map && !ops->dt_free_map) - return -EINVAL; - return 0; } /** - * pinctrl_register() - register a pin controller device + * pinctrl_init_controller() - init a pin controller device * @pctldesc: descriptor for this pin controller * @dev: parent device for this pin controller * @driver_data: private pin controller data for this pin controller */ -struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, - struct device *dev, void *driver_data) +struct pinctrl_dev *pinctrl_init_controller(struct pinctrl_desc *pctldesc, + struct device *dev, + void *driver_data) { struct pinctrl_dev *pctldev; int ret; @@ -1784,17 +1952,22 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, return ERR_PTR(-EINVAL); pctldev = kzalloc(sizeof(*pctldev), GFP_KERNEL); - if (pctldev == NULL) { - dev_err(dev, "failed to alloc struct pinctrl_dev\n"); + if (!pctldev) return ERR_PTR(-ENOMEM); - } /* Initialize pin control device struct */ pctldev->owner = pctldesc->owner; pctldev->desc = pctldesc; pctldev->driver_data = driver_data; INIT_RADIX_TREE(&pctldev->pin_desc_tree, GFP_KERNEL); +#ifdef CONFIG_GENERIC_PINCTRL_GROUPS + INIT_RADIX_TREE(&pctldev->pin_group_tree, GFP_KERNEL); +#endif +#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS + INIT_RADIX_TREE(&pctldev->pin_function_tree, GFP_KERNEL); +#endif INIT_LIST_HEAD(&pctldev->gpio_ranges); + INIT_LIST_HEAD(&pctldev->node); pctldev->dev = dev; mutex_init(&pctldev->mutex); @@ -1829,21 +2002,28 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, goto out_err; } - mutex_lock(&pinctrldev_list_mutex); - list_add_tail(&pctldev->node, &pinctrldev_list); - mutex_unlock(&pinctrldev_list_mutex); + return pctldev; - pctldev->p = pinctrl_get(pctldev->dev); +out_err: + mutex_destroy(&pctldev->mutex); + kfree(pctldev); + return ERR_PTR(ret); +} +static int pinctrl_create_and_start(struct pinctrl_dev *pctldev) +{ + pctldev->p = create_pinctrl(pctldev->dev, pctldev); if (!IS_ERR(pctldev->p)) { + kref_get(&pctldev->p->users); pctldev->hog_default = pinctrl_lookup_state(pctldev->p, PINCTRL_STATE_DEFAULT); if (IS_ERR(pctldev->hog_default)) { - dev_dbg(dev, "failed to lookup the default state\n"); + dev_dbg(pctldev->dev, + "failed to lookup the default state\n"); } else { if (pinctrl_select_state(pctldev->p, pctldev->hog_default)) - dev_err(dev, + dev_err(pctldev->dev, "failed to select default state\n"); } @@ -1851,20 +2031,85 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, pinctrl_lookup_state(pctldev->p, PINCTRL_STATE_SLEEP); if (IS_ERR(pctldev->hog_sleep)) - dev_dbg(dev, "failed to lookup the sleep state\n"); + dev_dbg(pctldev->dev, + "failed to lookup the sleep state\n"); } + mutex_lock(&pinctrldev_list_mutex); + list_add_tail(&pctldev->node, &pinctrldev_list); + mutex_unlock(&pinctrldev_list_mutex); + pinctrl_init_device_debugfs(pctldev); + return 0; +} + +/** + * pinctrl_register() - register a pin controller device + * @pctldesc: descriptor for this pin controller + * @dev: parent device for this pin controller + * @driver_data: private pin controller data for this pin controller + * + * Note that pinctrl_register() is known to have problems as the pin + * controller driver functions are called before the driver has a + * struct pinctrl_dev handle. To avoid issues later on, please use the + * new pinctrl_register_and_init() below instead. + */ +struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, + struct device *dev, void *driver_data) +{ + struct pinctrl_dev *pctldev; + int error; + + pctldev = pinctrl_init_controller(pctldesc, dev, driver_data); + if (IS_ERR(pctldev)) + return pctldev; + + error = pinctrl_create_and_start(pctldev); + if (error) { + mutex_destroy(&pctldev->mutex); + kfree(pctldev); + + return ERR_PTR(error); + } + return pctldev; -out_err: - mutex_destroy(&pctldev->mutex); - kfree(pctldev); - return ERR_PTR(ret); } EXPORT_SYMBOL_GPL(pinctrl_register); +int pinctrl_register_and_init(struct pinctrl_desc *pctldesc, + struct device *dev, void *driver_data, + struct pinctrl_dev **pctldev) +{ + struct pinctrl_dev *p; + int error; + + p = pinctrl_init_controller(pctldesc, dev, driver_data); + if (IS_ERR(p)) + return PTR_ERR(p); + + /* + * We have pinctrl_start() call functions in the pin controller + * driver with create_pinctrl() for at least dt_node_to_map(). So + * let's make sure pctldev is properly initialized for the + * pin controller driver before we do anything. + */ + *pctldev = p; + + error = pinctrl_create_and_start(p); + if (error) { + mutex_destroy(&p->mutex); + kfree(p); + *pctldev = NULL; + + return error; + } + + return 0; +} +EXPORT_SYMBOL_GPL(pinctrl_register_and_init); + /** * pinctrl_unregister() - unregister pinmux * @pctldev: pin controller to unregister @@ -1874,6 +2119,7 @@ EXPORT_SYMBOL_GPL(pinctrl_register); void pinctrl_unregister(struct pinctrl_dev *pctldev) { struct pinctrl_gpio_range *range, *n; + if (pctldev == NULL) return; @@ -1881,13 +2127,15 @@ void pinctrl_unregister(struct pinctrl_dev *pctldev) pinctrl_remove_device_debugfs(pctldev); mutex_unlock(&pctldev->mutex); - if (!IS_ERR(pctldev->p)) + if (!IS_ERR_OR_NULL(pctldev->p)) pinctrl_put(pctldev->p); mutex_lock(&pinctrldev_list_mutex); mutex_lock(&pctldev->mutex); /* TODO: check that no pinmuxes are still active? */ list_del(&pctldev->node); + pinmux_generic_free_functions(pctldev); + pinctrl_generic_free_groups(pctldev); /* Destroy descriptor tree */ pinctrl_free_pindescs(pctldev, pctldev->desc->pins, pctldev->desc->npins); @@ -1954,6 +2202,42 @@ struct pinctrl_dev *devm_pinctrl_register(struct device *dev, EXPORT_SYMBOL_GPL(devm_pinctrl_register); /** + * devm_pinctrl_register_and_init() - Resource managed pinctrl register and init + * @dev: parent device for this pin controller + * @pctldesc: descriptor for this pin controller + * @driver_data: private pin controller data for this pin controller + * + * Returns an error pointer if pincontrol register failed. Otherwise + * it returns valid pinctrl handle. + * + * The pinctrl device will be automatically released when the device is unbound. + */ +int devm_pinctrl_register_and_init(struct device *dev, + struct pinctrl_desc *pctldesc, + void *driver_data, + struct pinctrl_dev **pctldev) +{ + struct pinctrl_dev **ptr; + int error; + + ptr = devres_alloc(devm_pinctrl_dev_release, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return -ENOMEM; + + error = pinctrl_register_and_init(pctldesc, dev, driver_data, pctldev); + if (error) { + devres_free(ptr); + return error; + } + + *ptr = *pctldev; + devres_add(dev, ptr); + + return 0; +} +EXPORT_SYMBOL_GPL(devm_pinctrl_register_and_init); + +/** * devm_pinctrl_unregister() - Resource managed version of pinctrl_unregister(). * @dev: device for which which resource was allocated * @pctldev: the pinctrl device to unregister. diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 747c423c11f3..1c35de59a658 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -24,6 +24,10 @@ struct pinctrl_gpio_range; * controller * @pin_desc_tree: each pin descriptor for this pin controller is stored in * this radix tree + * @pin_group_tree: optionally each pin group can be stored in this radix tree + * @num_groups: optionally number of groups can be kept here + * @pin_function_tree: optionally each function can be stored in this radix tree + * @num_functions: optionally number of functions can be kept here * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller, * ranges are added to this list at runtime * @dev: the device entry for this pin controller @@ -40,6 +44,14 @@ struct pinctrl_dev { struct list_head node; struct pinctrl_desc *desc; struct radix_tree_root pin_desc_tree; +#ifdef CONFIG_GENERIC_PINCTRL_GROUPS + struct radix_tree_root pin_group_tree; + unsigned int num_groups; +#endif +#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS + struct radix_tree_root pin_function_tree; + unsigned int num_functions; +#endif struct list_head gpio_ranges; struct device *dev; struct module *owner; @@ -171,6 +183,49 @@ struct pinctrl_maps { unsigned num_maps; }; +#ifdef CONFIG_GENERIC_PINCTRL_GROUPS + +/** + * struct group_desc - generic pin group descriptor + * @name: name of the pin group + * @pins: array of pins that belong to the group + * @num_pins: number of pins in the group + * @data: pin controller driver specific data + */ +struct group_desc { + const char *name; + int *pins; + int num_pins; + void *data; +}; + +int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev); + +const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group_selector); + +int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group_selector, + const unsigned int **pins, + unsigned int *npins); + +struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev, + unsigned int group_selector); + +int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name, + int *gpins, int ngpins, void *data); + +int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev, + unsigned int group_selector); + +static inline int +pinctrl_generic_remove_last_group(struct pinctrl_dev *pctldev) +{ + return pinctrl_generic_remove_group(pctldev, pctldev->num_groups - 1); +} + +#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */ + struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np); int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 260908480075..0e5c9f14a706 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -42,7 +42,8 @@ static void dt_free_map(struct pinctrl_dev *pctldev, { if (pctldev) { const struct pinctrl_ops *ops = pctldev->desc->pctlops; - ops->dt_free_map(pctldev, map, num_maps); + if (ops->dt_free_map) + ops->dt_free_map(pctldev, map, num_maps); } else { /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ kfree(map); @@ -100,11 +101,12 @@ struct pinctrl_dev *of_pinctrl_get(struct device_node *np) return get_pinctrl_dev_from_of_node(np); } -static int dt_to_map_one_config(struct pinctrl *p, const char *statename, +static int dt_to_map_one_config(struct pinctrl *p, + struct pinctrl_dev *pctldev, + const char *statename, struct device_node *np_config) { struct device_node *np_pctldev; - struct pinctrl_dev *pctldev; const struct pinctrl_ops *ops; int ret; struct pinctrl_map *map; @@ -121,7 +123,8 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename, /* OK let's just assume this will appear later then */ return -EPROBE_DEFER; } - pctldev = get_pinctrl_dev_from_of_node(np_pctldev); + if (!pctldev) + pctldev = get_pinctrl_dev_from_of_node(np_pctldev); if (pctldev) break; /* Do not defer probing of hogs (circular loop) */ @@ -166,7 +169,22 @@ static int dt_remember_dummy_state(struct pinctrl *p, const char *statename) return dt_remember_or_free_map(p, statename, NULL, map, 1); } -int pinctrl_dt_to_map(struct pinctrl *p) +bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev) +{ + struct device_node *np; + struct property *prop; + int size; + + np = pctldev->dev->of_node; + if (!np) + return false; + + prop = of_find_property(np, "pinctrl-0", &size); + + return prop ? true : false; +} + +int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev) { struct device_node *np = p->dev->of_node; int state, ret; @@ -233,7 +251,8 @@ int pinctrl_dt_to_map(struct pinctrl *p) } /* Parse the node */ - ret = dt_to_map_one_config(p, statename, np_config); + ret = dt_to_map_one_config(p, pctldev, statename, + np_config); of_node_put(np_config); if (ret < 0) goto err; diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h index c2d1a5505850..43d8d19aa5ee 100644 --- a/drivers/pinctrl/devicetree.h +++ b/drivers/pinctrl/devicetree.h @@ -20,8 +20,10 @@ struct of_phandle_args; #ifdef CONFIG_OF +bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev); + void pinctrl_dt_free_maps(struct pinctrl *p); -int pinctrl_dt_to_map(struct pinctrl *p); +int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev); int pinctrl_count_index_with_args(const struct device_node *np, const char *list_name); @@ -32,7 +34,13 @@ int pinctrl_parse_index_with_args(const struct device_node *np, #else -static inline int pinctrl_dt_to_map(struct pinctrl *p) +static inline bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev) +{ + return false; +} + +static inline int pinctrl_dt_to_map(struct pinctrl *p, + struct pinctrl_dev *pctldev) { return 0; } diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index fc8cbf611723..cae05e76c111 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -1,6 +1,7 @@ config PINCTRL_IMX bool - select PINMUX + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS select PINCONF select REGMAP diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 5ef7e875b50e..a7ace9e1ad81 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -27,6 +27,7 @@ #include <linux/regmap.h> #include "../core.h" +#include "../pinmux.h" #include "pinctrl-imx.h" /* The bits in CONFIG cell defined in binding doc*/ @@ -42,59 +43,25 @@ struct imx_pinctrl { struct pinctrl_dev *pctl; void __iomem *base; void __iomem *input_sel_base; - const struct imx_pinctrl_soc_info *info; + struct imx_pinctrl_soc_info *info; }; -static inline const struct imx_pin_group *imx_pinctrl_find_group_by_name( - const struct imx_pinctrl_soc_info *info, +static inline const struct group_desc *imx_pinctrl_find_group_by_name( + struct pinctrl_dev *pctldev, const char *name) { - const struct imx_pin_group *grp = NULL; + const struct group_desc *grp = NULL; int i; - for (i = 0; i < info->ngroups; i++) { - if (!strcmp(info->groups[i].name, name)) { - grp = &info->groups[i]; + for (i = 0; i < pctldev->num_groups; i++) { + grp = pinctrl_generic_get_group(pctldev, i); + if (grp && !strcmp(grp->name, name)) break; - } } return grp; } -static int imx_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->ngroups; -} - -static const char *imx_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->groups[selector].name; -} - -static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *npins) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - if (selector >= info->ngroups) - return -EINVAL; - - *pins = info->groups[selector].pin_ids; - *npins = info->groups[selector].npins; - - return 0; -} - static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset) { @@ -106,8 +73,8 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, struct pinctrl_map **map, unsigned *num_maps) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_group *grp; + struct imx_pinctrl_soc_info *info = ipctl->info; + const struct group_desc *grp; struct pinctrl_map *new_map; struct device_node *parent; int map_num = 1; @@ -117,15 +84,17 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, * first find the group of this node and check if we need create * config maps for pins */ - grp = imx_pinctrl_find_group_by_name(info, np->name); + grp = imx_pinctrl_find_group_by_name(pctldev, np->name); if (!grp) { dev_err(info->dev, "unable to find group for node %s\n", np->name); return -EINVAL; } - for (i = 0; i < grp->npins; i++) { - if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) + for (i = 0; i < grp->num_pins; i++) { + struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; + + if (!(pin->config & IMX_NO_PAD_CTL)) map_num++; } @@ -149,12 +118,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, /* create config map */ new_map++; - for (i = j = 0; i < grp->npins; i++) { - if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { + for (i = j = 0; i < grp->num_pins; i++) { + struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; + + if (!(pin->config & IMX_NO_PAD_CTL)) { new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; new_map[j].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i].pin); - new_map[j].data.configs.configs = &grp->pins[i].config; + pin_get_name(pctldev, pin->pin); + new_map[j].data.configs.configs = &pin->config; new_map[j].data.configs.num_configs = 1; j++; } @@ -173,9 +144,9 @@ static void imx_dt_free_map(struct pinctrl_dev *pctldev, } static const struct pinctrl_ops imx_pctrl_ops = { - .get_groups_count = imx_get_groups_count, - .get_group_name = imx_get_group_name, - .get_group_pins = imx_get_group_pins, + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, .pin_dbg_show = imx_pin_dbg_show, .dt_node_to_map = imx_dt_node_to_map, .dt_free_map = imx_dt_free_map, @@ -186,24 +157,33 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg; unsigned int npins, pin_id; int i; - struct imx_pin_group *grp; + struct group_desc *grp = NULL; + struct function_desc *func = NULL; /* * Configure the mux mode for each pin in the group for a specific * function. */ - grp = &info->groups[group]; - npins = grp->npins; + grp = pinctrl_generic_get_group(pctldev, group); + if (!grp) + return -EINVAL; + + func = pinmux_generic_get_function(pctldev, selector); + if (!func) + return -EINVAL; + + npins = grp->num_pins; dev_dbg(ipctl->dev, "enable function %s group %s\n", - info->functions[selector].name, grp->name); + func->name, grp->name); for (i = 0; i < npins; i++) { - struct imx_pin *pin = &grp->pins[i]; + struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; + pin_id = pin->pin; pin_reg = &info->pin_regs[pin_id]; @@ -272,43 +252,13 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->nfunctions; -} - -static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->functions[selector].name; -} - -static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].num_groups; - - return 0; -} - static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg; - struct imx_pin_group *grp; + struct group_desc *grp; struct imx_pin *imx_pin; unsigned int pin, group; u32 reg; @@ -322,10 +272,12 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, return -EINVAL; /* Find the pinctrl config with GPIO mux mode for the requested pin */ - for (group = 0; group < info->ngroups; group++) { - grp = &info->groups[group]; - for (pin = 0; pin < grp->npins; pin++) { - imx_pin = &grp->pins[pin]; + for (group = 0; group < pctldev->num_groups; group++) { + grp = pinctrl_generic_get_group(pctldev, group); + if (!grp) + continue; + for (pin = 0; pin < grp->num_pins; pin++) { + imx_pin = &((struct imx_pin *)(grp->data))[pin]; if (imx_pin->pin == offset && !imx_pin->mux_mode) goto mux_pin; } @@ -346,7 +298,7 @@ static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg; u32 reg; @@ -371,7 +323,7 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool input) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg; u32 reg; @@ -398,9 +350,9 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, } static const struct pinmux_ops imx_pmx_ops = { - .get_functions_count = imx_pmx_get_funcs_count, - .get_function_name = imx_pmx_get_func_name, - .get_function_groups = imx_pmx_get_groups, + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, .set_mux = imx_pmx_set, .gpio_request_enable = imx_pmx_gpio_request_enable, .gpio_disable_free = imx_pmx_gpio_disable_free, @@ -411,7 +363,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; if (pin_reg->conf_reg == -1) { @@ -433,7 +385,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, unsigned num_configs) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; int i; @@ -467,7 +419,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pinctrl_soc_info *info = ipctl->info; const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; unsigned long config; @@ -483,20 +435,22 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned group) { - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - struct imx_pin_group *grp; + struct group_desc *grp; unsigned long config; const char *name; int i, ret; - if (group > info->ngroups) + if (group > pctldev->num_groups) return; seq_printf(s, "\n"); - grp = &info->groups[group]; - for (i = 0; i < grp->npins; i++) { - struct imx_pin *pin = &grp->pins[i]; + grp = pinctrl_generic_get_group(pctldev, group); + if (!grp) + return; + + for (i = 0; i < grp->num_pins; i++) { + struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; + name = pin_get_name(pctldev, pin->pin); ret = imx_pinconf_get(pctldev, pin->pin, &config); if (ret) @@ -520,7 +474,7 @@ static const struct pinconf_ops imx_pinconf_ops = { #define SHARE_FSL_PIN_SIZE 20 static int imx_pinctrl_parse_groups(struct device_node *np, - struct imx_pin_group *grp, + struct group_desc *grp, struct imx_pinctrl_soc_info *info, u32 index) { @@ -554,20 +508,20 @@ static int imx_pinctrl_parse_groups(struct device_node *np, return -EINVAL; } - grp->npins = size / pin_size; - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), - GFP_KERNEL); - grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - if (!grp->pins || ! grp->pin_ids) + grp->num_pins = size / pin_size; + grp->data = devm_kzalloc(info->dev, grp->num_pins * + sizeof(struct imx_pin), GFP_KERNEL); + grp->pins = devm_kzalloc(info->dev, grp->num_pins * + sizeof(unsigned int), GFP_KERNEL); + if (!grp->pins || !grp->data) return -ENOMEM; - for (i = 0; i < grp->npins; i++) { + for (i = 0; i < grp->num_pins; i++) { u32 mux_reg = be32_to_cpu(*list++); u32 conf_reg; unsigned int pin_id; struct imx_pin_reg *pin_reg; - struct imx_pin *pin = &grp->pins[i]; + struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) mux_reg = -1; @@ -583,7 +537,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; pin_reg = &info->pin_regs[pin_id]; pin->pin = pin_id; - grp->pin_ids[i] = pin_id; + grp->pins[i] = pin_id; pin_reg->mux_reg = mux_reg; pin_reg->conf_reg = conf_reg; pin->input_reg = be32_to_cpu(*list++); @@ -604,31 +558,46 @@ static int imx_pinctrl_parse_groups(struct device_node *np, } static int imx_pinctrl_parse_functions(struct device_node *np, - struct imx_pinctrl_soc_info *info, + struct imx_pinctrl *ipctl, u32 index) { + struct pinctrl_dev *pctl = ipctl->pctl; + struct imx_pinctrl_soc_info *info = ipctl->info; struct device_node *child; - struct imx_pmx_func *func; - struct imx_pin_group *grp; + struct function_desc *func; + struct group_desc *grp; u32 i = 0; dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); - func = &info->functions[index]; + func = pinmux_generic_get_function(pctl, index); + if (!func) + return -EINVAL; /* Initialise function */ func->name = np->name; - func->num_groups = of_get_child_count(np); - if (func->num_groups == 0) { + func->num_group_names = of_get_child_count(np); + if (func->num_group_names == 0) { dev_err(info->dev, "no groups defined in %s\n", np->full_name); return -EINVAL; } - func->groups = devm_kzalloc(info->dev, - func->num_groups * sizeof(char *), GFP_KERNEL); + func->group_names = devm_kzalloc(info->dev, + func->num_group_names * + sizeof(char *), GFP_KERNEL); for_each_child_of_node(np, child) { - func->groups[i] = child->name; - grp = &info->groups[info->group_index++]; + func->group_names[i] = child->name; + + grp = devm_kzalloc(info->dev, sizeof(struct group_desc), + GFP_KERNEL); + if (!grp) + return -ENOMEM; + + mutex_lock(&info->mutex); + radix_tree_insert(&pctl->pin_group_tree, + info->group_index++, grp); + mutex_unlock(&info->mutex); + imx_pinctrl_parse_groups(child, grp, info, i++); } @@ -659,10 +628,12 @@ static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) } static int imx_pinctrl_probe_dt(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info) + struct imx_pinctrl *ipctl) { struct device_node *np = pdev->dev.of_node; struct device_node *child; + struct pinctrl_dev *pctl = ipctl->pctl; + struct imx_pinctrl_soc_info *info = ipctl->info; u32 nfuncs = 0; u32 i = 0; bool flat_funcs; @@ -681,35 +652,50 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, } } - info->nfunctions = nfuncs; - info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), + for (i = 0; i < nfuncs; i++) { + struct function_desc *function; + + function = devm_kzalloc(&pdev->dev, sizeof(*function), GFP_KERNEL); - if (!info->functions) - return -ENOMEM; + if (!function) + return -ENOMEM; + + mutex_lock(&info->mutex); + radix_tree_insert(&pctl->pin_function_tree, i, function); + mutex_unlock(&info->mutex); + } + pctl->num_functions = nfuncs; info->group_index = 0; if (flat_funcs) { - info->ngroups = of_get_child_count(np); + pctl->num_groups = of_get_child_count(np); } else { - info->ngroups = 0; + pctl->num_groups = 0; for_each_child_of_node(np, child) - info->ngroups += of_get_child_count(child); + pctl->num_groups += of_get_child_count(child); } - info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), - GFP_KERNEL); - if (!info->groups) - return -ENOMEM; if (flat_funcs) { - imx_pinctrl_parse_functions(np, info, 0); + imx_pinctrl_parse_functions(np, ipctl, 0); } else { + i = 0; for_each_child_of_node(np, child) - imx_pinctrl_parse_functions(child, info, i++); + imx_pinctrl_parse_functions(child, ipctl, i++); } return 0; } +/* + * imx_free_resources() - free memory used by this driver + * @info: info driver instance + */ +static void imx_free_resources(struct imx_pinctrl *ipctl) +{ + if (ipctl->pctl) + pinctrl_unregister(ipctl->pctl); +} + int imx_pinctrl_probe(struct platform_device *pdev, struct imx_pinctrl_soc_info *info) { @@ -783,23 +769,31 @@ int imx_pinctrl_probe(struct platform_device *pdev, imx_pinctrl_desc->confops = &imx_pinconf_ops; imx_pinctrl_desc->owner = THIS_MODULE; - ret = imx_pinctrl_probe_dt(pdev, info); - if (ret) { - dev_err(&pdev->dev, "fail to probe dt properties\n"); - return ret; - } + mutex_init(&info->mutex); ipctl->info = info; ipctl->dev = info->dev; platform_set_drvdata(pdev, ipctl); - ipctl->pctl = devm_pinctrl_register(&pdev->dev, - imx_pinctrl_desc, ipctl); - if (IS_ERR(ipctl->pctl)) { + ret = devm_pinctrl_register_and_init(&pdev->dev, + imx_pinctrl_desc, ipctl, + &ipctl->pctl); + if (ret) { dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - return PTR_ERR(ipctl->pctl); + goto free; + } + + ret = imx_pinctrl_probe_dt(pdev, ipctl); + if (ret) { + dev_err(&pdev->dev, "fail to probe dt properties\n"); + goto free; } dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); return 0; + +free: + imx_free_resources(ipctl); + + return ret; } diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 8af8aa2897ab..ff2d3e56b7c5 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -18,7 +18,7 @@ struct platform_device; /** - * struct imx_pin_group - describes a single i.MX pin + * struct imx_pin - describes a single i.MX pin * @pin: the pin_id of this pin * @mux_mode: the mux mode for this pin. * @input_reg: the select input register offset for this pin if any @@ -35,33 +35,6 @@ struct imx_pin { }; /** - * struct imx_pin_group - describes an IMX pin group - * @name: the name of this specific pin group - * @npins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array - * @pins: array of pins - */ -struct imx_pin_group { - const char *name; - unsigned npins; - unsigned int *pin_ids; - struct imx_pin *pins; -}; - -/** - * struct imx_pmx_func - describes IMX pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @num_groups: the number of groups - */ -struct imx_pmx_func { - const char *name; - const char **groups; - unsigned num_groups; -}; - -/** * struct imx_pin_reg - describe a pin reg map * @mux_reg: mux register offset * @conf_reg: config register offset @@ -76,13 +49,10 @@ struct imx_pinctrl_soc_info { const struct pinctrl_pin_desc *pins; unsigned int npins; struct imx_pin_reg *pin_regs; - struct imx_pin_group *groups; - unsigned int ngroups; unsigned int group_index; - struct imx_pmx_func *functions; - unsigned int nfunctions; unsigned int flags; const char *gpr_compatible; + struct mutex mutex; }; #define SHARE_MUX_CONF_REG 0x1 diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 00fb055a4897..396830a41127 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -56,6 +56,14 @@ config PINCTRL_BROXTON Broxton pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. +config PINCTRL_GEMINILAKE + tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Gemini Lake SoC pins and using them as GPIOs. + config PINCTRL_SUNRISEPOINT tristate "Intel Sunrisepoint pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 30803078f09e..12f3af5b2ca5 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o +obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index d94aef17348b..fa3c5758ac67 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1466,7 +1466,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) val & BYT_INPUT_EN ? " " : "in", val & BYT_OUTPUT_EN ? " " : "out", val & BYT_LEVEL ? "hi" : "lo", - comm->pad_map[i], comm->pad_map[i] * 32, + comm->pad_map[i], comm->pad_map[i] * 16, conf0 & 0x7, conf0 & BYT_TRIG_NEG ? " fall" : " ", conf0 & BYT_TRIG_POS ? " rise" : " ", @@ -1709,7 +1709,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, sizeof(*vg->saved_context), GFP_KERNEL); #endif - ret = gpiochip_add_data(gc, vg); + ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg); if (ret) { dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n"); return ret; @@ -1719,7 +1719,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) 0, 0, vg->soc_data->npins); if (ret) { dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n"); - goto fail; + return ret; } /* set up interrupts */ @@ -1730,7 +1730,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) handle_bad_irq, IRQ_TYPE_NONE); if (ret) { dev_err(&vg->pdev->dev, "failed to add irqchip\n"); - goto fail; + return ret; } gpiochip_set_chained_irqchip(gc, &byt_irqchip, @@ -1739,11 +1739,6 @@ static int byt_gpio_probe(struct byt_gpio *vg) } return ret; - -fail: - gpiochip_remove(&vg->chip); - - return ret; } static int byt_set_soc_data(struct byt_gpio *vg, @@ -1826,7 +1821,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) vg->pctl_desc.pins = vg->soc_data->pins; vg->pctl_desc.npins = vg->soc_data->npins; - vg->pctl_dev = pinctrl_register(&vg->pctl_desc, &pdev->dev, vg); + vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg); if (IS_ERR(vg->pctl_dev)) { dev_err(&pdev->dev, "failed to register pinctrl driver\n"); return PTR_ERR(vg->pctl_dev); @@ -1835,10 +1830,8 @@ static int byt_pinctrl_probe(struct platform_device *pdev) raw_spin_lock_init(&vg->lock); ret = byt_gpio_probe(vg); - if (ret) { - pinctrl_unregister(vg->pctl_dev); + if (ret) return ret; - } platform_set_drvdata(pdev, vg); pm_runtime_enable(&pdev->dev); diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index 901b356b09d7..e6e6fd112585 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -1004,8 +1004,8 @@ static const struct acpi_device_id bxt_pinctrl_acpi_match[] = { MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match); static const struct platform_device_id bxt_pinctrl_platform_ids[] = { - { "apl-pinctrl", (kernel_ulong_t)&apl_pinctrl_soc_data }, - { "broxton-pinctrl", (kernel_ulong_t)&bxt_pinctrl_soc_data }, + { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data }, + { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data }, { }, }; @@ -1058,7 +1058,6 @@ static const struct dev_pm_ops bxt_pinctrl_pm_ops = { static struct platform_driver bxt_pinctrl_driver = { .probe = bxt_pinctrl_probe, - .remove = intel_pinctrl_remove, .driver = { .name = "broxton-pinctrl", .acpi_match_table = bxt_pinctrl_acpi_match, diff --git a/drivers/pinctrl/intel/pinctrl-geminilake.c b/drivers/pinctrl/intel/pinctrl-geminilake.c new file mode 100644 index 000000000000..a6b94c930007 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-geminilake.c @@ -0,0 +1,512 @@ +/* + * Intel Gemini Lake SoC pinctrl/GPIO driver + * + * Copyright (C) 2017 Intel Corporation + * Author: Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/acpi.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define GLK_PAD_OWN 0x020 +#define GLK_HOSTSW_OWN 0x0b0 +#define GLK_PADCFGLOCK 0x080 +#define GLK_GPI_IE 0x110 + +#define GLK_COMMUNITY(s, e) \ + { \ + .padown_offset = GLK_PAD_OWN, \ + .padcfglock_offset = GLK_PADCFGLOCK, \ + .hostown_offset = GLK_HOSTSW_OWN, \ + .ie_offset = GLK_GPI_IE, \ + .gpp_size = 32, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + } + +/* GLK */ +static const struct pinctrl_pin_desc glk_northwest_pins[] = { + PINCTRL_PIN(0, "TCK"), + PINCTRL_PIN(1, "TRST_B"), + PINCTRL_PIN(2, "TMS"), + PINCTRL_PIN(3, "TDI"), + PINCTRL_PIN(4, "TDO"), + PINCTRL_PIN(5, "JTAGX"), + PINCTRL_PIN(6, "CX_PREQ_B"), + PINCTRL_PIN(7, "CX_PRDY_B"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GP_INTD_DSI_TE1"), + PINCTRL_PIN(43, "GP_INTD_DSI_TE2"), + PINCTRL_PIN(44, "USB_OC0_B"), + PINCTRL_PIN(45, "USB_OC1_B"), + PINCTRL_PIN(46, "DSI_I2C_SDA"), + PINCTRL_PIN(47, "DSI_I2C_SCL"), + PINCTRL_PIN(48, "PMC_I2C_SDA"), + PINCTRL_PIN(49, "PMC_I2C_SCL"), + PINCTRL_PIN(50, "LPSS_I2C0_SDA"), + PINCTRL_PIN(51, "LPSS_I2C0_SCL"), + PINCTRL_PIN(52, "LPSS_I2C1_SDA"), + PINCTRL_PIN(53, "LPSS_I2C1_SCL"), + PINCTRL_PIN(54, "LPSS_I2C2_SDA"), + PINCTRL_PIN(55, "LPSS_I2C2_SCL"), + PINCTRL_PIN(56, "LPSS_I2C3_SDA"), + PINCTRL_PIN(57, "LPSS_I2C3_SCL"), + PINCTRL_PIN(58, "LPSS_I2C4_SDA"), + PINCTRL_PIN(59, "LPSS_I2C4_SCL"), + PINCTRL_PIN(60, "LPSS_UART0_RXD"), + PINCTRL_PIN(61, "LPSS_UART0_TXD"), + PINCTRL_PIN(62, "LPSS_UART0_RTS_B"), + PINCTRL_PIN(63, "LPSS_UART0_CTS_B"), + PINCTRL_PIN(64, "LPSS_UART2_RXD"), + PINCTRL_PIN(65, "LPSS_UART2_TXD"), + PINCTRL_PIN(66, "LPSS_UART2_RTS_B"), + PINCTRL_PIN(67, "LPSS_UART2_CTS_B"), + PINCTRL_PIN(68, "PMC_SPI_FS0"), + PINCTRL_PIN(69, "PMC_SPI_FS1"), + PINCTRL_PIN(70, "PMC_SPI_FS2"), + PINCTRL_PIN(71, "PMC_SPI_RXD"), + PINCTRL_PIN(72, "PMC_SPI_TXD"), + PINCTRL_PIN(73, "PMC_SPI_CLK"), + PINCTRL_PIN(74, "THERMTRIP_B"), + PINCTRL_PIN(75, "PROCHOT_B"), + PINCTRL_PIN(76, "EMMC_RST_B"), + PINCTRL_PIN(77, "GPIO_212"), + PINCTRL_PIN(78, "GPIO_213"), + PINCTRL_PIN(79, "GPIO_214"), +}; + +static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 }; +static const unsigned int glk_northwest_pwm0_pins[] = { 42 }; +static const unsigned int glk_northwest_pwm1_pins[] = { 43 }; +static const unsigned int glk_northwest_pwm2_pins[] = { 44 }; +static const unsigned int glk_northwest_pwm3_pins[] = { 45 }; +static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 }; +static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 }; +static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 }; +static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 }; +static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 }; +static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 }; +static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 }; + +static const struct intel_pingroup glk_northwest_groups[] = { + PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2), + PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2), + PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2), + PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2), + PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2), + PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1), + PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1), + PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1), + PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1), + PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1), + PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1), + PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1), +}; + +static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" }; +static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" }; +static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" }; +static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" }; +static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" }; +static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" }; +static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" }; +static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" }; +static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" }; +static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" }; +static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" }; +static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" }; + +static const struct intel_function glk_northwest_functions[] = { + FUNCTION("uart1", glk_northwest_uart1_groups), + FUNCTION("pmw0", glk_northwest_pwm0_groups), + FUNCTION("pmw1", glk_northwest_pwm1_groups), + FUNCTION("pmw2", glk_northwest_pwm2_groups), + FUNCTION("pmw3", glk_northwest_pwm3_groups), + FUNCTION("i2c0", glk_northwest_i2c0_groups), + FUNCTION("i2c1", glk_northwest_i2c1_groups), + FUNCTION("i2c2", glk_northwest_i2c2_groups), + FUNCTION("i2c3", glk_northwest_i2c3_groups), + FUNCTION("i2c4", glk_northwest_i2c4_groups), + FUNCTION("uart0", glk_northwest_uart0_groups), + FUNCTION("uart2", glk_northwest_uart2_groups), +}; + +static const struct intel_community glk_northwest_communities[] = { + GLK_COMMUNITY(0, 79), +}; + +static const struct intel_pinctrl_soc_data glk_northwest_soc_data = { + .uid = "1", + .pins = glk_northwest_pins, + .npins = ARRAY_SIZE(glk_northwest_pins), + .groups = glk_northwest_groups, + .ngroups = ARRAY_SIZE(glk_northwest_groups), + .functions = glk_northwest_functions, + .nfunctions = ARRAY_SIZE(glk_northwest_functions), + .communities = glk_northwest_communities, + .ncommunities = ARRAY_SIZE(glk_northwest_communities), +}; + +static const struct pinctrl_pin_desc glk_north_pins[] = { + PINCTRL_PIN(0, "SVID0_ALERT_B"), + PINCTRL_PIN(1, "SVID0_DATA"), + PINCTRL_PIN(2, "SVID0_CLK"), + PINCTRL_PIN(3, "LPSS_SPI_0_CLK"), + PINCTRL_PIN(4, "LPSS_SPI_0_FS0"), + PINCTRL_PIN(5, "LPSS_SPI_0_FS1"), + PINCTRL_PIN(6, "LPSS_SPI_0_RXD"), + PINCTRL_PIN(7, "LPSS_SPI_0_TXD"), + PINCTRL_PIN(8, "LPSS_SPI_1_CLK"), + PINCTRL_PIN(9, "LPSS_SPI_1_FS0"), + PINCTRL_PIN(10, "LPSS_SPI_1_FS1"), + PINCTRL_PIN(11, "LPSS_SPI_1_FS2"), + PINCTRL_PIN(12, "LPSS_SPI_1_RXD"), + PINCTRL_PIN(13, "LPSS_SPI_1_TXD"), + PINCTRL_PIN(14, "FST_SPI_CS0_B"), + PINCTRL_PIN(15, "FST_SPI_CS1_B"), + PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"), + PINCTRL_PIN(17, "FST_SPI_MISO_IO1"), + PINCTRL_PIN(18, "FST_SPI_IO2"), + PINCTRL_PIN(19, "FST_SPI_IO3"), + PINCTRL_PIN(20, "FST_SPI_CLK"), + PINCTRL_PIN(21, "FST_SPI_CLK_FB"), + PINCTRL_PIN(22, "PMU_PLTRST_B"), + PINCTRL_PIN(23, "PMU_PWRBTN_B"), + PINCTRL_PIN(24, "PMU_SLP_S0_B"), + PINCTRL_PIN(25, "PMU_SLP_S3_B"), + PINCTRL_PIN(26, "PMU_SLP_S4_B"), + PINCTRL_PIN(27, "SUSPWRDNACK"), + PINCTRL_PIN(28, "EMMC_PWR_EN_B"), + PINCTRL_PIN(29, "PMU_AC_PRESENT"), + PINCTRL_PIN(30, "PMU_BATLOW_B"), + PINCTRL_PIN(31, "PMU_RESETBUTTON_B"), + PINCTRL_PIN(32, "PMU_SUSCLK"), + PINCTRL_PIN(33, "SUS_STAT_B"), + PINCTRL_PIN(34, "LPSS_I2C5_SDA"), + PINCTRL_PIN(35, "LPSS_I2C5_SCL"), + PINCTRL_PIN(36, "LPSS_I2C6_SDA"), + PINCTRL_PIN(37, "LPSS_I2C6_SCL"), + PINCTRL_PIN(38, "LPSS_I2C7_SDA"), + PINCTRL_PIN(39, "LPSS_I2C7_SCL"), + PINCTRL_PIN(40, "PCIE_WAKE0_B"), + PINCTRL_PIN(41, "PCIE_WAKE1_B"), + PINCTRL_PIN(42, "PCIE_WAKE2_B"), + PINCTRL_PIN(43, "PCIE_WAKE3_B"), + PINCTRL_PIN(44, "PCIE_CLKREQ0_B"), + PINCTRL_PIN(45, "PCIE_CLKREQ1_B"), + PINCTRL_PIN(46, "PCIE_CLKREQ2_B"), + PINCTRL_PIN(47, "PCIE_CLKREQ3_B"), + PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"), + PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"), + PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"), + PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"), + PINCTRL_PIN(52, "PANEL0_VDDEN"), + PINCTRL_PIN(53, "PANEL0_BKLTEN"), + PINCTRL_PIN(54, "PANEL0_BKLTCTL"), + PINCTRL_PIN(55, "HV_DDI0_HPD"), + PINCTRL_PIN(56, "HV_DDI1_HPD"), + PINCTRL_PIN(57, "HV_EDP_HPD"), + PINCTRL_PIN(58, "GPIO_134"), + PINCTRL_PIN(59, "GPIO_135"), + PINCTRL_PIN(60, "GPIO_136"), + PINCTRL_PIN(61, "GPIO_137"), + PINCTRL_PIN(62, "GPIO_138"), + PINCTRL_PIN(63, "GPIO_139"), + PINCTRL_PIN(64, "GPIO_140"), + PINCTRL_PIN(65, "GPIO_141"), + PINCTRL_PIN(66, "GPIO_142"), + PINCTRL_PIN(67, "GPIO_143"), + PINCTRL_PIN(68, "GPIO_144"), + PINCTRL_PIN(69, "GPIO_145"), + PINCTRL_PIN(70, "GPIO_146"), + PINCTRL_PIN(71, "LPC_ILB_SERIRQ"), + PINCTRL_PIN(72, "LPC_CLKOUT0"), + PINCTRL_PIN(73, "LPC_CLKOUT1"), + PINCTRL_PIN(74, "LPC_AD0"), + PINCTRL_PIN(75, "LPC_AD1"), + PINCTRL_PIN(76, "LPC_AD2"), + PINCTRL_PIN(77, "LPC_AD3"), + PINCTRL_PIN(78, "LPC_CLKRUNB"), + PINCTRL_PIN(79, "LPC_FRAMEB"), +}; + +static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 }; +static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 }; +static const unsigned int glk_north_i2c5_pins[] = { 34, 35 }; +static const unsigned int glk_north_i2c6_pins[] = { 36, 37 }; +static const unsigned int glk_north_i2c7_pins[] = { 38, 39 }; +static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 }; +static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 }; + +static const struct intel_pingroup glk_north_groups[] = { + PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1), + PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1), + PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1), + PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1), + PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1), + PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2), + PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2), +}; + +static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" }; +static const char * const glk_north_spi1_groups[] = { "spi1_grp" }; +static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" }; +static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" }; +static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" }; +static const char * const glk_north_uart0_groups[] = { "uart0_grp" }; + +static const struct intel_function glk_north_functions[] = { + FUNCTION("spi0", glk_north_spi0_groups), + FUNCTION("spi1", glk_north_spi1_groups), + FUNCTION("i2c5", glk_north_i2c5_groups), + FUNCTION("i2c6", glk_north_i2c6_groups), + FUNCTION("i2c7", glk_north_i2c7_groups), + FUNCTION("uart0", glk_north_uart0_groups), +}; + +static const struct intel_community glk_north_communities[] = { + GLK_COMMUNITY(0, 79), +}; + +static const struct intel_pinctrl_soc_data glk_north_soc_data = { + .uid = "2", + .pins = glk_north_pins, + .npins = ARRAY_SIZE(glk_north_pins), + .groups = glk_north_groups, + .ngroups = ARRAY_SIZE(glk_north_groups), + .functions = glk_north_functions, + .nfunctions = ARRAY_SIZE(glk_north_functions), + .communities = glk_north_communities, + .ncommunities = ARRAY_SIZE(glk_north_communities), +}; + +static const struct pinctrl_pin_desc glk_audio_pins[] = { + PINCTRL_PIN(0, "AVS_I2S0_MCLK"), + PINCTRL_PIN(1, "AVS_I2S0_BCLK"), + PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"), + PINCTRL_PIN(3, "AVS_I2S0_SDI"), + PINCTRL_PIN(4, "AVS_I2S0_SDO"), + PINCTRL_PIN(5, "AVS_I2S1_MCLK"), + PINCTRL_PIN(6, "AVS_I2S1_BCLK"), + PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"), + PINCTRL_PIN(8, "AVS_I2S1_SDI"), + PINCTRL_PIN(9, "AVS_I2S1_SDO"), + PINCTRL_PIN(10, "AVS_HDA_BCLK"), + PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"), + PINCTRL_PIN(12, "AVS_HDA_SDI"), + PINCTRL_PIN(13, "AVS_HDA_SDO"), + PINCTRL_PIN(14, "AVS_HDA_RSTB"), + PINCTRL_PIN(15, "AVS_M_CLK_A1"), + PINCTRL_PIN(16, "AVS_M_CLK_B1"), + PINCTRL_PIN(17, "AVS_M_DATA_1"), + PINCTRL_PIN(18, "AVS_M_CLK_AB2"), + PINCTRL_PIN(19, "AVS_M_DATA_2"), +}; + +static const struct intel_community glk_audio_communities[] = { + GLK_COMMUNITY(0, 19), +}; + +static const struct intel_pinctrl_soc_data glk_audio_soc_data = { + .uid = "3", + .pins = glk_audio_pins, + .npins = ARRAY_SIZE(glk_audio_pins), + .communities = glk_audio_communities, + .ncommunities = ARRAY_SIZE(glk_audio_communities), +}; + +static const struct pinctrl_pin_desc glk_scc_pins[] = { + PINCTRL_PIN(0, "SMB_ALERTB"), + PINCTRL_PIN(1, "SMB_CLK"), + PINCTRL_PIN(2, "SMB_DATA"), + PINCTRL_PIN(3, "SDCARD_LVL_WP"), + PINCTRL_PIN(4, "SDCARD_CLK"), + PINCTRL_PIN(5, "SDCARD_CLK_FB"), + PINCTRL_PIN(6, "SDCARD_D0"), + PINCTRL_PIN(7, "SDCARD_D1"), + PINCTRL_PIN(8, "SDCARD_D2"), + PINCTRL_PIN(9, "SDCARD_D3"), + PINCTRL_PIN(10, "SDCARD_CMD"), + PINCTRL_PIN(11, "SDCARD_CD_B"), + PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"), + PINCTRL_PIN(13, "GPIO_210"), + PINCTRL_PIN(14, "OSC_CLK_OUT_0"), + PINCTRL_PIN(15, "OSC_CLK_OUT_1"), + PINCTRL_PIN(16, "CNV_BRI_DT"), + PINCTRL_PIN(17, "CNV_BRI_RSP"), + PINCTRL_PIN(18, "CNV_RGI_DT"), + PINCTRL_PIN(19, "CNV_RGI_RSP"), + PINCTRL_PIN(20, "CNV_RF_RESET_B"), + PINCTRL_PIN(21, "XTAL_CLKREQ"), + PINCTRL_PIN(22, "SDIO_CLK_FB"), + PINCTRL_PIN(23, "EMMC0_CLK"), + PINCTRL_PIN(24, "EMMC0_CLK_FB"), + PINCTRL_PIN(25, "EMMC0_D0"), + PINCTRL_PIN(26, "EMMC0_D1"), + PINCTRL_PIN(27, "EMMC0_D2"), + PINCTRL_PIN(28, "EMMC0_D3"), + PINCTRL_PIN(29, "EMMC0_D4"), + PINCTRL_PIN(30, "EMMC0_D5"), + PINCTRL_PIN(31, "EMMC0_D6"), + PINCTRL_PIN(32, "EMMC0_D7"), + PINCTRL_PIN(33, "EMMC0_CMD"), + PINCTRL_PIN(34, "EMMC0_STROBE"), +}; + +static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 }; +static const unsigned int glk_scc_sdcard_pins[] = { + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, +}; +static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 }; +static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 }; +static const unsigned int glk_scc_emmc_pins[] = { + 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, +}; + +static const struct intel_pingroup glk_scc_groups[] = { + PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2), + PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1), + PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2), + PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3), + PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1), +}; + +static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" }; +static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" }; +static const char * const glk_scc_sdio_groups[] = { "sdio_grp" }; +static const char * const glk_scc_uart1_groups[] = { "uart1_grp" }; +static const char * const glk_scc_emmc_groups[] = { "emmc_grp" }; + +static const struct intel_function glk_scc_functions[] = { + FUNCTION("i2c7", glk_scc_i2c7_groups), + FUNCTION("sdcard", glk_scc_sdcard_groups), + FUNCTION("sdio", glk_scc_sdio_groups), + FUNCTION("uart1", glk_scc_uart1_groups), + FUNCTION("emmc", glk_scc_emmc_groups), +}; + +static const struct intel_community glk_scc_communities[] = { + GLK_COMMUNITY(0, 34), +}; + +static const struct intel_pinctrl_soc_data glk_scc_soc_data = { + .uid = "4", + .pins = glk_scc_pins, + .npins = ARRAY_SIZE(glk_scc_pins), + .groups = glk_scc_groups, + .ngroups = ARRAY_SIZE(glk_scc_groups), + .functions = glk_scc_functions, + .nfunctions = ARRAY_SIZE(glk_scc_functions), + .communities = glk_scc_communities, + .ncommunities = ARRAY_SIZE(glk_scc_communities), +}; + +static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = { + &glk_northwest_soc_data, + &glk_north_soc_data, + &glk_audio_soc_data, + &glk_scc_soc_data, + NULL, +}; + +static const struct acpi_device_id glk_pinctrl_acpi_match[] = { + { "INT3453" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match); + +static int glk_pinctrl_probe(struct platform_device *pdev) +{ + const struct intel_pinctrl_soc_data *soc_data = NULL; + struct acpi_device *adev; + int i; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return -ENODEV; + + for (i = 0; glk_pinctrl_soc_data[i]; i++) { + if (!strcmp(adev->pnp.unique_id, + glk_pinctrl_soc_data[i]->uid)) { + soc_data = glk_pinctrl_soc_data[i]; + break; + } + } + + if (!soc_data) + return -ENODEV; + + return intel_pinctrl_probe(pdev, soc_data); +} + +static const struct dev_pm_ops glk_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, + intel_pinctrl_resume) +}; + +static struct platform_driver glk_pinctrl_driver = { + .probe = glk_pinctrl_probe, + .driver = { + .name = "geminilake-pinctrl", + .acpi_match_table = glk_pinctrl_acpi_match, + .pm = &glk_pinctrl_pm_ops, + }, +}; + +static int __init glk_pinctrl_init(void) +{ + return platform_driver_register(&glk_pinctrl_driver); +} +subsys_initcall(glk_pinctrl_init); + +static void __exit glk_pinctrl_exit(void) +{ + platform_driver_unregister(&glk_pinctrl_driver); +} +module_exit(glk_pinctrl_exit); + +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 6df35dcb29ae..523264463d35 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -13,6 +13,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/gpio/driver.h> +#include <linux/log2.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> @@ -23,6 +24,10 @@ #include "pinctrl-intel.h" /* Offset from regs */ +#define REVID 0x000 +#define REVID_SHIFT 16 +#define REVID_MASK GENMASK(31, 16) + #define PADBAR 0x00c #define GPI_IS 0x100 #define GPI_GPE_STS 0x140 @@ -41,6 +46,7 @@ #define PADCFG0_RXEVCFG_EDGE 1 #define PADCFG0_RXEVCFG_DISABLED 2 #define PADCFG0_RXEVCFG_EDGE_BOTH 3 +#define PADCFG0_PREGFRXSEL BIT(24) #define PADCFG0_RXINV BIT(23) #define PADCFG0_GPIROUTIOXAPIC BIT(20) #define PADCFG0_GPIROUTSCI BIT(19) @@ -62,9 +68,17 @@ #define PADCFG1_TERM_5K 2 #define PADCFG1_TERM_1K 1 +#define PADCFG2 0x008 +#define PADCFG2_DEBEN BIT(0) +#define PADCFG2_DEBOUNCE_SHIFT 1 +#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) + +#define DEBOUNCE_PERIOD 31250 /* ns */ + struct intel_pad_context { u32 padcfg0; u32 padcfg1; + u32 padcfg2; }; struct intel_community_context { @@ -126,13 +140,19 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, { const struct intel_community *community; unsigned padno; + size_t nregs; community = intel_get_community(pctrl, pin); if (!community) return NULL; padno = pin_to_padno(community, pin); - return community->pad_regs + reg + padno * 8; + nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; + + if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) + return NULL; + + return community->pad_regs + reg + padno * nregs * 4; } static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) @@ -244,6 +264,7 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + void __iomem *padcfg; u32 cfg0, cfg1, mode; bool locked, acpi; @@ -263,6 +284,11 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); + /* Dump the additional PADCFG registers if available */ + padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); + if (padcfg) + seq_printf(s, " 0x%08x", readl(padcfg)); + locked = intel_pad_locked(pctrl, pin); acpi = intel_pad_acpi_mode(pctrl, pin); @@ -432,12 +458,14 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); + const struct intel_community *community; u32 value, term; - u16 arg = 0; + u32 arg = 0; if (!intel_pad_owned_by_host(pctrl, pin)) return -ENOTSUPP; + community = intel_get_community(pctrl, pin); value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; @@ -473,6 +501,11 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, return -EINVAL; switch (term) { + case PADCFG1_TERM_1K: + if (!(community->features & PINCTRL_FEATURE_1K_PD)) + return -EINVAL; + arg = 1000; + break; case PADCFG1_TERM_5K: arg = 5000; break; @@ -483,6 +516,24 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, break; + case PIN_CONFIG_INPUT_DEBOUNCE: { + void __iomem *padcfg2; + u32 v; + + padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); + if (!padcfg2) + return -ENOTSUPP; + + v = readl(padcfg2); + if (!(v & PADCFG2_DEBEN)) + return -EINVAL; + + v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; + arg = BIT(v) * DEBOUNCE_PERIOD / 1000; + + break; + } + default: return -ENOTSUPP; } @@ -496,6 +547,7 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, { unsigned param = pinconf_to_config_param(config); unsigned arg = pinconf_to_config_argument(config); + const struct intel_community *community; void __iomem *padcfg1; unsigned long flags; int ret = 0; @@ -503,6 +555,7 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, raw_spin_lock_irqsave(&pctrl->lock, flags); + community = intel_get_community(pctrl, pin); padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); value = readl(padcfg1); @@ -545,6 +598,11 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, case 5000: value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; break; + case 1000: + if (!(community->features & PINCTRL_FEATURE_1K_PD)) + return -EINVAL; + value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; + break; default: ret = -EINVAL; } @@ -560,6 +618,53 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, return ret; } +static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin, + unsigned debounce) +{ + void __iomem *padcfg0, *padcfg2; + unsigned long flags; + u32 value0, value2; + int ret = 0; + + padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); + if (!padcfg2) + return -ENOTSUPP; + + padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + value0 = readl(padcfg0); + value2 = readl(padcfg2); + + /* Disable glitch filter and debouncer */ + value0 &= ~PADCFG0_PREGFRXSEL; + value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); + + if (debounce) { + unsigned long v; + + v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); + if (v < 3 || v > 15) { + ret = -EINVAL; + goto exit_unlock; + } else { + /* Enable glitch filter and debouncer */ + value0 |= PADCFG0_PREGFRXSEL; + value2 |= v << PADCFG2_DEBOUNCE_SHIFT; + value2 |= PADCFG2_DEBEN; + } + } + + writel(value0, padcfg0); + writel(value2, padcfg2); + +exit_unlock: + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return ret; +} + static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, unsigned nconfigs) { @@ -579,6 +684,13 @@ static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, return ret; break; + case PIN_CONFIG_INPUT_DEBOUNCE: + ret = intel_config_set_debounce(pctrl, pin, + pinconf_to_config_argument(configs[i])); + if (ret) + return ret; + break; + default: return -ENOTSUPP; } @@ -653,6 +765,7 @@ static const struct gpio_chip intel_gpio_chip = { .direction_output = intel_gpio_direction_output, .get = intel_gpio_get, .set = intel_gpio_set, + .set_config = gpiochip_generic_config, }; static void intel_gpio_irq_ack(struct irq_data *d) @@ -892,7 +1005,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) pctrl->chip.base = -1; pctrl->irq = irq; - ret = gpiochip_add_data(&pctrl->chip, pctrl); + ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "failed to register gpiochip\n"); return ret; @@ -902,7 +1015,7 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 0, 0, pctrl->soc->npins); if (ret) { dev_err(pctrl->dev, "failed to add GPIO pin range\n"); - goto fail; + return ret; } /* @@ -915,24 +1028,19 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) dev_name(pctrl->dev), pctrl); if (ret) { dev_err(pctrl->dev, "failed to request interrupt\n"); - goto fail; + return ret; } ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, handle_bad_irq, IRQ_TYPE_NONE); if (ret) { dev_err(pctrl->dev, "failed to add irqchip\n"); - goto fail; + return ret; } gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, NULL); return 0; - -fail: - gpiochip_remove(&pctrl->chip); - - return ret; } static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) @@ -1013,6 +1121,20 @@ int intel_pinctrl_probe(struct platform_device *pdev, if (IS_ERR(regs)) return PTR_ERR(regs); + /* + * Determine community features based on the revision if + * not specified already. + */ + if (!community->features) { + u32 rev; + + rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; + if (rev >= 0x94) { + community->features |= PINCTRL_FEATURE_DEBOUNCE; + community->features |= PINCTRL_FEATURE_1K_PD; + } + } + /* Read offset of the pad configuration registers */ padbar = readl(regs + PADBAR); @@ -1054,16 +1176,6 @@ int intel_pinctrl_probe(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(intel_pinctrl_probe); -int intel_pinctrl_remove(struct platform_device *pdev) -{ - struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); - - gpiochip_remove(&pctrl->chip); - - return 0; -} -EXPORT_SYMBOL_GPL(intel_pinctrl_remove); - #ifdef CONFIG_PM_SLEEP static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin) { @@ -1096,6 +1208,7 @@ int intel_pinctrl_suspend(struct device *dev) pads = pctrl->context.pads; for (i = 0; i < pctrl->soc->npins; i++) { const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; + void __iomem *padcfg; u32 val; if (!intel_pinctrl_should_save(pctrl, desc->number)) @@ -1105,6 +1218,10 @@ int intel_pinctrl_suspend(struct device *dev) pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); pads[i].padcfg1 = val; + + padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); + if (padcfg) + pads[i].padcfg2 = readl(padcfg); } communities = pctrl->context.communities; @@ -1177,6 +1294,16 @@ int intel_pinctrl_resume(struct device *dev) dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", desc->number, readl(padcfg)); } + + padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); + if (padcfg) { + val = readl(padcfg); + if (val != pads[i].padcfg2) { + writel(pads[i].padcfg2, padcfg); + dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", + desc->number, readl(padcfg)); + } + } } communities = pctrl->context.communities; diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index b60215793017..fe9521f345b5 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -58,6 +58,7 @@ struct intel_function { * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * HOSTSW_OWN, GPI_IS, GPI_IE, etc. * @npins: Number of pins in this community + * @features: Additional features supported by the hardware * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * @ngpps: Number of groups (hw groups) in this community (reserved for @@ -72,11 +73,16 @@ struct intel_community { unsigned pin_base; unsigned gpp_size; size_t npins; + unsigned features; void __iomem *regs; void __iomem *pad_regs; size_t ngpps; }; +/* Additional features supported by the hardware */ +#define PINCTRL_FEATURE_DEBOUNCE BIT(0) +#define PINCTRL_FEATURE_1K_PD BIT(1) + #define PIN_GROUP(n, p, m) \ { \ .name = (n), \ @@ -121,8 +127,6 @@ struct intel_pinctrl_soc_data { int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data); -int intel_pinctrl_remove(struct platform_device *pdev); - #ifdef CONFIG_PM_SLEEP int intel_pinctrl_suspend(struct device *dev); int intel_pinctrl_resume(struct device *dev); diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index c725a5313b4e..9877526c0807 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -574,7 +574,6 @@ static const struct dev_pm_ops spt_pinctrl_pm_ops = { static struct platform_driver spt_pinctrl_driver = { .probe = spt_pinctrl_probe, - .remove = intel_pinctrl_remove, .driver = { .name = "sunrisepoint-pinctrl", .acpi_match_table = spt_pinctrl_acpi_match, diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 4f0bc8a103f4..80fe3b48796c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -10,25 +10,29 @@ config PINCTRL_MTK # For ARMv7 SoCs config PINCTRL_MT2701 - bool "Mediatek MT2701 pin control" if COMPILE_TEST && !MACH_MT2701 + bool "Mediatek MT2701 pin control" + depends on MACH_MT2701 || COMPILE_TEST depends on OF default MACH_MT2701 select PINCTRL_MTK config PINCTRL_MT7623 - bool "Mediatek MT7623 pin control" if COMPILE_TEST && !MACH_MT7623 + bool "Mediatek MT7623 pin control" + depends on MACH_MT7623 || COMPILE_TEST depends on OF default MACH_MT7623 select PINCTRL_MTK_COMMON config PINCTRL_MT8135 - bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135 + bool "Mediatek MT8135 pin control" + depends on MACH_MT8135 || COMPILE_TEST depends on OF default MACH_MT8135 select PINCTRL_MTK config PINCTRL_MT8127 - bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127 + bool "Mediatek MT8127 pin control" + depends on MACH_MT8127 || COMPILE_TEST depends on OF default MACH_MT8127 select PINCTRL_MTK @@ -43,7 +47,8 @@ config PINCTRL_MT8173 # For PMIC config PINCTRL_MT6397 - bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397 + bool "Mediatek MT6397 pin control" + depends on MFD_MT6397 || COMPILE_TEST depends on OF default MFD_MT6397 select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index 67895f8234e3..fa28dd6b871b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 John Crispin <blogic@openwrt.org> + * Copyright (c) 2016 John Crispin <john@phrozen.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h index 3472a76ad422..e06cfc40da0f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 John Crispin <blogic@openwrt.org> + * Copyright (c) 2016 John Crispin <john@phrozen.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index e0bca4df2a2f..7671424d46cb 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -232,6 +232,10 @@ static const unsigned int pwm_e_pins[] = { PIN(GPIOX_19, EE_OFF) }; static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; static const unsigned int pwm_f_y_pins[] = { PIN(GPIOY_15, EE_OFF) }; +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; + static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = { MESON_PIN(GPIOAO_0, 0), MESON_PIN(GPIOAO_1, 0), @@ -439,6 +443,11 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(eth_txd2, 6, 3), GROUP(eth_txd3, 6, 2), + /* Bank H */ + GROUP(hdmi_hpd, 1, 26), + GROUP(hdmi_sda, 1, 25), + GROUP(hdmi_scl, 1, 24), + /* Bank DV */ GROUP(uart_tx_b, 2, 29), GROUP(uart_rx_b, 2, 28), @@ -635,6 +644,14 @@ static const char * const pwm_f_y_groups[] = { "pwm_f_y", }; +static const char * const hdmi_hpd_groups[] = { + "hdmi_hpd", +}; + +static const char * const hdmi_i2c_groups[] = { + "hdmi_sda", "hdmi_scl", +}; + static const char * const gpio_aobus_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", @@ -698,6 +715,8 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(pwm_e), FUNCTION(pwm_f_x), FUNCTION(pwm_f_y), + FUNCTION(hdmi_hpd), + FUNCTION(hdmi_i2c), }; static struct meson_pmx_func meson_gxbb_aobus_functions[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index b69743b07a1d..4ab94a85e306 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -197,6 +197,10 @@ static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) }; +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; + static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = { MESON_PIN(GPIOAO_0, 0), MESON_PIN(GPIOAO_1, 0), @@ -221,6 +225,8 @@ static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; +static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) }; + static struct meson_pmx_group meson_gxl_periphs_groups[] = { GPIO_GROUP(GPIOZ_0, EE_OFF), GPIO_GROUP(GPIOZ_1, EE_OFF), @@ -362,6 +368,11 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { GROUP(eth_txd2, 4, 11), GROUP(eth_txd3, 4, 10), + /* Bank H */ + GROUP(hdmi_hpd, 6, 31), + GROUP(hdmi_sda, 6, 30), + GROUP(hdmi_scl, 6, 29), + /* Bank DV */ GROUP(uart_tx_b, 2, 16), GROUP(uart_rx_b, 2, 15), @@ -417,6 +428,7 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = { GROUP(uart_cts_ao_b, 0, 8), GROUP(uart_rts_ao_b, 0, 7), GROUP(remote_input_ao, 0, 0), + GROUP(pwm_ao_b, 0, 3), }; static const char * const gpio_periphs_groups[] = { @@ -505,6 +517,14 @@ static const char * const pwm_e_groups[] = { "pwm_e", }; +static const char * const hdmi_hpd_groups[] = { + "hdmi_hpd", +}; + +static const char * const hdmi_i2c_groups[] = { + "hdmi_sda", "hdmi_scl", +}; + static const char * const gpio_aobus_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", @@ -522,6 +542,10 @@ static const char * const remote_input_ao_groups[] = { "remote_input_ao", }; +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b", +}; + static struct meson_pmx_func meson_gxl_periphs_functions[] = { FUNCTION(gpio_periphs), FUNCTION(emmc), @@ -536,6 +560,8 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = { FUNCTION(i2c_c), FUNCTION(eth), FUNCTION(pwm_e), + FUNCTION(hdmi_hpd), + FUNCTION(hdmi_i2c), }; static struct meson_pmx_func meson_gxl_aobus_functions[] = { @@ -543,6 +569,7 @@ static struct meson_pmx_func meson_gxl_aobus_functions[] = { FUNCTION(uart_ao), FUNCTION(uart_ao_b), FUNCTION(remote_input_ao), + FUNCTION(pwm_ao_b), }; static struct meson_bank meson_gxl_periphs_banks[] = { diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c index 9cc1cc3f5c34..c2de4f8ee488 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c @@ -23,18 +23,6 @@ #include "pinctrl-mvebu.h" -static void __iomem *mpp_base; - -static int armada_370_mpp_ctrl_get(unsigned pid, unsigned long *config) -{ - return default_mpp_ctrl_get(mpp_base, pid, config); -} - -static int armada_370_mpp_ctrl_set(unsigned pid, unsigned long config) -{ - return default_mpp_ctrl_set(mpp_base, pid, config); -} - static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { MPP_MODE(0, MPP_FUNCTION(0x0, "gpio", NULL), @@ -384,8 +372,8 @@ static const struct of_device_id armada_370_pinctrl_of_match[] = { { }, }; -static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = { - MPP_FUNC_CTRL(0, 65, NULL, armada_370_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = { + MPP_FUNC_CTRL(0, 65, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = { @@ -397,12 +385,6 @@ static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = { static int armada_370_pinctrl_probe(struct platform_device *pdev) { struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info; - struct resource *res; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); soc->variant = 0; /* no variants for Armada 370 */ soc->controls = mv88f6710_mpp_controls; @@ -414,7 +396,7 @@ static int armada_370_pinctrl_probe(struct platform_device *pdev) pdev->dev.platform_data = soc; - return mvebu_pinctrl_probe(pdev); + return mvebu_pinctrl_simple_mmio_probe(pdev); } static struct platform_driver armada_370_pinctrl_driver = { diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index 070651431ca4..30cbf23b0b03 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -23,18 +23,6 @@ #include "pinctrl-mvebu.h" -static void __iomem *mpp_base; - -static int armada_375_mpp_ctrl_get(unsigned pid, unsigned long *config) -{ - return default_mpp_ctrl_get(mpp_base, pid, config); -} - -static int armada_375_mpp_ctrl_set(unsigned pid, unsigned long config) -{ - return default_mpp_ctrl_set(mpp_base, pid, config); -} - static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_MODE(0, MPP_FUNCTION(0x0, "gpio", NULL), @@ -402,8 +390,8 @@ static const struct of_device_id armada_375_pinctrl_of_match[] = { { }, }; -static struct mvebu_mpp_ctrl mv88f6720_mpp_controls[] = { - MPP_FUNC_CTRL(0, 69, NULL, armada_375_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv88f6720_mpp_controls[] = { + MPP_FUNC_CTRL(0, 69, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f6720_mpp_gpio_ranges[] = { @@ -415,12 +403,6 @@ static struct pinctrl_gpio_range mv88f6720_mpp_gpio_ranges[] = { static int armada_375_pinctrl_probe(struct platform_device *pdev) { struct mvebu_pinctrl_soc_info *soc = &armada_375_pinctrl_info; - struct resource *res; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); soc->variant = 0; /* no variants for Armada 375 */ soc->controls = mv88f6720_mpp_controls; @@ -432,7 +414,7 @@ static int armada_375_pinctrl_probe(struct platform_device *pdev) pdev->dev.platform_data = soc; - return mvebu_pinctrl_probe(pdev); + return mvebu_pinctrl_simple_mmio_probe(pdev); } static struct platform_driver armada_375_pinctrl_driver = { diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 4e84c8e4938c..e66ed239522e 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -22,18 +22,6 @@ #include "pinctrl-mvebu.h" -static void __iomem *mpp_base; - -static int armada_38x_mpp_ctrl_get(unsigned pid, unsigned long *config) -{ - return default_mpp_ctrl_get(mpp_base, pid, config); -} - -static int armada_38x_mpp_ctrl_set(unsigned pid, unsigned long config) -{ - return default_mpp_ctrl_set(mpp_base, pid, config); -} - enum { V_88F6810 = BIT(0), V_88F6820 = BIT(1), @@ -409,8 +397,8 @@ static const struct of_device_id armada_38x_pinctrl_of_match[] = { { }, }; -static struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = { - MPP_FUNC_CTRL(0, 59, NULL, armada_38x_mpp_ctrl), +static const struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = { + MPP_FUNC_CTRL(0, 59, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = { @@ -423,16 +411,10 @@ static int armada_38x_pinctrl_probe(struct platform_device *pdev) struct mvebu_pinctrl_soc_info *soc = &armada_38x_pinctrl_info; const struct of_device_id *match = of_match_device(armada_38x_pinctrl_of_match, &pdev->dev); - struct resource *res; if (!match) return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); - soc->variant = (unsigned) match->data & 0xff; soc->controls = armada_38x_mpp_controls; soc->ncontrols = ARRAY_SIZE(armada_38x_mpp_controls); @@ -443,7 +425,7 @@ static int armada_38x_pinctrl_probe(struct platform_device *pdev) pdev->dev.platform_data = soc; - return mvebu_pinctrl_probe(pdev); + return mvebu_pinctrl_simple_mmio_probe(pdev); } static struct platform_driver armada_38x_pinctrl_driver = { diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c index e288f8ba0bf1..697c8774a4da 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c @@ -22,18 +22,6 @@ #include "pinctrl-mvebu.h" -static void __iomem *mpp_base; - -static int armada_39x_mpp_ctrl_get(unsigned pid, unsigned long *config) -{ - return default_mpp_ctrl_get(mpp_base, pid, config); -} - -static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config) -{ - return default_mpp_ctrl_set(mpp_base, pid, config); -} - enum { V_88F6920 = BIT(0), V_88F6925 = BIT(1), @@ -391,8 +379,8 @@ static const struct of_device_id armada_39x_pinctrl_of_match[] = { { }, }; -static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = { - MPP_FUNC_CTRL(0, 59, NULL, armada_39x_mpp_ctrl), +static const struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = { + MPP_FUNC_CTRL(0, 59, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = { @@ -405,16 +393,10 @@ static int armada_39x_pinctrl_probe(struct platform_device *pdev) struct mvebu_pinctrl_soc_info *soc = &armada_39x_pinctrl_info; const struct of_device_id *match = of_match_device(armada_39x_pinctrl_of_match, &pdev->dev); - struct resource *res; if (!match) return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); - soc->variant = (unsigned) match->data & 0xff; soc->controls = armada_39x_mpp_controls; soc->ncontrols = ARRAY_SIZE(armada_39x_mpp_controls); @@ -425,7 +407,7 @@ static int armada_39x_pinctrl_probe(struct platform_device *pdev) pdev->dev.platform_data = soc; - return mvebu_pinctrl_probe(pdev); + return mvebu_pinctrl_simple_mmio_probe(pdev); } static struct platform_driver armada_39x_pinctrl_driver = { diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index e4ea71a9d985..61cbc138703e 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -30,25 +30,18 @@ #include "pinctrl-mvebu.h" -static void __iomem *mpp_base; static u32 *mpp_saved_regs; -static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config) -{ - return default_mpp_ctrl_get(mpp_base, pid, config); -} - -static int armada_xp_mpp_ctrl_set(unsigned pid, unsigned long config) -{ - return default_mpp_ctrl_set(mpp_base, pid, config); -} - enum armada_xp_variant { V_MV78230 = BIT(0), V_MV78260 = BIT(1), V_MV78460 = BIT(2), V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460), V_MV78260_PLUS = (V_MV78260 | V_MV78460), + V_98DX3236 = BIT(3), + V_98DX3336 = BIT(4), + V_98DX4251 = BIT(5), + V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251), }; static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { @@ -360,6 +353,131 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)), }; +static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { + MPP_MODE(0, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)), + MPP_MODE(1, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)), + MPP_MODE(2, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)), + MPP_MODE(3, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)), + MPP_MODE(4, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)), + MPP_MODE(5, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)), + MPP_MODE(6, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)), + MPP_MODE(7, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)), + MPP_MODE(8, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)), + MPP_MODE(9, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)), + MPP_MODE(10, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)), + MPP_MODE(11, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)), + MPP_MODE(12, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)), + MPP_MODE(18, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)), + MPP_MODE(22, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)), + MPP_MODE(23, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)), + MPP_MODE(24, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)), + MPP_MODE(26, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)), + MPP_MODE(28, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)), + MPP_MODE(29, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)), + MPP_MODE(31, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)), +}; + static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info; static const struct of_device_id armada_xp_pinctrl_of_match[] = { @@ -375,11 +493,19 @@ static const struct of_device_id armada_xp_pinctrl_of_match[] = { .compatible = "marvell,mv78460-pinctrl", .data = (void *) V_MV78460, }, + { + .compatible = "marvell,98dx3236-pinctrl", + .data = (void *) V_98DX3236, + }, + { + .compatible = "marvell,98dx4251-pinctrl", + .data = (void *) V_98DX4251, + }, { }, }; -static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = { - MPP_FUNC_CTRL(0, 48, NULL, armada_xp_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv78230_mpp_controls[] = { + MPP_FUNC_CTRL(0, 48, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = { @@ -387,8 +513,8 @@ static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(1, 32, 32, 17), }; -static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = { - MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv78260_mpp_controls[] = { + MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = { @@ -397,8 +523,8 @@ static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(2, 64, 64, 3), }; -static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = { - MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv78460_mpp_controls[] = { + MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { @@ -407,6 +533,14 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(2, 64, 64, 3), }; +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = { + MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl), +}; + +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), +}; + static int armada_xp_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) { @@ -417,7 +551,7 @@ static int armada_xp_pinctrl_suspend(struct platform_device *pdev, nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); for (i = 0; i < nregs; i++) - mpp_saved_regs[i] = readl(mpp_base + i * 4); + mpp_saved_regs[i] = readl(soc->control_data[0].base + i * 4); return 0; } @@ -431,7 +565,7 @@ static int armada_xp_pinctrl_resume(struct platform_device *pdev) nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); for (i = 0; i < nregs; i++) - writel(mpp_saved_regs[i], mpp_base + i * 4); + writel(mpp_saved_regs[i], soc->control_data[0].base + i * 4); return 0; } @@ -441,17 +575,11 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; const struct of_device_id *match = of_match_device(armada_xp_pinctrl_of_match, &pdev->dev); - struct resource *res; int nregs; if (!match) return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); - soc->variant = (unsigned) match->data & 0xff; switch (soc->variant) { @@ -488,6 +616,17 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) soc->gpioranges = mv78460_mpp_gpio_ranges; soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges); break; + case V_98DX3236: + case V_98DX3336: + case V_98DX4251: + /* fall-through */ + soc->controls = mv98dx3236_mpp_controls; + soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls); + soc->modes = mv98dx3236_mpp_modes; + soc->nmodes = mv98dx3236_mpp_controls[0].npins; + soc->gpioranges = mv98dx3236_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges); + break; } nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); @@ -499,7 +638,7 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) pdev->dev.platform_data = soc; - return mvebu_pinctrl_probe(pdev); + return mvebu_pinctrl_simple_mmio_probe(pdev); } static struct platform_driver armada_xp_pinctrl_driver = { diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index f93ae0dcef9c..89ae93c49f2f 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c @@ -61,30 +61,20 @@ #define CONFIG_PMU BIT(4) -static void __iomem *mpp_base; static void __iomem *mpp4_base; static void __iomem *pmu_base; static struct regmap *gconfmap; -static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) -{ - return default_mpp_ctrl_get(mpp_base, pid, config); -} - -static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) -{ - return default_mpp_ctrl_set(mpp_base, pid, config); -} - -static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) +static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, + unsigned pid, unsigned long *config) { unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; - unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); unsigned long func; if ((pmu & BIT(pid)) == 0) - return default_mpp_ctrl_get(mpp_base, pid, config); + return mvebu_mmio_mpp_ctrl_get(data, pid, config); func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); *config = (func >> shift) & MVEBU_MPP_MASK; @@ -93,19 +83,20 @@ static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) return 0; } -static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) +static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, + unsigned pid, unsigned long config) { unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; - unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); unsigned long func; if ((config & CONFIG_PMU) == 0) { - writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); - return default_mpp_ctrl_set(mpp_base, pid, config); + writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); + return mvebu_mmio_mpp_ctrl_set(data, pid, config); } - writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); + writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL); func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); func &= ~(MVEBU_MPP_MASK << shift); func |= (config & MVEBU_MPP_MASK) << shift; @@ -114,7 +105,8 @@ static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) return 0; } -static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) +static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config) { unsigned long mpp4 = readl(mpp4_base); unsigned long mask; @@ -144,7 +136,8 @@ static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) return 0; } -static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) +static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config) { unsigned long mpp4 = readl(mpp4_base); unsigned long mask; @@ -178,7 +171,8 @@ static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) return 0; } -static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) +static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config) { unsigned int gmpp; @@ -188,7 +182,8 @@ static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) return 0; } -static int dove_nand_ctrl_set(unsigned pid, unsigned long config) +static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config) { regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG, NAND_GPIO_EN, @@ -196,28 +191,31 @@ static int dove_nand_ctrl_set(unsigned pid, unsigned long config) return 0; } -static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) +static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config) { - unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); *config = ((pmu & AU0_AC97_SEL) != 0); return 0; } -static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) +static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config) { - unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL); pmu &= ~AU0_AC97_SEL; if (config) pmu |= AU0_AC97_SEL; - writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL); + writel(pmu, data->base + PMU_MPP_GENERAL_CTRL); return 0; } -static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) +static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config) { unsigned int mpp4 = readl(mpp4_base); unsigned int sspc1; @@ -247,7 +245,8 @@ static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) return 0; } -static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) +static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config) { unsigned int mpp4 = readl(mpp4_base); @@ -274,11 +273,12 @@ static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) * break other functions. If you require all mpps as gpio * enforce gpio setting by pinctrl mapping. */ -static int dove_audio1_ctrl_gpio_req(unsigned pid) +static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl_data *data, + unsigned pid) { unsigned long config; - dove_audio1_ctrl_get(pid, &config); + dove_audio1_ctrl_get(data, pid, &config); switch (config) { case 0x02: /* i2s1 : gpio[56:57] */ @@ -301,14 +301,16 @@ static int dove_audio1_ctrl_gpio_req(unsigned pid) } /* mpp[52:57] has gpio pins capable of in and out */ -static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input) +static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl_data *data, + unsigned pid, bool input) { if (pid < 52 || pid > 57) return -ENOTSUPP; return 0; } -static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) +static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config) { unsigned int gcfg1; unsigned int gcfg2; @@ -327,7 +329,8 @@ static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) return 0; } -static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) +static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config) { unsigned int gcfg1 = 0; unsigned int gcfg2 = 0; @@ -354,9 +357,9 @@ static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) return 0; } -static struct mvebu_mpp_ctrl dove_mpp_controls[] = { +static const struct mvebu_mpp_ctrl dove_mpp_controls[] = { MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl), - MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl), + MPP_FUNC_CTRL(16, 23, NULL, mvebu_mmio_mpp_ctrl), MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), @@ -769,6 +772,10 @@ static int dove_pinctrl_probe(struct platform_device *pdev) struct resource fb_res; const struct of_device_id *match = of_match_device(dove_pinctrl_of_match, &pdev->dev); + struct mvebu_mpp_ctrl_data *mpp_data; + void __iomem *base; + int i; + pdev->dev.platform_data = (void *)match->data; /* @@ -783,9 +790,18 @@ static int dove_pinctrl_probe(struct platform_device *pdev) clk_prepare_enable(clk); mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); + base = devm_ioremap_resource(&pdev->dev, mpp_res); + if (IS_ERR(base)) + return PTR_ERR(base); + + mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols, + sizeof(*mpp_data), GFP_KERNEL); + if (!mpp_data) + return -ENOMEM; + + dove_pinctrl_info.control_data = mpp_data; + for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++) + mpp_data[i].base = base; /* prepare fallback resource */ memcpy(&fb_res, mpp_res, sizeof(struct resource)); diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c index 5f89c26f3292..be12b6d569a0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c +++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c @@ -21,18 +21,6 @@ #include "pinctrl-mvebu.h" -static void __iomem *mpp_base; - -static int kirkwood_mpp_ctrl_get(unsigned pid, unsigned long *config) -{ - return default_mpp_ctrl_get(mpp_base, pid, config); -} - -static int kirkwood_mpp_ctrl_set(unsigned pid, unsigned long config) -{ - return default_mpp_ctrl_set(mpp_base, pid, config); -} - #define V(f6180, f6190, f6192, f6281, f6282, dx4122) \ ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \ (f6281 << 3) | (f6282 << 4) | (dx4122 << 5)) @@ -370,8 +358,8 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = { MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0))), }; -static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = { - MPP_FUNC_CTRL(0, 44, NULL, kirkwood_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = { + MPP_FUNC_CTRL(0, 44, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = { @@ -379,8 +367,8 @@ static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = { MPP_GPIO_RANGE(1, 35, 35, 10), }; -static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = { - MPP_FUNC_CTRL(0, 35, NULL, kirkwood_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = { + MPP_FUNC_CTRL(0, 35, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = { @@ -388,8 +376,8 @@ static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = { MPP_GPIO_RANGE(1, 32, 32, 4), }; -static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = { - MPP_FUNC_CTRL(0, 49, NULL, kirkwood_mpp_ctrl), +static const struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = { + MPP_FUNC_CTRL(0, 49, NULL, mvebu_mmio_mpp_ctrl), }; static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = { @@ -469,17 +457,12 @@ static const struct of_device_id kirkwood_pinctrl_of_match[] = { static int kirkwood_pinctrl_probe(struct platform_device *pdev) { - struct resource *res; const struct of_device_id *match = of_match_device(kirkwood_pinctrl_of_match, &pdev->dev); - pdev->dev.platform_data = (void *)match->data; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mpp_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(mpp_base)) - return PTR_ERR(mpp_base); + pdev->dev.platform_data = (void *)match->data; - return mvebu_pinctrl_probe(pdev); + return mvebu_pinctrl_simple_mmio_probe(pdev); } static struct platform_driver kirkwood_pinctrl_driver = { diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index b6ec6db78351..1bdfe770eb5c 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -23,6 +23,8 @@ #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> #include "pinctrl-mvebu.h" @@ -38,7 +40,8 @@ struct mvebu_pinctrl_function { struct mvebu_pinctrl_group { const char *name; - struct mvebu_mpp_ctrl *ctrl; + const struct mvebu_mpp_ctrl *ctrl; + struct mvebu_mpp_ctrl_data *data; struct mvebu_mpp_ctrl_setting *settings; unsigned num_settings; unsigned gid; @@ -57,6 +60,30 @@ struct mvebu_pinctrl { u8 variant; }; +int mvebu_mmio_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, + unsigned int pid, unsigned long *config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + + *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; + + return 0; +} + +int mvebu_mmio_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, + unsigned int pid, unsigned long config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned long reg; + + reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); + writel(reg | (config << shift), data->base + off); + + return 0; +} + static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid( struct mvebu_pinctrl *pctl, unsigned pid) { @@ -146,7 +173,7 @@ static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev, if (!grp->ctrl) return -EINVAL; - return grp->ctrl->mpp_get(grp->pins[0], config); + return grp->ctrl->mpp_get(grp->data, grp->pins[0], config); } static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev, @@ -161,7 +188,7 @@ static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev, return -EINVAL; for (i = 0; i < num_configs; i++) { - ret = grp->ctrl->mpp_set(grp->pins[0], configs[i]); + ret = grp->ctrl->mpp_set(grp->data, grp->pins[0], configs[i]); if (ret) return ret; } /* for each config */ @@ -188,18 +215,19 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, if (curr->subname) seq_printf(s, "(%s)", curr->subname); if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) { - seq_printf(s, "("); + seq_putc(s, '('); if (curr->flags & MVEBU_SETTING_GPI) - seq_printf(s, "i"); + seq_putc(s, 'i'); if (curr->flags & MVEBU_SETTING_GPO) - seq_printf(s, "o"); - seq_printf(s, ")"); + seq_putc(s, 'o'); + seq_putc(s, ')'); } - } else - seq_printf(s, "current: UNKNOWN"); + } else { + seq_puts(s, "current: UNKNOWN"); + } if (grp->num_settings > 1) { - seq_printf(s, ", available = ["); + seq_puts(s, ", available = ["); for (n = 0; n < grp->num_settings; n++) { if (curr == &grp->settings[n]) continue; @@ -214,17 +242,16 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "(%s)", grp->settings[n].subname); if (grp->settings[n].flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) { - seq_printf(s, "("); + seq_putc(s, '('); if (grp->settings[n].flags & MVEBU_SETTING_GPI) - seq_printf(s, "i"); + seq_putc(s, 'i'); if (grp->settings[n].flags & MVEBU_SETTING_GPO) - seq_printf(s, "o"); - seq_printf(s, ")"); + seq_putc(s, 'o'); + seq_putc(s, ')'); } } - seq_printf(s, " ]"); + seq_puts(s, " ]"); } - return; } static const struct pinconf_ops mvebu_pinconf_ops = { @@ -302,7 +329,7 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, return -EINVAL; if (grp->ctrl->mpp_gpio_req) - return grp->ctrl->mpp_gpio_req(offset); + return grp->ctrl->mpp_gpio_req(grp->data, offset); setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); if (!setting) @@ -325,7 +352,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, return -EINVAL; if (grp->ctrl->mpp_gpio_dir) - return grp->ctrl->mpp_gpio_dir(offset, input); + return grp->ctrl->mpp_gpio_dir(grp->data, offset, input); setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); if (!setting) @@ -398,13 +425,9 @@ static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } - *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); - if (*map == NULL) { - dev_err(pctl->dev, - "cannot allocate pinctrl_map memory for %s\n", - np->name); + *map = kmalloc_array(nmaps, sizeof(**map), GFP_KERNEL); + if (!*map) return -ENOMEM; - } n = 0; of_property_for_each_string(np, "marvell,pins", prop, group) { @@ -563,10 +586,8 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl), GFP_KERNEL); - if (!pctl) { - dev_err(&pdev->dev, "unable to alloc driver\n"); + if (!pctl) return -ENOMEM; - } pctl->desc.name = dev_name(&pdev->dev); pctl->desc.owner = THIS_MODULE; @@ -582,7 +603,7 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) pctl->num_groups = 0; pctl->desc.npins = 0; for (n = 0; n < soc->ncontrols; n++) { - struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; + const struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; pctl->desc.npins += ctrl->npins; /* initialize control's pins[] array */ @@ -604,10 +625,8 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins * sizeof(struct pinctrl_pin_desc), GFP_KERNEL); - if (!pdesc) { - dev_err(&pdev->dev, "failed to alloc pinctrl pins\n"); + if (!pdesc) return -ENOMEM; - } for (n = 0; n < pctl->desc.npins; n++) pdesc[n].number = n; @@ -628,9 +647,13 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) /* assign mpp controls to groups */ gid = 0; for (n = 0; n < soc->ncontrols; n++) { - struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; + const struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; + struct mvebu_mpp_ctrl_data *data = soc->control_data ? + &soc->control_data[n] : NULL; + pctl->groups[gid].gid = gid; pctl->groups[gid].ctrl = ctrl; + pctl->groups[gid].data = data; pctl->groups[gid].name = ctrl->name; pctl->groups[gid].pins = ctrl->pins; pctl->groups[gid].npins = ctrl->npins; @@ -650,6 +673,7 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) gid++; pctl->groups[gid].gid = gid; pctl->groups[gid].ctrl = ctrl; + pctl->groups[gid].data = data; pctl->groups[gid].name = noname_buf; pctl->groups[gid].pins = &ctrl->pins[k]; pctl->groups[gid].npins = 1; @@ -725,3 +749,94 @@ int mvebu_pinctrl_probe(struct platform_device *pdev) return 0; } + +/* + * mvebu_pinctrl_simple_mmio_probe - probe a simple mmio pinctrl + * @pdev: platform device (with platform data already attached) + * + * Initialise a simple (single base address) mmio pinctrl driver, + * assigning the MMIO base address to all mvebu mpp ctrl instances. + */ +int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev); + struct mvebu_mpp_ctrl_data *mpp_data; + struct resource *res; + void __iomem *base; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + mpp_data = devm_kcalloc(&pdev->dev, soc->ncontrols, sizeof(*mpp_data), + GFP_KERNEL); + if (!mpp_data) + return -ENOMEM; + + for (i = 0; i < soc->ncontrols; i++) + mpp_data[i].base = base; + + soc->control_data = mpp_data; + + return mvebu_pinctrl_probe(pdev); +} + +int mvebu_regmap_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, + unsigned int pid, unsigned long *config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned int val; + int err; + + err = regmap_read(data->regmap.map, data->regmap.offset + off, &val); + if (err) + return err; + + *config = (val >> shift) & MVEBU_MPP_MASK; + + return 0; +} + +int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, + unsigned int pid, unsigned long config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + + return regmap_update_bits(data->regmap.map, data->regmap.offset + off, + MVEBU_MPP_MASK << shift, config << shift); +} + +int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev, + struct device *syscon_dev) +{ + struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev); + struct mvebu_mpp_ctrl_data *mpp_data; + struct regmap *regmap; + u32 offset; + int i; + + regmap = syscon_node_to_regmap(syscon_dev->of_node); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + if (of_property_read_u32(pdev->dev.of_node, "offset", &offset)) + return -EINVAL; + + mpp_data = devm_kcalloc(&pdev->dev, soc->ncontrols, sizeof(*mpp_data), + GFP_KERNEL); + if (!mpp_data) + return -ENOMEM; + + for (i = 0; i < soc->ncontrols; i++) { + mpp_data[i].regmap.map = regmap; + mpp_data[i].regmap.offset = offset; + } + + soc->control_data = mpp_data; + + return mvebu_pinctrl_probe(pdev); +} diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h index b75a5f4adf3b..c90704e74884 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h @@ -14,6 +14,22 @@ #define __PINCTRL_MVEBU_H__ /** + * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations + * @base: base address of pinctrl hardware + * @regmap.map: regmap structure + * @regmap.offset: regmap offset + */ +struct mvebu_mpp_ctrl_data { + union { + void __iomem *base; + struct { + struct regmap *map; + u32 offset; + } regmap; + }; +}; + +/** * struct mvebu_mpp_ctrl - describe a mpp control * @name: name of the control group * @pid: first pin id handled by this control @@ -37,10 +53,13 @@ struct mvebu_mpp_ctrl { u8 pid; u8 npins; unsigned *pins; - int (*mpp_get)(unsigned pid, unsigned long *config); - int (*mpp_set)(unsigned pid, unsigned long config); - int (*mpp_gpio_req)(unsigned pid); - int (*mpp_gpio_dir)(unsigned pid, bool input); + int (*mpp_get)(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config); + int (*mpp_set)(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config); + int (*mpp_gpio_req)(struct mvebu_mpp_ctrl_data *data, unsigned pid); + int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl_data *data, unsigned pid, + bool input); }; /** @@ -93,6 +112,7 @@ struct mvebu_mpp_mode { * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu * @variant: variant mask of soc_info * @controls: list of available mvebu_mpp_ctrls + * @control_data: optional array, one entry for each control * @ncontrols: number of available mvebu_mpp_ctrls * @modes: list of available mvebu_mpp_modes * @nmodes: number of available mvebu_mpp_modes @@ -105,7 +125,8 @@ struct mvebu_mpp_mode { */ struct mvebu_pinctrl_soc_info { u8 variant; - struct mvebu_mpp_ctrl *controls; + const struct mvebu_mpp_ctrl *controls; + struct mvebu_mpp_ctrl_data *control_data; int ncontrols; struct mvebu_mpp_mode *modes; int nmodes; @@ -177,30 +198,18 @@ struct mvebu_pinctrl_soc_info { #define MVEBU_MPP_BITS 4 #define MVEBU_MPP_MASK 0xf -static inline int default_mpp_ctrl_get(void __iomem *base, unsigned int pid, - unsigned long *config) -{ - unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; - unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; - - *config = (readl(base + off) >> shift) & MVEBU_MPP_MASK; - - return 0; -} - -static inline int default_mpp_ctrl_set(void __iomem *base, unsigned int pid, - unsigned long config) -{ - unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; - unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; - unsigned long reg; - - reg = readl(base + off) & ~(MVEBU_MPP_MASK << shift); - writel(reg | (config << shift), base + off); - - return 0; -} +int mvebu_mmio_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config); +int mvebu_mmio_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config); +int mvebu_regmap_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long *config); +int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, + unsigned long config); int mvebu_pinctrl_probe(struct platform_device *pdev); +int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev); +int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev, + struct device *syscon_dev); #endif diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c index 84e144167b44..c2e0c16cf9b3 100644 --- a/drivers/pinctrl/mvebu/pinctrl-orion.c +++ b/drivers/pinctrl/mvebu/pinctrl-orion.c @@ -32,7 +32,8 @@ static void __iomem *mpp_base; static void __iomem *high_mpp_base; -static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config) +static int orion_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, + unsigned pid, unsigned long *config) { unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; @@ -47,7 +48,8 @@ static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config) return 0; } -static int orion_mpp_ctrl_set(unsigned pid, unsigned long config) +static int orion_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, + unsigned pid, unsigned long config) { unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; @@ -161,7 +163,7 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = { MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)), }; -static struct mvebu_mpp_ctrl orion_mpp_controls[] = { +static const struct mvebu_mpp_ctrl orion_mpp_controls[] = { MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl), }; diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 5391db7b368d..d69e357a7a98 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -198,7 +198,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) char *output_value; char *output_enable; - for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) { + for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { seq_printf(s, "GPIO bank%d\t", bank); switch (bank) { @@ -214,10 +214,14 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) i = 128; pin_num = AMD_GPIO_PINS_BANK2 + i; break; + case 3: + i = 192; + pin_num = AMD_GPIO_PINS_BANK3 + i; + break; default: - return; + /* Illegal bank number, ignore */ + continue; } - for (; i < pin_num; i++) { seq_printf(s, "pin%d\t", i); spin_lock_irqsave(&gpio_dev->lock, flags); @@ -227,14 +231,14 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { interrupt_enable = "interrupt is enabled|"; - if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) - && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) + if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && + !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) active_level = "Active low|"; - else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) - && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) + else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) && + !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) active_level = "Active high|"; - else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) - && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) + else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && + pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)) active_level = "Active on both|"; else active_level = "Unknow Active level|"; @@ -258,17 +262,17 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) interrupt_mask = "interrupt is masked|"; - if (pin_reg & BIT(WAKE_CNTRL_OFF)) + if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) wake_cntrl0 = "enable wakeup in S0i3 state|"; else wake_cntrl0 = "disable wakeup in S0i3 state|"; - if (pin_reg & BIT(WAKE_CNTRL_OFF)) + if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) wake_cntrl1 = "enable wakeup in S3 state|"; else wake_cntrl1 = "disable wakeup in S3 state|"; - if (pin_reg & BIT(WAKE_CNTRL_OFF)) + if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) wake_cntrl2 = "enable wakeup in S4/S5 state|"; else wake_cntrl2 = "disable wakeup in S4/S5 state|"; @@ -488,6 +492,7 @@ static struct irq_chip amd_gpio_irqchip = { .irq_unmask = amd_gpio_irq_unmask, .irq_eoi = amd_gpio_irq_eoi, .irq_set_type = amd_gpio_irq_set_type, + .flags = IRQCHIP_SKIP_SET_WAKE, }; static void amd_gpio_irq_handler(struct irq_desc *desc) @@ -773,15 +778,16 @@ static int amd_gpio_probe(struct platform_device *pdev) gpio_dev->gc.set_config = amd_gpio_set_config; gpio_dev->gc.dbg_show = amd_gpio_dbg_show; - gpio_dev->gc.base = 0; + gpio_dev->gc.base = -1; gpio_dev->gc.label = pdev->name; gpio_dev->gc.owner = THIS_MODULE; gpio_dev->gc.parent = &pdev->dev; - gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS; + gpio_dev->gc.ngpio = resource_size(res) / 4; #if defined(CONFIG_OF_GPIO) gpio_dev->gc.of_node = pdev->dev.of_node; #endif + gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; gpio_dev->groups = kerncz_groups; gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); @@ -798,7 +804,7 @@ static int amd_gpio_probe(struct platform_device *pdev) return ret; ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), - 0, 0, TOTAL_NUMBER_OF_PINS); + 0, 0, gpio_dev->gc.ngpio); if (ret) { dev_err(&pdev->dev, "Failed to add pin range\n"); goto out2; @@ -819,7 +825,6 @@ static int amd_gpio_probe(struct platform_device *pdev) &amd_gpio_irqchip, irq_base, amd_gpio_irq_handler); - platform_set_drvdata(pdev, gpio_dev); dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 7bfea47dbb47..c03f77822069 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -13,13 +13,12 @@ #ifndef _PINCTRL_AMD_H #define _PINCTRL_AMD_H -#define TOTAL_NUMBER_OF_PINS 192 #define AMD_GPIO_PINS_PER_BANK 64 -#define AMD_GPIO_TOTAL_BANKS 3 #define AMD_GPIO_PINS_BANK0 63 #define AMD_GPIO_PINS_BANK1 64 #define AMD_GPIO_PINS_BANK2 56 +#define AMD_GPIO_PINS_BANK3 32 #define WAKE_INT_MASTER_REG 0xfc #define EOI_MASK (1 << 29) @@ -35,7 +34,9 @@ #define ACTIVE_LEVEL_OFF 9 #define INTERRUPT_ENABLE_OFF 11 #define INTERRUPT_MASK_OFF 12 -#define WAKE_CNTRL_OFF 13 +#define WAKE_CNTRL_OFF_S0I3 13 +#define WAKE_CNTRL_OFF_S3 14 +#define WAKE_CNTRL_OFF_S4 15 #define PIN_STS_OFF 16 #define DRV_STRENGTH_SEL_OFF 17 #define PULL_UP_SEL_OFF 19 @@ -93,6 +94,7 @@ struct amd_gpio { u32 ngroups; struct pinctrl_dev *pctrl; struct gpio_chip gc; + unsigned int hwbank_num; struct resource *res; struct platform_device *pdev; }; diff --git a/drivers/pinctrl/pinctrl-da850-pupd.c b/drivers/pinctrl/pinctrl-da850-pupd.c index 44d5f5f5b07f..f41d3d948dd8 100644 --- a/drivers/pinctrl/pinctrl-da850-pupd.c +++ b/drivers/pinctrl/pinctrl-da850-pupd.c @@ -192,6 +192,7 @@ static const struct of_device_id da850_pupd_of_match[] = { { .compatible = "ti,da850-pupd" }, { } }; +MODULE_DEVICE_TABLE(of, da850_pupd_of_match); static struct platform_driver da850_pupd_driver = { .driver = { diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index 0b0fc2eb48e0..fb73dcbb5ef3 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -7,7 +7,7 @@ * by the Free Software Foundation. * * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + * Copyright (C) 2012 John Crispin <john@phrozen.org> */ #include <linux/gpio.h> diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index a4d647424600..41dc39c7a7b1 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. * - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + * Copyright (C) 2012 John Crispin <john@phrozen.org> */ #include <linux/module.h> diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h index e137d139e494..0e4308b8f235 100644 --- a/drivers/pinctrl/pinctrl-lantiq.h +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. * - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + * Copyright (C) 2012 John Crispin <john@phrozen.org> */ #ifndef __PINCTRL_LANTIQ_H diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index f71f2e813ea6..8b2d45e85bae 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -33,27 +33,12 @@ #include "core.h" #include "devicetree.h" #include "pinconf.h" +#include "pinmux.h" #define DRIVER_NAME "pinctrl-single" #define PCS_OFF_DISABLED ~0U /** - * struct pcs_pingroup - pingroups for a function - * @np: pingroup device node pointer - * @name: pingroup name - * @gpins: array of the pins in the group - * @ngpins: number of pins in the group - * @node: list node - */ -struct pcs_pingroup { - struct device_node *np; - const char *name; - int *gpins; - int ngpins; - struct list_head node; -}; - -/** * struct pcs_func_vals - mux function register offset and value pair * @reg: register virtual address * @val: register value @@ -176,16 +161,10 @@ struct pcs_soc_data { * @bits_per_mux: number of bits per mux * @bits_per_pin: number of bits per pin * @pins: physical pins on the SoC - * @pgtree: pingroup index radix tree - * @ftree: function index radix tree - * @pingroups: list of pingroups - * @functions: list of functions * @gpiofuncs: list of gpio functions * @irqs: list of interrupt registers * @chip: chip container for this instance * @domain: IRQ domain for this instance - * @ngroups: number of pingroups - * @nfuncs: number of functions * @desc: pin controller descriptor * @read: register read function to use * @write: register write function to use @@ -213,16 +192,10 @@ struct pcs_device { bool bits_per_mux; unsigned bits_per_pin; struct pcs_data pins; - struct radix_tree_root pgtree; - struct radix_tree_root ftree; - struct list_head pingroups; - struct list_head functions; struct list_head gpiofuncs; struct list_head irqs; struct irq_chip chip; struct irq_domain *domain; - unsigned ngroups; - unsigned nfuncs; struct pinctrl_desc desc; unsigned (*read)(void __iomem *reg); void (*write)(unsigned val, void __iomem *reg); @@ -288,54 +261,6 @@ static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) writel(val, reg); } -static int pcs_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct pcs_device *pcs; - - pcs = pinctrl_dev_get_drvdata(pctldev); - - return pcs->ngroups; -} - -static const char *pcs_get_group_name(struct pinctrl_dev *pctldev, - unsigned gselector) -{ - struct pcs_device *pcs; - struct pcs_pingroup *group; - - pcs = pinctrl_dev_get_drvdata(pctldev); - group = radix_tree_lookup(&pcs->pgtree, gselector); - if (!group) { - dev_err(pcs->dev, "%s could not find pingroup%i\n", - __func__, gselector); - return NULL; - } - - return group->name; -} - -static int pcs_get_group_pins(struct pinctrl_dev *pctldev, - unsigned gselector, - const unsigned **pins, - unsigned *npins) -{ - struct pcs_device *pcs; - struct pcs_pingroup *group; - - pcs = pinctrl_dev_get_drvdata(pctldev); - group = radix_tree_lookup(&pcs->pgtree, gselector); - if (!group) { - dev_err(pcs->dev, "%s could not find pingroup%i\n", - __func__, gselector); - return -EINVAL; - } - - *pins = group->gpins; - *npins = group->ngpins; - - return 0; -} - static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin) @@ -369,67 +294,21 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, struct pinctrl_map **map, unsigned *num_maps); static const struct pinctrl_ops pcs_pinctrl_ops = { - .get_groups_count = pcs_get_groups_count, - .get_group_name = pcs_get_group_name, - .get_group_pins = pcs_get_group_pins, + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, .pin_dbg_show = pcs_pin_dbg_show, .dt_node_to_map = pcs_dt_node_to_map, .dt_free_map = pcs_dt_free_map, }; -static int pcs_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct pcs_device *pcs; - - pcs = pinctrl_dev_get_drvdata(pctldev); - - return pcs->nfuncs; -} - -static const char *pcs_get_function_name(struct pinctrl_dev *pctldev, - unsigned fselector) -{ - struct pcs_device *pcs; - struct pcs_function *func; - - pcs = pinctrl_dev_get_drvdata(pctldev); - func = radix_tree_lookup(&pcs->ftree, fselector); - if (!func) { - dev_err(pcs->dev, "%s could not find function%i\n", - __func__, fselector); - return NULL; - } - - return func->name; -} - -static int pcs_get_function_groups(struct pinctrl_dev *pctldev, - unsigned fselector, - const char * const **groups, - unsigned * const ngroups) -{ - struct pcs_device *pcs; - struct pcs_function *func; - - pcs = pinctrl_dev_get_drvdata(pctldev); - func = radix_tree_lookup(&pcs->ftree, fselector); - if (!func) { - dev_err(pcs->dev, "%s could not find function%i\n", - __func__, fselector); - return -EINVAL; - } - *groups = func->pgnames; - *ngroups = func->npgnames; - - return 0; -} - static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, struct pcs_function **func) { struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); struct pin_desc *pdesc = pin_desc_get(pctldev, pin); const struct pinctrl_setting_mux *setting; + struct function_desc *function; unsigned fselector; /* If pin is not described in DTS & enabled, mux_setting is NULL. */ @@ -437,7 +316,8 @@ static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, if (!setting) return -ENOTSUPP; fselector = setting->func; - *func = radix_tree_lookup(&pcs->ftree, fselector); + function = pinmux_generic_get_function(pctldev, fselector); + *func = function->data; if (!(*func)) { dev_err(pcs->dev, "%s could not find function%i\n", __func__, fselector); @@ -450,6 +330,7 @@ static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, unsigned group) { struct pcs_device *pcs; + struct function_desc *function; struct pcs_function *func; int i; @@ -457,7 +338,8 @@ static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, /* If function mask is null, needn't enable it. */ if (!pcs->fmask) return 0; - func = radix_tree_lookup(&pcs->ftree, fselector); + function = pinmux_generic_get_function(pctldev, fselector); + func = function->data; if (!func) return -EINVAL; @@ -515,9 +397,9 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, } static const struct pinmux_ops pcs_pinmux_ops = { - .get_functions_count = pcs_get_functions_count, - .get_function_name = pcs_get_function_name, - .get_function_groups = pcs_get_function_groups, + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, .set_mux = pcs_set_mux, .gpio_request_enable = pcs_request_gpio, }; @@ -685,7 +567,7 @@ static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned npins, old = 0; int i, ret; - ret = pcs_get_group_pins(pctldev, group, &pins, &npins); + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; for (i = 0; i < npins; i++) { @@ -707,7 +589,7 @@ static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned npins; int i, ret; - ret = pcs_get_group_pins(pctldev, group, &pins, &npins); + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); if (ret) return ret; for (i = 0; i < npins; i++) { @@ -859,77 +741,24 @@ static struct pcs_function *pcs_add_function(struct pcs_device *pcs, unsigned npgnames) { struct pcs_function *function; + int res; function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); if (!function) return NULL; - function->name = name; function->vals = vals; function->nvals = nvals; - function->pgnames = pgnames; - function->npgnames = npgnames; - mutex_lock(&pcs->mutex); - list_add_tail(&function->node, &pcs->functions); - radix_tree_insert(&pcs->ftree, pcs->nfuncs, function); - pcs->nfuncs++; - mutex_unlock(&pcs->mutex); + res = pinmux_generic_add_function(pcs->pctl, name, + pgnames, npgnames, + function); + if (res) + return NULL; return function; } -static void pcs_remove_function(struct pcs_device *pcs, - struct pcs_function *function) -{ - int i; - - mutex_lock(&pcs->mutex); - for (i = 0; i < pcs->nfuncs; i++) { - struct pcs_function *found; - - found = radix_tree_lookup(&pcs->ftree, i); - if (found == function) - radix_tree_delete(&pcs->ftree, i); - } - list_del(&function->node); - mutex_unlock(&pcs->mutex); -} - -/** - * pcs_add_pingroup() - add a pingroup to the pingroup list - * @pcs: pcs driver instance - * @np: device node of the mux entry - * @name: name of the pingroup - * @gpins: array of the pins that belong to the group - * @ngpins: number of pins in the group - */ -static int pcs_add_pingroup(struct pcs_device *pcs, - struct device_node *np, - const char *name, - int *gpins, - int ngpins) -{ - struct pcs_pingroup *pingroup; - - pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL); - if (!pingroup) - return -ENOMEM; - - pingroup->name = name; - pingroup->np = np; - pingroup->gpins = gpins; - pingroup->ngpins = ngpins; - - mutex_lock(&pcs->mutex); - list_add_tail(&pingroup->node, &pcs->pingroups); - radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup); - pcs->ngroups++; - mutex_unlock(&pcs->mutex); - - return 0; -} - /** * pcs_get_pin_by_offset() - get a pin index based on the register offset * @pcs: pcs driver instance @@ -1100,10 +929,9 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, return 0; } -static void pcs_free_pingroups(struct pcs_device *pcs); - /** * smux_parse_one_pinctrl_entry() - parses a device tree mux entry + * @pctldev: pin controller device * @pcs: pinctrl driver instance * @np: device node of the mux entry * @map: map entry @@ -1134,7 +962,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, rows = pinctrl_count_index_with_args(np, name); if (rows <= 0) { - dev_err(pcs->dev, "Ivalid number of rows: %d\n", rows); + dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); return -EINVAL; } @@ -1186,7 +1014,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, goto free_pins; } - res = pcs_add_pingroup(pcs, np, np->name, pins, found); + res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); if (res < 0) goto free_function; @@ -1205,10 +1033,10 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, return 0; free_pingroups: - pcs_free_pingroups(pcs); + pinctrl_generic_remove_last_group(pcs->pctl); *num_maps = 1; free_function: - pcs_remove_function(pcs, function); + pinmux_generic_remove_last_function(pcs->pctl); free_pins: devm_kfree(pcs->dev, pins); @@ -1320,7 +1148,7 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, goto free_pins; } - res = pcs_add_pingroup(pcs, np, np->name, pins, found); + res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); if (res < 0) goto free_function; @@ -1337,11 +1165,10 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, return 0; free_pingroups: - pcs_free_pingroups(pcs); + pinctrl_generic_remove_last_group(pcs->pctl); *num_maps = 1; free_function: - pcs_remove_function(pcs, function); - + pinmux_generic_remove_last_function(pcs->pctl); free_pins: devm_kfree(pcs->dev, pins); @@ -1409,60 +1236,6 @@ free_map: } /** - * pcs_free_funcs() - free memory used by functions - * @pcs: pcs driver instance - */ -static void pcs_free_funcs(struct pcs_device *pcs) -{ - struct list_head *pos, *tmp; - int i; - - mutex_lock(&pcs->mutex); - for (i = 0; i < pcs->nfuncs; i++) { - struct pcs_function *func; - - func = radix_tree_lookup(&pcs->ftree, i); - if (!func) - continue; - radix_tree_delete(&pcs->ftree, i); - } - list_for_each_safe(pos, tmp, &pcs->functions) { - struct pcs_function *function; - - function = list_entry(pos, struct pcs_function, node); - list_del(&function->node); - } - mutex_unlock(&pcs->mutex); -} - -/** - * pcs_free_pingroups() - free memory used by pingroups - * @pcs: pcs driver instance - */ -static void pcs_free_pingroups(struct pcs_device *pcs) -{ - struct list_head *pos, *tmp; - int i; - - mutex_lock(&pcs->mutex); - for (i = 0; i < pcs->ngroups; i++) { - struct pcs_pingroup *pingroup; - - pingroup = radix_tree_lookup(&pcs->pgtree, i); - if (!pingroup) - continue; - radix_tree_delete(&pcs->pgtree, i); - } - list_for_each_safe(pos, tmp, &pcs->pingroups) { - struct pcs_pingroup *pingroup; - - pingroup = list_entry(pos, struct pcs_pingroup, node); - list_del(&pingroup->node); - } - mutex_unlock(&pcs->mutex); -} - -/** * pcs_irq_free() - free interrupt * @pcs: pcs driver instance */ @@ -1490,8 +1263,7 @@ static void pcs_free_resources(struct pcs_device *pcs) { pcs_irq_free(pcs); pinctrl_unregister(pcs->pctl); - pcs_free_funcs(pcs); - pcs_free_pingroups(pcs); + #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) if (pcs->missing_nr_pinctrl_cells) of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); @@ -1885,8 +1657,6 @@ static int pcs_probe(struct platform_device *pdev) pcs->np = np; raw_spin_lock_init(&pcs->lock); mutex_init(&pcs->mutex); - INIT_LIST_HEAD(&pcs->pingroups); - INIT_LIST_HEAD(&pcs->functions); INIT_LIST_HEAD(&pcs->gpiofuncs); soc = match->data; pcs->flags = soc->flags; @@ -1947,8 +1717,6 @@ static int pcs_probe(struct platform_device *pdev) return -ENODEV; } - INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL); - INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL); platform_set_drvdata(pdev, pcs); switch (pcs->width) { @@ -1979,10 +1747,9 @@ static int pcs_probe(struct platform_device *pdev) if (ret < 0) goto free; - pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs); - if (IS_ERR(pcs->pctl)) { + ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); + if (ret) { dev_err(pcs->dev, "could not register single pinctrl driver\n"); - ret = PTR_ERR(pcs->pctl); goto free; } diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index dd85ad1807f5..d4167e2c173a 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. * - * Copyright (C) 2012 John Crispin <blogic@openwrt.org> + * Copyright (C) 2012 John Crispin <john@phrozen.org> * Copyright (C) 2015 Martin Schiller <mschiller@tdt.de> */ diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index ece702881946..29ad3151abec 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -99,37 +99,24 @@ static int pin_request(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n", pin, desc->name, owner); - if (gpio_range) { - /* There's no need to support multiple GPIO requests */ - if (desc->gpio_owner) { - dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->gpio_owner, owner); - goto out; - } - if (ops->strict && desc->mux_usecount && - strcmp(desc->mux_owner, owner)) { - dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->mux_owner, owner); - goto out; - } + if ((!gpio_range || ops->strict) && + desc->mux_usecount && strcmp(desc->mux_owner, owner)) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->mux_owner, owner); + goto out; + } + if ((gpio_range || ops->strict) && desc->gpio_owner) { + dev_err(pctldev->dev, + "pin %s already requested by %s; cannot claim for %s\n", + desc->name, desc->gpio_owner, owner); + goto out; + } + + if (gpio_range) { desc->gpio_owner = owner; } else { - if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { - dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->mux_owner, owner); - goto out; - } - if (ops->strict && desc->gpio_owner) { - dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->gpio_owner, owner); - goto out; - } - desc->mux_usecount++; if (desc->mux_usecount > 1) return 0; @@ -695,3 +682,176 @@ void pinmux_init_device_debugfs(struct dentry *devroot, } #endif /* CONFIG_DEBUG_FS */ + +#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS + +/** + * pinmux_generic_get_function_count() - returns number of functions + * @pctldev: pin controller device + */ +int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev) +{ + return pctldev->num_functions; +} +EXPORT_SYMBOL_GPL(pinmux_generic_get_function_count); + +/** + * pinmux_generic_get_function_name() - returns the function name + * @pctldev: pin controller device + * @selector: function number + */ +const char * +pinmux_generic_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct function_desc *function; + + function = radix_tree_lookup(&pctldev->pin_function_tree, + selector); + if (!function) + return NULL; + + return function->name; +} +EXPORT_SYMBOL_GPL(pinmux_generic_get_function_name); + +/** + * pinmux_generic_get_function_groups() - gets the function groups + * @pctldev: pin controller device + * @selector: function number + * @groups: array of pin groups + * @num_groups: number of pin groups + */ +int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct function_desc *function; + + function = radix_tree_lookup(&pctldev->pin_function_tree, + selector); + if (!function) { + dev_err(pctldev->dev, "%s could not find function%i\n", + __func__, selector); + return -EINVAL; + } + *groups = function->group_names; + *num_groups = function->num_group_names; + + return 0; +} +EXPORT_SYMBOL_GPL(pinmux_generic_get_function_groups); + +/** + * pinmux_generic_get_function() - returns a function based on the number + * @pctldev: pin controller device + * @group_selector: function number + */ +struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct function_desc *function; + + function = radix_tree_lookup(&pctldev->pin_function_tree, + selector); + if (!function) + return NULL; + + return function; +} +EXPORT_SYMBOL_GPL(pinmux_generic_get_function); + +/** + * pinmux_generic_get_function_groups() - gets the function groups + * @pctldev: pin controller device + * @name: name of the function + * @groups: array of pin groups + * @num_groups: number of pin groups + * @data: pin controller driver specific data + */ +int pinmux_generic_add_function(struct pinctrl_dev *pctldev, + const char *name, + const char **groups, + const unsigned int num_groups, + void *data) +{ + struct function_desc *function; + + function = devm_kzalloc(pctldev->dev, sizeof(*function), GFP_KERNEL); + if (!function) + return -ENOMEM; + + function->name = name; + function->group_names = groups; + function->num_group_names = num_groups; + function->data = data; + + radix_tree_insert(&pctldev->pin_function_tree, pctldev->num_functions, + function); + + pctldev->num_functions++; + + return 0; +} +EXPORT_SYMBOL_GPL(pinmux_generic_add_function); + +/** + * pinmux_generic_remove_function() - removes a numbered function + * @pctldev: pin controller device + * @selector: function number + * + * Note that the caller must take care of locking. + */ +int pinmux_generic_remove_function(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct function_desc *function; + + function = radix_tree_lookup(&pctldev->pin_function_tree, + selector); + if (!function) + return -ENOENT; + + radix_tree_delete(&pctldev->pin_function_tree, selector); + devm_kfree(pctldev->dev, function); + + pctldev->num_functions--; + + return 0; +} +EXPORT_SYMBOL_GPL(pinmux_generic_remove_function); + +/** + * pinmux_generic_free_functions() - removes all functions + * @pctldev: pin controller device + * + * Note that the caller must take care of locking. + */ +void pinmux_generic_free_functions(struct pinctrl_dev *pctldev) +{ + struct radix_tree_iter iter; + struct function_desc *function; + unsigned long *indices; + void **slot; + int i = 0; + + indices = devm_kzalloc(pctldev->dev, sizeof(*indices) * + pctldev->num_functions, GFP_KERNEL); + if (!indices) + return; + + radix_tree_for_each_slot(slot, &pctldev->pin_function_tree, &iter, 0) + indices[i++] = iter.index; + + for (i = 0; i < pctldev->num_functions; i++) { + function = radix_tree_lookup(&pctldev->pin_function_tree, + indices[i]); + radix_tree_delete(&pctldev->pin_function_tree, indices[i]); + devm_kfree(pctldev->dev, function); + } + + pctldev->num_functions = 0; +} + +#endif /* CONFIG_GENERIC_PINMUX_FUNCTIONS */ diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index d1a98b1c9fce..248d8ea30e26 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -111,3 +111,59 @@ static inline void pinmux_init_device_debugfs(struct dentry *devroot, } #endif + +#ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS + +/** + * struct function_desc - generic function descriptor + * @name: name of the function + * @group_names: array of pin group names + * @num_group_names: number of pin group names + * @data: pin controller driver specific data + */ +struct function_desc { + const char *name; + const char **group_names; + int num_group_names; + void *data; +}; + +int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev); + +const char * +pinmux_generic_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector); + +int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups); + +struct function_desc *pinmux_generic_get_function(struct pinctrl_dev *pctldev, + unsigned int selector); + +int pinmux_generic_add_function(struct pinctrl_dev *pctldev, + const char *name, + const char **groups, + unsigned const num_groups, + void *data); + +int pinmux_generic_remove_function(struct pinctrl_dev *pctldev, + unsigned int selector); + +static inline int +pinmux_generic_remove_last_function(struct pinctrl_dev *pctldev) +{ + return pinmux_generic_remove_function(pctldev, + pctldev->num_functions - 1); +} + +void pinmux_generic_free_functions(struct pinctrl_dev *pctldev); + +#else + +static inline void pinmux_generic_free_functions(struct pinctrl_dev *pctldev) +{ +} + +#endif /* CONFIG_GENERIC_PINMUX_FUNCTIONS */ diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 775c88303017..f8e9e1c2b2f6 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -61,7 +61,7 @@ struct msm_pinctrl { struct notifier_block restart_nb; int irq; - spinlock_t lock; + raw_spinlock_t lock; DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); @@ -153,14 +153,14 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, if (WARN_ON(i == g->nfuncs)) return -EINVAL; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->ctl_reg); val &= ~mask; val |= i << g->mux_bit; writel(val, pctrl->regs + g->ctl_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } @@ -323,14 +323,14 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_OUTPUT: /* set output value */ - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->io_reg); if (arg) val |= BIT(g->out_bit); else val &= ~BIT(g->out_bit); writel(val, pctrl->regs + g->io_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); /* enable output */ arg = 1; @@ -351,12 +351,12 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, return -EINVAL; } - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->ctl_reg); val &= ~(mask << bit); val |= arg << bit; writel(val, pctrl->regs + g->ctl_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } return 0; @@ -384,13 +384,13 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) g = &pctrl->soc->groups[offset]; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->ctl_reg); val &= ~BIT(g->oe_bit); writel(val, pctrl->regs + g->ctl_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } @@ -404,7 +404,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in g = &pctrl->soc->groups[offset]; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->io_reg); if (value) @@ -417,7 +417,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in val |= BIT(g->oe_bit); writel(val, pctrl->regs + g->ctl_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } @@ -443,7 +443,7 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) g = &pctrl->soc->groups[offset]; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->io_reg); if (value) @@ -452,7 +452,7 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) val &= ~BIT(g->out_bit); writel(val, pctrl->regs + g->io_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } #ifdef CONFIG_DEBUG_FS @@ -571,7 +571,7 @@ static void msm_gpio_irq_mask(struct irq_data *d) g = &pctrl->soc->groups[d->hwirq]; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_cfg_reg); val &= ~BIT(g->intr_enable_bit); @@ -579,7 +579,7 @@ static void msm_gpio_irq_mask(struct irq_data *d) clear_bit(d->hwirq, pctrl->enabled_irqs); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static void msm_gpio_irq_unmask(struct irq_data *d) @@ -592,7 +592,7 @@ static void msm_gpio_irq_unmask(struct irq_data *d) g = &pctrl->soc->groups[d->hwirq]; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_status_reg); val &= ~BIT(g->intr_status_bit); @@ -604,7 +604,7 @@ static void msm_gpio_irq_unmask(struct irq_data *d) set_bit(d->hwirq, pctrl->enabled_irqs); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static void msm_gpio_irq_ack(struct irq_data *d) @@ -617,7 +617,7 @@ static void msm_gpio_irq_ack(struct irq_data *d) g = &pctrl->soc->groups[d->hwirq]; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_status_reg); if (g->intr_ack_high) @@ -629,7 +629,7 @@ static void msm_gpio_irq_ack(struct irq_data *d) if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) msm_gpio_update_dual_edge_pos(pctrl, g, d); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) @@ -642,7 +642,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) g = &pctrl->soc->groups[d->hwirq]; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); /* * For hw without possibility of detecting both edges @@ -716,7 +716,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) msm_gpio_update_dual_edge_pos(pctrl, g, d); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) irq_set_handler_locked(d, handle_level_irq); @@ -732,11 +732,11 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) struct msm_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; - spin_lock_irqsave(&pctrl->lock, flags); + raw_spin_lock_irqsave(&pctrl->lock, flags); irq_set_irq_wake(pctrl->irq, on); - spin_unlock_irqrestore(&pctrl->lock, flags); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); return 0; } @@ -882,7 +882,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, pctrl->soc = soc_data; pctrl->chip = msm_gpio_template; - spin_lock_init(&pctrl->lock); + raw_spin_lock_init(&pctrl->lock); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pctrl->regs = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c index 5591d093bf78..bb71dd1e6279 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -193,9 +193,9 @@ static const struct pinctrl_pin_desc msm8660_pins[] = { PINCTRL_PIN(171, "GPIO_171"), PINCTRL_PIN(172, "GPIO_172"), - PINCTRL_PIN(173, "SDC1_CLK"), - PINCTRL_PIN(174, "SDC1_CMD"), - PINCTRL_PIN(175, "SDC1_DATA"), + PINCTRL_PIN(173, "SDC4_CLK"), + PINCTRL_PIN(174, "SDC4_CMD"), + PINCTRL_PIN(175, "SDC4_DATA"), PINCTRL_PIN(176, "SDC3_CLK"), PINCTRL_PIN(177, "SDC3_CMD"), PINCTRL_PIN(178, "SDC3_DATA"), diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 07409fde02b2..f9b49967f512 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -24,11 +24,15 @@ #include <linux/irqdomain.h> #include <linux/irq.h> #include <linux/irqchip/chained_irq.h> +#include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/spinlock.h> +#include <linux/regmap.h> #include <linux/err.h> +#include <linux/soc/samsung/exynos-pmu.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" @@ -528,10 +532,8 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) weint_data = devm_kzalloc(dev, bank->nr_pins * sizeof(*weint_data), GFP_KERNEL); - if (!weint_data) { - dev_err(dev, "could not allocate memory for weint_data\n"); + if (!weint_data) return -ENOMEM; - } for (idx = 0; idx < bank->nr_pins; ++idx) { irq = irq_of_parse_and_map(bank->of_node, idx); @@ -559,10 +561,8 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); - if (!muxed_data) { - dev_err(dev, "could not allocate memory for muxed_data\n"); + if (!muxed_data) return -ENOMEM; - } irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, muxed_data); @@ -644,6 +644,60 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) exynos_pinctrl_resume_bank(drvdata, bank); } +/* Retention control for S5PV210 are located at the end of clock controller */ +#define S5P_OTHERS 0xE000 + +#define S5P_OTHERS_RET_IO (1 << 31) +#define S5P_OTHERS_RET_CF (1 << 30) +#define S5P_OTHERS_RET_MMC (1 << 29) +#define S5P_OTHERS_RET_UART (1 << 28) + +static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata) +{ + void *clk_base = drvdata->retention_ctrl->priv; + u32 tmp; + + tmp = __raw_readl(clk_base + S5P_OTHERS); + tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC | + S5P_OTHERS_RET_UART); + __raw_writel(tmp, clk_base + S5P_OTHERS); +} + +static struct samsung_retention_ctrl * +s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data) +{ + struct samsung_retention_ctrl *ctrl; + struct device_node *np; + void *clk_base; + + ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return ERR_PTR(-ENOMEM); + + np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); + if (!np) { + pr_err("%s: failed to find clock controller DT node\n", + __func__); + return ERR_PTR(-ENODEV); + } + + clk_base = of_iomap(np, 0); + if (!clk_base) { + pr_err("%s: failed to map clock registers\n", __func__); + return ERR_PTR(-EINVAL); + } + + ctrl->priv = clk_base; + ctrl->disable = s5pv210_retention_disable; + + return ctrl; +} + +static const struct samsung_retention_data s5pv210_retention_data __initconst = { + .init = s5pv210_retention_init, +}; + /* pin banks of s5pv210 pin-controller */ static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), @@ -691,9 +745,58 @@ const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &s5pv210_retention_data, }, }; +/* Pad retention control code for accessing PMU regmap */ +static atomic_t exynos_shared_retention_refcnt; + +static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) +{ + if (drvdata->retention_ctrl->refcnt) + atomic_inc(drvdata->retention_ctrl->refcnt); +} + +static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) +{ + struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; + struct regmap *pmu_regs = ctrl->priv; + int i; + + if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) + return; + + for (i = 0; i < ctrl->nr_regs; i++) + regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); +} + +static struct samsung_retention_ctrl * +exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data) +{ + struct samsung_retention_ctrl *ctrl; + struct regmap *pmu_regs; + + ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return ERR_PTR(-ENOMEM); + + pmu_regs = exynos_get_pmu_regmap(); + if (IS_ERR(pmu_regs)) + return ERR_CAST(pmu_regs); + + ctrl->priv = pmu_regs; + ctrl->regs = data->regs; + ctrl->nr_regs = data->nr_regs; + ctrl->value = data->value; + ctrl->refcnt = data->refcnt; + ctrl->enable = exynos_retention_enable; + ctrl->disable = exynos_retention_disable; + + return ctrl; +} + /* pin banks of exynos3250 pin-controller 0 */ static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), @@ -726,6 +829,30 @@ static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = }; /* + * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle + * them all together + */ +static const u32 exynos3250_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, + S5P_PAD_RET_MMC2_OPTION, + S5P_PAD_RET_SPI_OPTION, +}; + +static const struct samsung_retention_data exynos3250_retention_data __initconst = { + .regs = exynos3250_retention_regs, + .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes * two gpio/pin-mux/pinconfig controllers. */ @@ -737,6 +864,7 @@ const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos3250_pin_banks1, @@ -745,6 +873,7 @@ const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, }, }; @@ -797,6 +926,36 @@ static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), }; +/* PMU pad retention groups registers for Exynos4 (without audio) */ +static const u32 exynos4_retention_regs[] = { + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, +}; + +static const struct samsung_retention_data exynos4_retention_data __initconst = { + .regs = exynos4_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* PMU retention control for audio pins can be tied to audio pin bank */ +static const u32 exynos4_audio_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, +}; + +static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { + .regs = exynos4_audio_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + /* * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes * three gpio/pin-mux/pinconfig controllers. @@ -809,6 +968,7 @@ const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos4210_pin_banks1, @@ -817,10 +977,12 @@ const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos4210_pin_banks2, .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), + .retention_data = &exynos4_audio_retention_data, }, }; @@ -894,6 +1056,7 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos4x12_pin_banks1, @@ -902,6 +1065,7 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos4x12_pin_banks2, @@ -909,6 +1073,7 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, }, { /* pin-controller instance 3 data */ .pin_banks = exynos4x12_pin_banks3, @@ -919,81 +1084,6 @@ const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { }, }; -/* pin banks of exynos4415 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), - EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38), -}; - -/* pin banks of exynos4415 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = { - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), - EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), - EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), - EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18), - EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"), - EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"), - EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"), - EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"), - EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"), - EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"), - EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"), - EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), - EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos4415 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), - EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"), -}; - -/* - * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes - * three gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos4415_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos4415_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos4415_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos4415_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos4415_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos4415_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, -}; - /* pin banks of exynos5250 pin-controller 0 */ static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), @@ -1063,6 +1153,7 @@ const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos5250_pin_banks1, @@ -1070,6 +1161,7 @@ const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos5250_pin_banks2, @@ -1084,6 +1176,7 @@ const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, }, }; @@ -1310,6 +1403,30 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), }; +/* PMU pad retention groups registers for Exynos5420 (without audio) */ +static const u32 exynos5420_retention_regs[] = { + EXYNOS_PAD_RET_DRAM_OPTION, + EXYNOS_PAD_RET_JTAG_OPTION, + EXYNOS5420_PAD_RET_GPIO_OPTION, + EXYNOS5420_PAD_RET_UART_OPTION, + EXYNOS5420_PAD_RET_MMCA_OPTION, + EXYNOS5420_PAD_RET_MMCB_OPTION, + EXYNOS5420_PAD_RET_MMCC_OPTION, + EXYNOS5420_PAD_RET_HSI_OPTION, + EXYNOS_PAD_RET_EBIA_OPTION, + EXYNOS_PAD_RET_EBIB_OPTION, + EXYNOS5420_PAD_RET_SPI_OPTION, + EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, +}; + +static const struct samsung_retention_data exynos5420_retention_data __initconst = { + .regs = exynos5420_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + /* * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes * four gpio/pin-mux/pinconfig controllers. @@ -1321,114 +1438,119 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos5420_pin_banks1, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos5420_pin_banks2, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 3 data */ .pin_banks = exynos5420_pin_banks3, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 4 data */ .pin_banks = exynos5420_pin_banks4, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos4_audio_retention_data, }, }; /* pin banks of exynos5433 pin-controller - ALIVE */ -static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = { - EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), - EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), - EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), - EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), - EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), +static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), + EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), + EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), }; /* pin banks of exynos5433 pin-controller - AUD */ -static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = { - EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), - EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), }; /* pin banks of exynos5433 pin-controller - CPIF */ -static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = { - EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), +static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), }; /* pin banks of exynos5433 pin-controller - eSE */ -static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = { - EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), +static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), }; /* pin banks of exynos5433 pin-controller - FINGER */ -static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = { - EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), +static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), }; /* pin banks of exynos5433 pin-controller - FSYS */ -static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = { - EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), - EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), - EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), - EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), - EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), - EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), +static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { + EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), + EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), }; /* pin banks of exynos5433 pin-controller - IMEM */ -static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = { - EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), +static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), }; /* pin banks of exynos5433 pin-controller - NFC */ -static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = { - EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), +static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), }; /* pin banks of exynos5433 pin-controller - PERIC */ -static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = { - EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), - EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), - EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), - EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), - EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), - EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), - EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), - EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), - EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), - EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), - EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), - EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), - EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), - EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), - EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), - EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), - EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), +static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { + EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), + EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), + EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), + EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), + EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), + EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), + EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), + EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), + EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), + EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), }; /* pin banks of exynos5433 pin-controller - TOUCH */ -static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = { - EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), +static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), }; /* * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes * ten gpio/pin-mux/pinconfig controllers. */ -const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = { +const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { { /* pin-controller instance 0 data */ .pin_banks = exynos5433_pin_banks0, diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c index 4c632812ccff..f17890aa6e25 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -489,10 +489,8 @@ static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d) data = devm_kzalloc(dev, sizeof(*data) + nr_domains * sizeof(*data->domains), GFP_KERNEL); - if (!data) { - dev_err(dev, "failed to allocate handler data\n"); + if (!data) return -ENOMEM; - } data->drvdata = d; bank = d->pin_banks; @@ -715,10 +713,8 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) return -ENODEV; data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); - if (!data) { - dev_err(dev, "could not allocate memory for wkup eint data\n"); + if (!data) return -ENOMEM; - } data->drvdata = d; for (i = 0; i < NUM_EINT0_IRQ; ++i) { @@ -751,10 +747,8 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) ddata = devm_kzalloc(dev, sizeof(*ddata) + nr_eints, GFP_KERNEL); - if (!ddata) { - dev_err(dev, "failed to allocate domain data\n"); + if (!ddata) return -ENOMEM; - } ddata->bank = bank; bank->irq_domain = irq_domain_add_linear(bank->of_node, diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 41e62391c33c..d79eadad6c5f 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -27,8 +27,8 @@ #include <linux/err.h> #include <linux/gpio.h> #include <linux/irqdomain.h> +#include <linux/of_device.h> #include <linux/spinlock.h> -#include <linux/syscore_ops.h> #include "../core.h" #include "pinctrl-samsung.h" @@ -48,9 +48,6 @@ static struct pin_config { { "samsung,pin-val", PINCFG_TYPE_DAT }, }; -/* Global list of devices (struct samsung_pinctrl_drv_data) */ -static LIST_HEAD(drvdata_list); - static unsigned int pin_base; static int samsung_get_group_count(struct pinctrl_dev *pctldev) @@ -93,10 +90,8 @@ static int reserve_map(struct device *dev, struct pinctrl_map **map, return 0; new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); + if (!new_map) return -ENOMEM; - } memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); @@ -133,10 +128,8 @@ static int add_map_configs(struct device *dev, struct pinctrl_map **map, dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), GFP_KERNEL); - if (!dup_configs) { - dev_err(dev, "kmemdup(configs) failed\n"); + if (!dup_configs) return -ENOMEM; - } (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; (*map)[*num_maps].data.configs.group_or_pin = group; @@ -156,10 +149,8 @@ static int add_config(struct device *dev, unsigned long **configs, new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, GFP_KERNEL); - if (!new_configs) { - dev_err(dev, "krealloc(configs) failed\n"); + if (!new_configs) return -ENOMEM; - } new_configs[old_num] = config; @@ -356,7 +347,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata, /* enable or disable a pinmux function */ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group, bool enable) + unsigned group) { struct samsung_pinctrl_drv_data *drvdata; const struct samsung_pin_bank_type *type; @@ -386,8 +377,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); data &= ~(mask << shift); - if (enable) - data |= func->val << shift; + data |= func->val << shift; writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); spin_unlock_irqrestore(&bank->slock, flags); @@ -398,7 +388,7 @@ static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { - samsung_pinmux_setup(pctldev, selector, group, true); + samsung_pinmux_setup(pctldev, selector, group); return 0; } @@ -756,10 +746,8 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions( functions = devm_kzalloc(dev, func_cnt * sizeof(*functions), GFP_KERNEL); - if (!functions) { - dev_err(dev, "failed to allocate memory for function list\n"); - return ERR_PTR(-EINVAL); - } + if (!functions) + return ERR_PTR(-ENOMEM); func = functions; /* @@ -850,10 +838,8 @@ static int samsung_pinctrl_register(struct platform_device *pdev, pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * drvdata->nr_pins, GFP_KERNEL); - if (!pindesc) { - dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); + if (!pindesc) return -ENOMEM; - } ctrldesc->pins = pindesc; ctrldesc->npins = drvdata->nr_pins; @@ -867,10 +853,8 @@ static int samsung_pinctrl_register(struct platform_device *pdev, */ pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * drvdata->nr_pins, GFP_KERNEL); - if (!pin_names) { - dev_err(&pdev->dev, "mem alloc for pin names failed\n"); + if (!pin_names) return -ENOMEM; - } /* for each pin, the name of the pin is pin-bank name + pin number */ for (bank = 0; bank < drvdata->nr_banks; bank++) { @@ -968,15 +952,12 @@ static int samsung_gpiolib_unregister(struct platform_device *pdev, return 0; } -static const struct of_device_id samsung_pinctrl_dt_match[]; - /* retrieve the soc specific data */ static const struct samsung_pin_ctrl * samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, struct platform_device *pdev) { int id; - const struct of_device_id *match; struct device_node *node = pdev->dev.of_node; struct device_node *np; const struct samsung_pin_bank_data *bdata; @@ -991,8 +972,8 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, dev_err(&pdev->dev, "failed to get alias id\n"); return ERR_PTR(-ENOENT); } - match = of_match_node(samsung_pinctrl_dt_match, node); - ctrl = (struct samsung_pin_ctrl *)match->data + id; + ctrl = of_device_get_match_data(&pdev->dev); + ctrl += id; d->suspend = ctrl->suspend; d->resume = ctrl->resume; @@ -1075,6 +1056,13 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) if (res) drvdata->irq = res->start; + if (ctrl->retention_data) { + drvdata->retention_ctrl = ctrl->retention_data->init(drvdata, + ctrl->retention_data); + if (IS_ERR(drvdata->retention_ctrl)) + return PTR_ERR(drvdata->retention_ctrl); + } + ret = samsung_gpiolib_register(pdev, drvdata); if (ret) return ret; @@ -1092,22 +1080,18 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, drvdata); - /* Add to the global list */ - list_add_tail(&drvdata->node, &drvdata_list); - return 0; } #ifdef CONFIG_PM - /** - * samsung_pinctrl_suspend_dev - save pinctrl state for suspend for a device + * samsung_pinctrl_suspend - save pinctrl state for suspend * * Save data for all banks handled by this device. */ -static void samsung_pinctrl_suspend_dev( - struct samsung_pinctrl_drv_data *drvdata) +static int samsung_pinctrl_suspend(struct device *dev) { + struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); int i; for (i = 0; i < drvdata->nr_banks; i++) { @@ -1141,18 +1125,23 @@ static void samsung_pinctrl_suspend_dev( if (drvdata->suspend) drvdata->suspend(drvdata); + if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) + drvdata->retention_ctrl->enable(drvdata); + + return 0; } /** - * samsung_pinctrl_resume_dev - restore pinctrl state from suspend for a device + * samsung_pinctrl_resume - restore pinctrl state from suspend * * Restore one of the banks that was saved during suspend. * * We don't bother doing anything complicated to avoid glitching lines since * we're called before pad retention is turned off. */ -static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) +static int samsung_pinctrl_resume(struct device *dev) { + struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev); int i; if (drvdata->resume) @@ -1188,48 +1177,14 @@ static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) if (widths[type]) writel(bank->pm_save[type], reg + offs[type]); } -} -/** - * samsung_pinctrl_suspend - save pinctrl state for suspend - * - * Save data for all banks across all devices. - */ -static int samsung_pinctrl_suspend(void) -{ - struct samsung_pinctrl_drv_data *drvdata; - - list_for_each_entry(drvdata, &drvdata_list, node) { - samsung_pinctrl_suspend_dev(drvdata); - } + if (drvdata->retention_ctrl && drvdata->retention_ctrl->disable) + drvdata->retention_ctrl->disable(drvdata); return 0; } - -/** - * samsung_pinctrl_resume - restore pinctrl state for suspend - * - * Restore data for all banks across all devices. - */ -static void samsung_pinctrl_resume(void) -{ - struct samsung_pinctrl_drv_data *drvdata; - - list_for_each_entry_reverse(drvdata, &drvdata_list, node) { - samsung_pinctrl_resume_dev(drvdata); - } -} - -#else -#define samsung_pinctrl_suspend NULL -#define samsung_pinctrl_resume NULL #endif -static struct syscore_ops samsung_pinctrl_syscore_ops = { - .suspend = samsung_pinctrl_suspend, - .resume = samsung_pinctrl_resume, -}; - static const struct of_device_id samsung_pinctrl_dt_match[] = { #ifdef CONFIG_PINCTRL_EXYNOS { .compatible = "samsung,exynos3250-pinctrl", @@ -1238,8 +1193,6 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = (void *)exynos4210_pin_ctrl }, { .compatible = "samsung,exynos4x12-pinctrl", .data = (void *)exynos4x12_pin_ctrl }, - { .compatible = "samsung,exynos4415-pinctrl", - .data = (void *)exynos4415_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", .data = (void *)exynos5250_pin_ctrl }, { .compatible = "samsung,exynos5260-pinctrl", @@ -1273,25 +1226,23 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { }; MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); +static const struct dev_pm_ops samsung_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(samsung_pinctrl_suspend, + samsung_pinctrl_resume) +}; + static struct platform_driver samsung_pinctrl_driver = { .probe = samsung_pinctrl_probe, .driver = { .name = "samsung-pinctrl", .of_match_table = samsung_pinctrl_dt_match, .suppress_bind_attrs = true, + .pm = &samsung_pinctrl_pm_ops, }, }; static int __init samsung_pinctrl_drv_register(void) { - /* - * Register syscore ops for save/restore of registers across suspend. - * It's important to ensure that this driver is running at an earlier - * initcall level than any arch-specific init calls that install syscore - * ops that turn off pad retention (like exynos_pm_resume). - */ - register_syscore_ops(&samsung_pinctrl_syscore_ops); - return platform_driver_register(&samsung_pinctrl_driver); } postcore_initcall(samsung_pinctrl_drv_register); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 043cb6c11180..515a61035e54 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -185,10 +185,48 @@ struct samsung_pin_bank { }; /** + * struct samsung_retention_data: runtime pin-bank retention control data. + * @regs: array of PMU registers to control pad retention. + * @nr_regs: number of registers in @regs array. + * @value: value to store to registers to turn off retention. + * @refcnt: atomic counter if retention control affects more than one bank. + * @priv: retention control code private data + * @enable: platform specific callback to enter retention mode. + * @disable: platform specific callback to exit retention mode. + **/ +struct samsung_retention_ctrl { + const u32 *regs; + int nr_regs; + u32 value; + atomic_t *refcnt; + void *priv; + void (*enable)(struct samsung_pinctrl_drv_data *); + void (*disable)(struct samsung_pinctrl_drv_data *); +}; + +/** + * struct samsung_retention_data: represent a pin-bank retention control data. + * @regs: array of PMU registers to control pad retention. + * @nr_regs: number of registers in @regs array. + * @value: value to store to registers to turn off retention. + * @refcnt: atomic counter if retention control affects more than one bank. + * @init: platform specific callback to initialize retention control. + **/ +struct samsung_retention_data { + const u32 *regs; + int nr_regs; + u32 value; + atomic_t *refcnt; + struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *, + const struct samsung_retention_data *); +}; + +/** * struct samsung_pin_ctrl: represent a pin controller. * @pin_banks: list of pin banks included in this controller. * @nr_banks: number of pin banks. * @nr_ext_resources: number of the extra base address for pin banks. + * @retention_data: configuration data for retention control. * @eint_gpio_init: platform specific callback to setup the external gpio * interrupts for the controller. * @eint_wkup_init: platform specific callback to setup the external wakeup @@ -198,6 +236,7 @@ struct samsung_pin_ctrl { const struct samsung_pin_bank_data *pin_banks; u32 nr_banks; int nr_ext_resources; + const struct samsung_retention_data *retention_data; int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); @@ -219,6 +258,7 @@ struct samsung_pin_ctrl { * @nr_function: number of such pin functions. * @pin_base: starting system wide pin number. * @nr_pins: number of pins supported by the controller. + * @retention_ctrl: retention control runtime data. */ struct samsung_pinctrl_drv_data { struct list_head node; @@ -238,6 +278,8 @@ struct samsung_pinctrl_drv_data { unsigned int pin_base; unsigned int nr_pins; + struct samsung_retention_ctrl *retention_ctrl; + void (*suspend)(struct samsung_pinctrl_drv_data *); void (*resume)(struct samsung_pinctrl_drv_data *); }; @@ -273,7 +315,6 @@ struct samsung_pmx_func { extern const struct samsung_pin_ctrl exynos3250_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos4210_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; -extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[]; extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[]; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 7ca37c3019ab..841cecdca7ea 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1691,6 +1691,72 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - ADI -------------------------------------------------------------------- */ +static const unsigned int adi_common_pins[] = { + /* ADIDATA, ADICS/SAMP, ADICLK */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), +}; +static const unsigned int adi_common_mux[] = { + /* ADIDATA, ADICS/SAMP, ADICLK */ + ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK, +}; +static const unsigned int adi_chsel0_pins[] = { + /* ADICHS 0 */ + RCAR_GP_PIN(6, 27), +}; +static const unsigned int adi_chsel0_mux[] = { + /* ADICHS 0 */ + ADICHS0_MARK, +}; +static const unsigned int adi_chsel1_pins[] = { + /* ADICHS 1 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int adi_chsel1_mux[] = { + /* ADICHS 1 */ + ADICHS1_MARK, +}; +static const unsigned int adi_chsel2_pins[] = { + /* ADICHS 2 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int adi_chsel2_mux[] = { + /* ADICHS 2 */ + ADICHS2_MARK, +}; +static const unsigned int adi_common_b_pins[] = { + /* ADIDATA B, ADICS/SAMP B, ADICLK B */ + RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), +}; +static const unsigned int adi_common_b_mux[] = { + /* ADIDATA B, ADICS/SAMP B, ADICLK B */ + ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK, +}; +static const unsigned int adi_chsel0_b_pins[] = { + /* ADICHS B 0 */ + RCAR_GP_PIN(5, 28), +}; +static const unsigned int adi_chsel0_b_mux[] = { + /* ADICHS B 0 */ + ADICHS0_B_MARK, +}; +static const unsigned int adi_chsel1_b_pins[] = { + /* ADICHS B 1 */ + RCAR_GP_PIN(5, 29), +}; +static const unsigned int adi_chsel1_b_mux[] = { + /* ADICHS B 1 */ + ADICHS1_B_MARK, +}; +static const unsigned int adi_chsel2_b_pins[] = { + /* ADICHS B 2 */ + RCAR_GP_PIN(5, 30), +}; +static const unsigned int adi_chsel2_b_mux[] = { + /* ADICHS B 2 */ + ADICHS2_B_MARK, +}; + /* - Audio Clock ------------------------------------------------------------ */ static const unsigned int audio_clk_a_pins[] = { /* CLK */ @@ -4343,6 +4409,14 @@ static const unsigned int vin2_clk_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(adi_common), + SH_PFC_PIN_GROUP(adi_chsel0), + SH_PFC_PIN_GROUP(adi_chsel1), + SH_PFC_PIN_GROUP(adi_chsel2), + SH_PFC_PIN_GROUP(adi_common_b), + SH_PFC_PIN_GROUP(adi_chsel0_b), + SH_PFC_PIN_GROUP(adi_chsel1_b), + SH_PFC_PIN_GROUP(adi_chsel2_b), SH_PFC_PIN_GROUP(audio_clk_a), SH_PFC_PIN_GROUP(audio_clk_b), SH_PFC_PIN_GROUP(audio_clk_b_b), @@ -4687,6 +4761,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin2_clk), }; +static const char * const adi_groups[] = { + "adi_common", + "adi_chsel0", + "adi_chsel1", + "adi_chsel2", + "adi_common_b", + "adi_chsel0_b", + "adi_chsel1_b", + "adi_chsel2_b", +}; + static const char * const audio_clk_groups[] = { "audio_clk_a", "audio_clk_b", @@ -5192,6 +5277,7 @@ static const char * const vin2_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(adi), SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(can0), @@ -6455,6 +6541,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7793 const struct sh_pfc_soc_info r8a7793_pinmux_info = { .name = "r8a77930_pfc", + .ops = &r8a7791_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 135ed5cbeb44..504d0c3d7f74 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -538,7 +538,7 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ FM(CLKOUT) FM(PRESETOUT) \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ - FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) + FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) enum { PINMUX_RESERVED = 0, @@ -1461,46 +1461,50 @@ static const struct sh_pfc_pin pinmux_pins[] = { * number for each pin. To this end use the pin layout from * R-Car H3SiP to calculate a unique number for each pin. */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -5415,167 +5419,211 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc #define PU6 0x18 static const struct sh_pfc_bias_info bias_info[] = { - { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ - { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ - - { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ - { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ - { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ - { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ - { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ - { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ - { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ - { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ - { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ - { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ - { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ - { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ - { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ - { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ - { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ - { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ - { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ - { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ - { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ - { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ - { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ - { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ - { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ - { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ - { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ - { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ - { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ - - { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ - { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ - { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ - { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ - { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ - { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ - { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ - { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ - { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ - { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ - { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ - { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ - { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ - { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ - { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ - { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ - { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ - { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ - { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ - { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ - { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ - { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ - { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ - { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ - { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ - { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ - - { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ - { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ - { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ - { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ - { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ - - { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ - { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ - { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ - { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ - { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ - { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ - { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ - { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ - { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ - { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ - { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ - { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ - { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ - { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ - { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ - { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ - { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ - { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ - { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ - { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ - { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ - - { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ - { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ - { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ - { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ - { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ - { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ - { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ - { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ - { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ - { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ - { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ - { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ - - { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ - { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ - { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ + { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ + { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ + { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ + { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ + { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ + { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ + { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ + { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ + { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ + { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ + { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ + { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ + { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ + { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ + { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ + { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ + { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ + { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ + { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ + { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ + { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ + { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ + { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ + { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ + { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ + { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ + { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ + { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ + + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ + + { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ + { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ + { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ + { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ + + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ + { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ + /* bit 8 n/a */ + { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ + { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ + { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ + { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ + { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ + { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ + { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ + { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ + + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ + + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ + { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ + + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ }; static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 7e16545a2c3c..b0362ae707e2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -19,19 +19,23 @@ #include "core.h" #include "sh_pfc.h" +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ + SH_PFC_PIN_CFG_PULL_UP | \ + SH_PFC_PIN_CFG_PULL_DOWN) + #define CPU_ALL_PORT(fn, sfx) \ - PORT_GP_16(0, fn, sfx), \ - PORT_GP_29(1, fn, sfx), \ - PORT_GP_15(2, fn, sfx), \ - PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(3, 12, fn, sfx), \ - PORT_GP_1(3, 13, fn, sfx), \ - PORT_GP_1(3, 14, fn, sfx), \ - PORT_GP_1(3, 15, fn, sfx), \ - PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_26(5, fn, sfx), \ - PORT_GP_32(6, fn, sfx), \ - PORT_GP_4(7, fn, sfx) + PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -541,6 +545,23 @@ MOD_SEL0_2 MOD_SEL1_2 \ MOD_SEL1_1 \ MOD_SEL1_0 MOD_SEL2_0 +/* + * These pins are not able to be muxed but have other properties + * that can be set, such as drive-strength or pull-up/pull-down enable. + */ +#define PINMUX_STATIC \ + FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ + FM(QSPI0_IO2) FM(QSPI0_IO3) \ + FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ + FM(QSPI1_IO2) FM(QSPI1_IO3) \ + FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ + FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ + FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ + FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ + FM(PRESETOUT) \ + FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ + FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) + enum { PINMUX_RESERVED = 0, @@ -565,6 +586,7 @@ enum { PINMUX_GPSR PINMUX_IPSR PINMUX_MOD_SELS + PINMUX_STATIC PINMUX_MARK_END, #undef F_ #undef FM @@ -1484,10 +1506,80 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), + +/* + * Static pins can not be muxed between different functions but + * still needs a mark entry in the pinmux list. Add each static + * pin to the list without an associated function. The sh-pfc + * core will do the right thing and skip trying to mux then pin + * while still applying configuration to it + */ +#define FM(x) PINMUX_DATA(x##_MARK, 0), + PINMUX_STATIC +#undef FM }; +/* + * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs. + * Physical layout rows: A - AW, cols: 1 - 39. + */ +#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) +#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) +#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + + /* + * Pins not associated with a GPIO port. + * + * The pin positions are different between different r8a7796 + * packages, all that is needed for the pfc driver is a unique + * number for each pin. To this end use the pin layout from + * R-Car M3SiP to calculate a unique number for each pin. + */ + SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; /* - EtherAVB --------------------------------------------------------------- */ @@ -1555,6 +1647,61 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - CAN ------------------------------------------------------------------ */ +static const unsigned int can0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int can0_data_a_mux[] = { + CAN0_TX_A_MARK, CAN0_RX_A_MARK, +}; +static const unsigned int can0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int can0_data_b_mux[] = { + CAN0_TX_B_MARK, CAN0_RX_B_MARK, +}; +static const unsigned int can1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; +static const unsigned int can1_data_mux[] = { + CAN1_TX_MARK, CAN1_RX_MARK, +}; + +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +/* - CAN FD --------------------------------------------------------------- */ +static const unsigned int canfd0_data_a_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int canfd0_data_a_mux[] = { + CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, +}; +static const unsigned int canfd0_data_b_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +}; +static const unsigned int canfd0_data_b_mux[] = { + CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, +}; +static const unsigned int canfd1_data_pins[] = { + /* TX, RX */ + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -1851,6 +1998,213 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; +static const unsigned int hscif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; +static const unsigned int hscif1_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif1_ctrl_a_mux[] = { + HRTS1_N_A_MARK, HCTS1_N_A_MARK, +}; + +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int hscif2_data_a_mux[] = { + HRX2_A_MARK, HTX2_A_MARK, +}; +static const unsigned int hscif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int hscif2_clk_a_mux[] = { + HSCK2_A_MARK, +}; +static const unsigned int hscif2_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +}; +static const unsigned int hscif2_ctrl_a_mux[] = { + HRTS2_N_A_MARK, HCTS2_N_A_MARK, +}; + +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; +static const unsigned int hscif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif2_clk_b_mux[] = { + HSCK2_B_MARK, +}; +static const unsigned int hscif2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), +}; +static const unsigned int hscif2_ctrl_b_mux[] = { + HRTS2_N_B_MARK, HCTS2_N_B_MARK, +}; + +static const unsigned int hscif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), +}; +static const unsigned int hscif2_data_c_mux[] = { + HRX2_C_MARK, HTX2_C_MARK, +}; +static const unsigned int hscif2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 24), +}; +static const unsigned int hscif2_clk_c_mux[] = { + HSCK2_C_MARK, +}; +static const unsigned int hscif2_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), +}; +static const unsigned int hscif2_ctrl_c_mux[] = { + HRTS2_N_C_MARK, HCTS2_N_C_MARK, +}; +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +static const unsigned int hscif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; +static const unsigned int hscif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int hscif3_data_c_mux[] = { + HRX3_C_MARK, HTX3_C_MARK, +}; +static const unsigned int hscif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; +static const unsigned int hscif3_data_d_mux[] = { + HRX3_D_MARK, HTX3_D_MARK, +}; +/* - HSCIF4 ----------------------------------------------------------------- */ +static const unsigned int hscif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), +}; +static const unsigned int hscif4_data_a_mux[] = { + HRX4_A_MARK, HTX4_A_MARK, +}; +static const unsigned int hscif4_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_clk_mux[] = { + HSCK4_MARK, +}; +static const unsigned int hscif4_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int hscif4_ctrl_mux[] = { + HRTS4_N_MARK, HCTS4_N_MARK, +}; + +static const unsigned int hscif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_data_b_mux[] = { + HRX4_B_MARK, HTX4_B_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ @@ -1902,6 +2256,705 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 22), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 8), +}; +static const unsigned int msiof1_clk_a_mux[] = { + MSIOF1_SCK_A_MARK, +}; +static const unsigned int msiof1_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(6, 9), +}; +static const unsigned int msiof1_sync_a_mux[] = { + MSIOF1_SYNC_A_MARK, +}; +static const unsigned int msiof1_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 5), +}; +static const unsigned int msiof1_ss1_a_mux[] = { + MSIOF1_SS1_A_MARK, +}; +static const unsigned int msiof1_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 6), +}; +static const unsigned int msiof1_ss2_a_mux[] = { + MSIOF1_SS2_A_MARK, +}; +static const unsigned int msiof1_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int msiof1_txd_a_mux[] = { + MSIOF1_TXD_A_MARK, +}; +static const unsigned int msiof1_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int msiof1_rxd_a_mux[] = { + MSIOF1_RXD_A_MARK, +}; +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int msiof1_sync_b_mux[] = { + MSIOF1_SYNC_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 8), +}; +static const unsigned int msiof1_txd_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; +static const unsigned int msiof1_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int msiof1_rxd_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 17), +}; +static const unsigned int msiof1_clk_c_mux[] = { + MSIOF1_SCK_C_MARK, +}; +static const unsigned int msiof1_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int msiof1_sync_c_mux[] = { + MSIOF1_SYNC_C_MARK, +}; +static const unsigned int msiof1_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int msiof1_ss1_c_mux[] = { + MSIOF1_SS1_C_MARK, +}; +static const unsigned int msiof1_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 27), +}; +static const unsigned int msiof1_ss2_c_mux[] = { + MSIOF1_SS2_C_MARK, +}; +static const unsigned int msiof1_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int msiof1_txd_c_mux[] = { + MSIOF1_TXD_C_MARK, +}; +static const unsigned int msiof1_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int msiof1_rxd_c_mux[] = { + MSIOF1_RXD_C_MARK, +}; +static const unsigned int msiof1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int msiof1_clk_d_mux[] = { + MSIOF1_SCK_D_MARK, +}; +static const unsigned int msiof1_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int msiof1_sync_d_mux[] = { + MSIOF1_SYNC_D_MARK, +}; +static const unsigned int msiof1_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int msiof1_ss1_d_mux[] = { + MSIOF1_SS1_D_MARK, +}; +static const unsigned int msiof1_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int msiof1_ss2_d_mux[] = { + MSIOF1_SS2_D_MARK, +}; +static const unsigned int msiof1_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int msiof1_txd_d_mux[] = { + MSIOF1_TXD_D_MARK, +}; +static const unsigned int msiof1_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int msiof1_rxd_d_mux[] = { + MSIOF1_RXD_D_MARK, +}; +static const unsigned int msiof1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int msiof1_clk_e_mux[] = { + MSIOF1_SCK_E_MARK, +}; +static const unsigned int msiof1_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int msiof1_sync_e_mux[] = { + MSIOF1_SYNC_E_MARK, +}; +static const unsigned int msiof1_ss1_e_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 4), +}; +static const unsigned int msiof1_ss1_e_mux[] = { + MSIOF1_SS1_E_MARK, +}; +static const unsigned int msiof1_ss2_e_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int msiof1_ss2_e_mux[] = { + MSIOF1_SS2_E_MARK, +}; +static const unsigned int msiof1_txd_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 3), +}; +static const unsigned int msiof1_txd_e_mux[] = { + MSIOF1_TXD_E_MARK, +}; +static const unsigned int msiof1_rxd_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int msiof1_rxd_e_mux[] = { + MSIOF1_RXD_E_MARK, +}; +static const unsigned int msiof1_clk_f_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 23), +}; +static const unsigned int msiof1_clk_f_mux[] = { + MSIOF1_SCK_F_MARK, +}; +static const unsigned int msiof1_sync_f_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 24), +}; +static const unsigned int msiof1_sync_f_mux[] = { + MSIOF1_SYNC_F_MARK, +}; +static const unsigned int msiof1_ss1_f_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 1), +}; +static const unsigned int msiof1_ss1_f_mux[] = { + MSIOF1_SS1_F_MARK, +}; +static const unsigned int msiof1_ss2_f_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int msiof1_ss2_f_mux[] = { + MSIOF1_SS2_F_MARK, +}; +static const unsigned int msiof1_txd_f_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 0), +}; +static const unsigned int msiof1_txd_f_mux[] = { + MSIOF1_TXD_F_MARK, +}; +static const unsigned int msiof1_rxd_f_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 25), +}; +static const unsigned int msiof1_rxd_f_mux[] = { + MSIOF1_RXD_F_MARK, +}; +static const unsigned int msiof1_clk_g_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int msiof1_clk_g_mux[] = { + MSIOF1_SCK_G_MARK, +}; +static const unsigned int msiof1_sync_g_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int msiof1_sync_g_mux[] = { + MSIOF1_SYNC_G_MARK, +}; +static const unsigned int msiof1_ss1_g_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int msiof1_ss1_g_mux[] = { + MSIOF1_SS1_G_MARK, +}; +static const unsigned int msiof1_ss2_g_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int msiof1_ss2_g_mux[] = { + MSIOF1_SS2_G_MARK, +}; +static const unsigned int msiof1_txd_g_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int msiof1_txd_g_mux[] = { + MSIOF1_TXD_G_MARK, +}; +static const unsigned int msiof1_rxd_g_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int msiof1_rxd_g_mux[] = { + MSIOF1_RXD_G_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 9), +}; +static const unsigned int msiof2_clk_a_mux[] = { + MSIOF2_SCK_A_MARK, +}; +static const unsigned int msiof2_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int msiof2_sync_a_mux[] = { + MSIOF2_SYNC_A_MARK, +}; +static const unsigned int msiof2_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof2_ss1_a_mux[] = { + MSIOF2_SS1_A_MARK, +}; +static const unsigned int msiof2_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof2_ss2_a_mux[] = { + MSIOF2_SS2_A_MARK, +}; +static const unsigned int msiof2_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int msiof2_txd_a_mux[] = { + MSIOF2_TXD_A_MARK, +}; +static const unsigned int msiof2_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof2_rxd_a_mux[] = { + MSIOF2_RXD_A_MARK, +}; +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; +static const unsigned int msiof2_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int msiof2_txd_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; +static const unsigned int msiof2_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int msiof2_rxd_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; +static const unsigned int msiof2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int msiof2_clk_c_mux[] = { + MSIOF2_SCK_C_MARK, +}; +static const unsigned int msiof2_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int msiof2_sync_c_mux[] = { + MSIOF2_SYNC_C_MARK, +}; +static const unsigned int msiof2_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int msiof2_ss1_c_mux[] = { + MSIOF2_SS1_C_MARK, +}; +static const unsigned int msiof2_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(2, 9), +}; +static const unsigned int msiof2_ss2_c_mux[] = { + MSIOF2_SS2_C_MARK, +}; +static const unsigned int msiof2_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int msiof2_txd_c_mux[] = { + MSIOF2_TXD_C_MARK, +}; +static const unsigned int msiof2_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int msiof2_rxd_c_mux[] = { + MSIOF2_RXD_C_MARK, +}; +static const unsigned int msiof2_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int msiof2_clk_d_mux[] = { + MSIOF2_SCK_D_MARK, +}; +static const unsigned int msiof2_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 9), +}; +static const unsigned int msiof2_sync_d_mux[] = { + MSIOF2_SYNC_D_MARK, +}; +static const unsigned int msiof2_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int msiof2_ss1_d_mux[] = { + MSIOF2_SS1_D_MARK, +}; +static const unsigned int msiof2_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int msiof2_ss2_d_mux[] = { + MSIOF2_SS2_D_MARK, +}; +static const unsigned int msiof2_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int msiof2_txd_d_mux[] = { + MSIOF2_TXD_D_MARK, +}; +static const unsigned int msiof2_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int msiof2_rxd_d_mux[] = { + MSIOF2_RXD_D_MARK, +}; +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof3_clk_a_mux[] = { + MSIOF3_SCK_A_MARK, +}; +static const unsigned int msiof3_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_sync_a_mux[] = { + MSIOF3_SYNC_A_MARK, +}; +static const unsigned int msiof3_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int msiof3_ss1_a_mux[] = { + MSIOF3_SS1_A_MARK, +}; +static const unsigned int msiof3_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int msiof3_ss2_a_mux[] = { + MSIOF3_SS2_A_MARK, +}; +static const unsigned int msiof3_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_txd_a_mux[] = { + MSIOF3_TXD_A_MARK, +}; +static const unsigned int msiof3_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_rxd_a_mux[] = { + MSIOF3_RXD_A_MARK, +}; +static const unsigned int msiof3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof3_clk_b_mux[] = { + MSIOF3_SCK_B_MARK, +}; +static const unsigned int msiof3_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int msiof3_sync_b_mux[] = { + MSIOF3_SYNC_B_MARK, +}; +static const unsigned int msiof3_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int msiof3_ss1_b_mux[] = { + MSIOF3_SS1_B_MARK, +}; +static const unsigned int msiof3_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int msiof3_ss2_b_mux[] = { + MSIOF3_SS2_B_MARK, +}; +static const unsigned int msiof3_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int msiof3_txd_b_mux[] = { + MSIOF3_TXD_B_MARK, +}; +static const unsigned int msiof3_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof3_rxd_b_mux[] = { + MSIOF3_RXD_B_MARK, +}; +static const unsigned int msiof3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 12), +}; +static const unsigned int msiof3_clk_c_mux[] = { + MSIOF3_SCK_C_MARK, +}; +static const unsigned int msiof3_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int msiof3_sync_c_mux[] = { + MSIOF3_SYNC_C_MARK, +}; +static const unsigned int msiof3_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int msiof3_txd_c_mux[] = { + MSIOF3_TXD_C_MARK, +}; +static const unsigned int msiof3_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int msiof3_rxd_c_mux[] = { + MSIOF3_RXD_C_MARK, +}; +static const unsigned int msiof3_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int msiof3_clk_d_mux[] = { + MSIOF3_SCK_D_MARK, +}; +static const unsigned int msiof3_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof3_sync_d_mux[] = { + MSIOF3_SYNC_D_MARK, +}; +static const unsigned int msiof3_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int msiof3_ss1_d_mux[] = { + MSIOF3_SS1_D_MARK, +}; +static const unsigned int msiof3_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int msiof3_txd_d_mux[] = { + MSIOF3_TXD_D_MARK, +}; +static const unsigned int msiof3_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int msiof3_rxd_d_mux[] = { + MSIOF3_RXD_D_MARK, +}; + +static const unsigned int msiof3_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int msiof3_clk_e_mux[] = { + MSIOF3_SCK_E_MARK, +}; +static const unsigned int msiof3_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int msiof3_sync_e_mux[] = { + MSIOF3_SYNC_E_MARK, +}; +static const unsigned int msiof3_ss1_e_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int msiof3_ss1_e_mux[] = { + MSIOF3_SS1_E_MARK, +}; +static const unsigned int msiof3_ss2_e_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int msiof3_ss2_e_mux[] = { + MSIOF3_SS1_E_MARK, +}; +static const unsigned int msiof3_txd_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int msiof3_txd_e_mux[] = { + MSIOF3_TXD_E_MARK, +}; +static const unsigned int msiof3_rxd_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int msiof3_rxd_e_mux[] = { + MSIOF3_RXD_E_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -2333,6 +3386,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -2371,6 +3431,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_clk_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk), + SH_PFC_PIN_GROUP(hscif4_ctrl), + SH_PFC_PIN_GROUP(hscif4_data_b), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), @@ -2378,6 +3466,105 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk_a), + SH_PFC_PIN_GROUP(msiof1_sync_a), + SH_PFC_PIN_GROUP(msiof1_ss1_a), + SH_PFC_PIN_GROUP(msiof1_ss2_a), + SH_PFC_PIN_GROUP(msiof1_txd_a), + SH_PFC_PIN_GROUP(msiof1_rxd_a), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_txd_b), + SH_PFC_PIN_GROUP(msiof1_rxd_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_ss1_c), + SH_PFC_PIN_GROUP(msiof1_ss2_c), + SH_PFC_PIN_GROUP(msiof1_txd_c), + SH_PFC_PIN_GROUP(msiof1_rxd_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_ss2_d), + SH_PFC_PIN_GROUP(msiof1_txd_d), + SH_PFC_PIN_GROUP(msiof1_rxd_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_ss1_e), + SH_PFC_PIN_GROUP(msiof1_ss2_e), + SH_PFC_PIN_GROUP(msiof1_txd_e), + SH_PFC_PIN_GROUP(msiof1_rxd_e), + SH_PFC_PIN_GROUP(msiof1_clk_f), + SH_PFC_PIN_GROUP(msiof1_sync_f), + SH_PFC_PIN_GROUP(msiof1_ss1_f), + SH_PFC_PIN_GROUP(msiof1_ss2_f), + SH_PFC_PIN_GROUP(msiof1_txd_f), + SH_PFC_PIN_GROUP(msiof1_rxd_f), + SH_PFC_PIN_GROUP(msiof1_clk_g), + SH_PFC_PIN_GROUP(msiof1_sync_g), + SH_PFC_PIN_GROUP(msiof1_ss1_g), + SH_PFC_PIN_GROUP(msiof1_ss2_g), + SH_PFC_PIN_GROUP(msiof1_txd_g), + SH_PFC_PIN_GROUP(msiof1_rxd_g), + SH_PFC_PIN_GROUP(msiof2_clk_a), + SH_PFC_PIN_GROUP(msiof2_sync_a), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_txd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_txd_b), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_ss1_c), + SH_PFC_PIN_GROUP(msiof2_ss2_c), + SH_PFC_PIN_GROUP(msiof2_txd_c), + SH_PFC_PIN_GROUP(msiof2_rxd_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_txd_d), + SH_PFC_PIN_GROUP(msiof2_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_a), + SH_PFC_PIN_GROUP(msiof3_sync_a), + SH_PFC_PIN_GROUP(msiof3_ss1_a), + SH_PFC_PIN_GROUP(msiof3_ss2_a), + SH_PFC_PIN_GROUP(msiof3_txd_a), + SH_PFC_PIN_GROUP(msiof3_rxd_a), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_ss1_b), + SH_PFC_PIN_GROUP(msiof3_ss2_b), + SH_PFC_PIN_GROUP(msiof3_txd_b), + SH_PFC_PIN_GROUP(msiof3_rxd_b), + SH_PFC_PIN_GROUP(msiof3_clk_c), + SH_PFC_PIN_GROUP(msiof3_sync_c), + SH_PFC_PIN_GROUP(msiof3_txd_c), + SH_PFC_PIN_GROUP(msiof3_rxd_c), + SH_PFC_PIN_GROUP(msiof3_clk_d), + SH_PFC_PIN_GROUP(msiof3_sync_d), + SH_PFC_PIN_GROUP(msiof3_ss1_d), + SH_PFC_PIN_GROUP(msiof3_txd_d), + SH_PFC_PIN_GROUP(msiof3_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_e), + SH_PFC_PIN_GROUP(msiof3_sync_e), + SH_PFC_PIN_GROUP(msiof3_ss1_e), + SH_PFC_PIN_GROUP(msiof3_ss2_e), + SH_PFC_PIN_GROUP(msiof3_txd_e), + SH_PFC_PIN_GROUP(msiof3_rxd_e), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -2447,6 +3634,28 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const can0_groups[] = { + "can0_data_a", + "can0_data_b", +}; + +static const char * const can1_groups[] = { + "can1_data", +}; + +static const char * const can_clk_groups[] = { + "can_clk", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data_a", + "canfd0_data_b", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -2500,6 +3709,49 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_ctrl_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data_a", + "hscif2_clk_a", + "hscif2_ctrl_a", + "hscif2_data_b", + "hscif2_clk_b", + "hscif2_ctrl_b", + "hscif2_data_c", + "hscif2_clk_c", + "hscif2_ctrl_c", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_clk", + "hscif3_ctrl", + "hscif3_data_b", + "hscif3_data_c", + "hscif3_data_d", +}; + +static const char * const hscif4_groups[] = { + "hscif4_data_a", + "hscif4_clk", + "hscif4_ctrl", + "hscif4_data_b", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -2516,6 +3768,117 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk_a", + "msiof1_sync_a", + "msiof1_ss1_a", + "msiof1_ss2_a", + "msiof1_txd_a", + "msiof1_rxd_a", + "msiof1_clk_b", + "msiof1_sync_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_txd_b", + "msiof1_rxd_b", + "msiof1_clk_c", + "msiof1_sync_c", + "msiof1_ss1_c", + "msiof1_ss2_c", + "msiof1_txd_c", + "msiof1_rxd_c", + "msiof1_clk_d", + "msiof1_sync_d", + "msiof1_ss1_d", + "msiof1_ss2_d", + "msiof1_txd_d", + "msiof1_rxd_d", + "msiof1_clk_e", + "msiof1_sync_e", + "msiof1_ss1_e", + "msiof1_ss2_e", + "msiof1_txd_e", + "msiof1_rxd_e", + "msiof1_clk_f", + "msiof1_sync_f", + "msiof1_ss1_f", + "msiof1_ss2_f", + "msiof1_txd_f", + "msiof1_rxd_f", + "msiof1_clk_g", + "msiof1_sync_g", + "msiof1_ss1_g", + "msiof1_ss2_g", + "msiof1_txd_g", + "msiof1_rxd_g", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk_a", + "msiof2_sync_a", + "msiof2_ss1_a", + "msiof2_ss2_a", + "msiof2_txd_a", + "msiof2_rxd_a", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_txd_b", + "msiof2_rxd_b", + "msiof2_clk_c", + "msiof2_sync_c", + "msiof2_ss1_c", + "msiof2_ss2_c", + "msiof2_txd_c", + "msiof2_rxd_c", + "msiof2_clk_d", + "msiof2_sync_d", + "msiof2_ss1_d", + "msiof2_ss2_d", + "msiof2_txd_d", + "msiof2_rxd_d", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_ss2_b", + "msiof3_txd_b", + "msiof3_rxd_b", + "msiof3_clk_c", + "msiof3_sync_c", + "msiof3_txd_c", + "msiof3_rxd_c", + "msiof3_clk_d", + "msiof3_sync_d", + "msiof3_ss1_d", + "msiof3_txd_d", + "msiof3_rxd_d", + "msiof3_clk_e", + "msiof3_sync_e", + "msiof3_ss1_e", + "msiof3_ss2_e", + "msiof3_txd_e", + "msiof3_rxd_e", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -2606,14 +3969,28 @@ static const char * const sdhi3_groups[] = { static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -3187,6 +4564,254 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { + { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ + { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ + { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ + { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ + { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ + { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { + { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ + { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ + { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ + { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ + { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ + { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ + { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { + { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ + { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ + { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ + { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ + { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ + { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ + { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ + { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { + { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ + { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ + { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ + { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { + { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ + { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ + { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ + { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { + { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ + { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ + { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ + { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ + { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ + { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ + { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ + { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { + { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ + { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ + { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ + { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ + { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ + { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ + { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ + { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { + { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ + { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ + { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ + { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ + { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ + { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ + { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ + { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { + { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ + { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ + { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ + { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ + { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ + { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ + { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { + { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ + { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ + { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ + { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ + { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ + { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ + { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { + { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ + { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ + { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ + { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ + { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ + { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ + { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ + { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { + { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ + { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { + { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ + { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { + { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ + { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ + { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { + { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ + { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ + { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ + { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ + { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ + { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { + { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ + { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ + { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { + { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ + { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ + { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ + { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ + { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ + { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ + { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ + { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { + { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ + { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ + { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ + { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ + { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ + { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ + { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ + { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { + { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ + { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ + { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ + { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ + { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { + { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ + { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ + { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ + { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { + { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ + { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ + { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ + { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ + { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */ + { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */ + { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ + { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { + { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ + { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ + { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ + { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ + { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ + { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ + { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ + { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { + { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ + { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ + { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ + { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ + { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ + { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ + { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ + { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { + { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ + { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ + { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ + { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ + { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ + { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ + { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ + } }, + { }, +}; + static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -3202,8 +4827,278 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return bit; } +#define PUEN 0xe6060400 +#define PUD 0xe6060440 + +#define PU0 0x00 +#define PU1 0x04 +#define PU2 0x08 +#define PU3 0x0c +#define PU4 0x10 +#define PU5 0x14 +#define PU6 0x18 + +static const struct sh_pfc_bias_info bias_info[] = { + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ + { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ + { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ + { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ + { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ + { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ + { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ + { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ + { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ + { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ + { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ + { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ + { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ + { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ + { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ + { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ + { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ + { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ + { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ + { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ + { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ + { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ + { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ + { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ + { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ + { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ + { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ + { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ + { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ + + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ + + { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ + { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */ + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ + { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ + { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ + + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ + { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ + /* bit 8 n/a */ + { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ + { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ + { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ + { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ + { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ + { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */ + /* bit 1 n/a on M3*/ + { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */ + + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ + + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ + { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ + + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */ + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */ + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ +}; + +static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + const struct sh_pfc_bias_info *info; + u32 reg; + u32 bit; + + info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); + if (!info) + return PIN_CONFIG_BIAS_DISABLE; + + reg = info->reg; + bit = BIT(info->bit); + + if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct sh_pfc_bias_info *info; + u32 enable, updown; + u32 reg; + u32 bit; + + info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); + if (!info) + return; + + reg = info->reg; + bit = BIT(info->bit); + + enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= bit; + + updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= bit; + + sh_pfc_write_reg(pfc, PUD + reg, 32, updown); + sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); +} + static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { .pin_to_pocctrl = r8a7796_pin_to_pocctrl, + .get_bias = r8a7796_pinmux_get_bias, + .set_bias = r8a7796_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7796_pinmux_info = { @@ -3221,6 +5116,7 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index fcacfa73ef6e..08150a321be6 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -816,6 +816,6 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) pmx->pctl_desc.pins = pmx->pins; pmx->pctl_desc.npins = pfc->info->nr_pins; - pmx->pctl = devm_pinctrl_register(pfc->dev, &pmx->pctl_desc, pmx); - return PTR_ERR_OR_ZERO(pmx->pctl); + return devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx, + &pmx->pctl); } diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 82b8a429743d..600d6427a978 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -5421,14 +5421,15 @@ static int atlas7_pinmux_probe(struct platform_device *pdev) sys2pci_np = of_find_node_by_name(NULL, "sys2pci"); if (!sys2pci_np) return -EINVAL; + ret = of_address_to_resource(sys2pci_np, 0, &res); + of_node_put(sys2pci_np); if (ret) return ret; + pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res); - if (IS_ERR(pmx->sys2pci_base)) { - of_node_put(sys2pci_np); + if (IS_ERR(pmx->sys2pci_base)) return -ENOMEM; - } pmx->dev = &pdev->dev; @@ -5444,7 +5445,7 @@ static int atlas7_pinmux_probe(struct platform_device *pdev) pmx->regs[idx] = of_iomap(np, idx); if (!pmx->regs[idx]) { dev_err(&pdev->dev, - "can't map ioc bank#%d registers\n", idx); + "can't map ioc bank#%d registers\n", idx); ret = -ENOMEM; goto unmap_io; } @@ -6057,8 +6058,8 @@ static int atlas7_gpio_probe(struct platform_device *pdev) ret = gpiochip_add_data(chip, a7gc); if (ret) { dev_err(&pdev->dev, - "%s: error in probe function with status %d\n", - np->name, ret); + "%s: error in probe function with status %d\n", + np->name, ret); goto failed; } diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index efc43711ff5c..abc405be0212 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -236,6 +236,15 @@ static void stm32_gpio_domain_activate(struct irq_domain *d, struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->range.id); + gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); +} + +static void stm32_gpio_domain_deactivate(struct irq_domain *d, + struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = d->host_data; + + gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); } static int stm32_gpio_domain_alloc(struct irq_domain *d, @@ -243,11 +252,9 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d, unsigned int nr_irqs, void *data) { struct stm32_gpio_bank *bank = d->host_data; - struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); struct irq_fwspec *fwspec = data; struct irq_fwspec parent_fwspec; irq_hw_number_t hwirq; - int ret; hwirq = fwspec->param[0]; parent_fwspec.fwnode = d->parent->fwnode; @@ -258,35 +265,15 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d, irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, bank); - ret = gpiochip_lock_as_irq(&bank->gpio_chip, hwirq); - if (ret) { - dev_err(pctl->dev, "Unable to configure STM32 %s%ld as IRQ\n", - bank->gpio_chip.label, hwirq); - return ret; - } - - ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); - if (ret) - gpiochip_unlock_as_irq(&bank->gpio_chip, hwirq); - - return ret; -} - -static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, - unsigned int nr_irqs) -{ - struct stm32_gpio_bank *bank = d->host_data; - struct irq_data *data = irq_get_irq_data(virq); - - irq_domain_free_irqs_common(d, virq, nr_irqs); - gpiochip_unlock_as_irq(&bank->gpio_chip, data->hwirq); + return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); } static const struct irq_domain_ops stm32_gpio_domain_ops = { .translate = stm32_gpio_domain_translate, .alloc = stm32_gpio_domain_alloc, - .free = stm32_gpio_domain_free, + .free = irq_domain_free_irqs_common, .activate = stm32_gpio_domain_activate, + .deactivate = stm32_gpio_domain_deactivate, }; /* Pinctrl functions */ @@ -631,6 +618,7 @@ static const struct pinmux_ops stm32_pmx_ops = { .get_function_groups = stm32_pmx_get_func_groups, .set_mux = stm32_pmx_set_mux, .gpio_set_direction = stm32_pmx_gpio_set_direction, + .strict = true, }; /* Pinconf functions */ diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index bff1ffc6f01e..92d845827577 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -9,18 +9,10 @@ config PINCTRL_SUN4I_A10 def_bool MACH_SUN4I select PINCTRL_SUNXI -config PINCTRL_SUN5I_A10S +config PINCTRL_SUN5I def_bool MACH_SUN5I select PINCTRL_SUNXI -config PINCTRL_SUN5I_A13 - def_bool MACH_SUN5I - select PINCTRL_SUNXI - -config PINCTRL_GR8 - def_bool MACH_SUN5I - select PINCTRL_SUNXI_COMMON - config PINCTRL_SUN6I_A31 def_bool MACH_SUN6I select PINCTRL_SUNXI @@ -63,6 +55,10 @@ config PINCTRL_SUN8I_H3_R def_bool MACH_SUN8I select PINCTRL_SUNXI_COMMON +config PINCTRL_SUN8I_V3S + def_bool MACH_SUN8I + select PINCTRL_SUNXI + config PINCTRL_SUN9I_A80 def_bool MACH_SUN9I select PINCTRL_SUNXI @@ -76,4 +72,8 @@ config PINCTRL_SUN50I_A64 bool select PINCTRL_SUNXI +config PINCTRL_SUN50I_H5 + bool + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 95f93d0561fc..f9a3855c42f1 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -3,9 +3,7 @@ obj-y += pinctrl-sunxi.o # SoC Drivers obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o -obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o -obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o -obj-$(CONFIG_PINCTRL_GR8) += pinctrl-gr8.o +obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o @@ -17,5 +15,7 @@ obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o +obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o +obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-gr8.c b/drivers/pinctrl/sunxi/pinctrl-gr8.c deleted file mode 100644 index 2f232c3a0579..000000000000 --- a/drivers/pinctrl/sunxi/pinctrl-gr8.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * NextThing GR8 SoCs pinctrl driver. - * - * Copyright (C) 2016 Mylene Josserand - * - * Based on pinctrl-sun5i-a13.c - * - * Mylene Josserand <mylene.josserand@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/pinctrl/pinctrl.h> - -#include "pinctrl-sunxi.h" - -static const struct sunxi_desc_pin sun5i_gr8_pins[] = { - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm0"), - SUNXI_FUNCTION(0x3, "spdif"), /* DO */ - SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ - SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ - SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ - SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* DO */ - SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* DI */ - SUNXI_FUNCTION(0x3, "spdif"), /* DI */ - SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ - SUNXI_FUNCTION(0x3, "spdif"), /* DO */ - SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ - SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ - SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ - SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ - SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ - SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ - SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ - SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ - SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ - SUNXI_FUNCTION(0x3, "uart2"), /* RX */ - SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ - SUNXI_FUNCTION(0x3, "uart2")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ - SUNXI_FUNCTION(0x3, "uart2")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ - SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ - SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ - SUNXI_FUNCTION(0x3, "emac")), /* ECRS */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ - SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ - SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ - SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ - SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ - SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ - SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ - SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ - SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ - SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ - SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ - SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ - SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ - SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ - SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ - SUNXI_FUNCTION(0x3, "emac")), /* ETXERR*/ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "emac")), /* EMDC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ - SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ - SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ - SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ - SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ - SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ - SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ - SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ - SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x2, "gps"), /* CLK */ - SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x2, "gps"), /* SIGN */ - SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x2, "gps"), /* MAG */ - SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x3, "ms"), /* BS */ - SUNXI_FUNCTION(0x4, "uart1"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x3, "ms"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart1"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ - SUNXI_FUNCTION(0x3, "ms"), /* D0 */ - SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ - SUNXI_FUNCTION(0x3, "ms"), /* D1 */ - SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ - SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ - SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x3, "ms"), /* D2 */ - SUNXI_FUNCTION(0x5, "uart2"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x3, "ms"), /* D3 */ - SUNXI_FUNCTION(0x5, "uart2"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart3"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart3"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x3, "pwm1"), - SUNXI_FUNCTION(0x5, "uart2"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ -}; - -static const struct sunxi_pinctrl_desc sun5i_gr8_pinctrl_data = { - .pins = sun5i_gr8_pins, - .npins = ARRAY_SIZE(sun5i_gr8_pins), - .irq_banks = 1, -}; - -static int sun5i_gr8_pinctrl_probe(struct platform_device *pdev) -{ - return sunxi_pinctrl_init(pdev, - &sun5i_gr8_pinctrl_data); -} - -static const struct of_device_id sun5i_gr8_pinctrl_match[] = { - { .compatible = "nextthing,gr8-pinctrl", }, - {} -}; - -static struct platform_driver sun5i_gr8_pinctrl_driver = { - .probe = sun5i_gr8_pinctrl_probe, - .driver = { - .name = "gr8-pinctrl", - .of_match_table = sun5i_gr8_pinctrl_match, - }, -}; -builtin_platform_driver(sun5i_gr8_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c new file mode 100644 index 000000000000..ccf9419e9418 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -0,0 +1,558 @@ +/* + * Allwinner H5 SoC pinctrl driver. + * + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * Based on pinctrl-sun8i-h3.c, which is: + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun50i_h5_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "pwm0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sim"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x3, "di"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x3, "di"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS */ + SUNXI_FUNCTION(0x3, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ + SUNXI_FUNCTION(0x4, "mmc2")), /* DS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */ + SUNXI_FUNCTION(0x3, "di"), /* TX */ + SUNXI_FUNCTION(0x4, "ts2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */ + SUNXI_FUNCTION(0x3, "di"), /* RX */ + SUNXI_FUNCTION(0x4, "ts2")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */ + SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */ + SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXCK */ + SUNXI_FUNCTION(0x4, "ts2")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */ + SUNXI_FUNCTION(0x4, "ts2")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* RXERR */ + SUNXI_FUNCTION(0x4, "ts2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D3 */ + SUNXI_FUNCTION(0x5, "ts3")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D4 */ + SUNXI_FUNCTION(0x5, "ts3")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D5 */ + SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */ + SUNXI_FUNCTION(0x4, "ts2"), /* D6 */ + SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* CRS */ + SUNXI_FUNCTION(0x4, "ts2"), /* D7 */ + SUNXI_FUNCTION(0x5, "ts3")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXCK */ + SUNXI_FUNCTION(0x4, "sim")), /* PWREN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */ + SUNXI_FUNCTION(0x4, "sim")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* TXERR */ + SUNXI_FUNCTION(0x4, "sim")), /* DATA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */ + SUNXI_FUNCTION(0x4, "sim")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac"), /* MDC */ + SUNXI_FUNCTION(0x4, "sim")), /* DET */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "ts0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "ts0")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "ts0")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x4, "ts1")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x4, "ts1")), /* ERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "ts"), /* D7 */ + SUNXI_FUNCTION(0x4, "ts1")), /* D0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ +}; + +static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { + .pins = sun50i_h5_pins, + .npins = ARRAY_SIZE(sun50i_h5_pins), + .irq_banks = 2, + .irq_read_needs_mux = true +}; + +static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun50i_h5_pinctrl_data); +} + +static const struct of_device_id sun50i_h5_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-h5-pinctrl", }, + {} +}; + +static struct platform_driver sun50i_h5_pinctrl_driver = { + .probe = sun50i_h5_pinctrl_probe, + .driver = { + .name = "sun50i-h5-pinctrl", + .of_match_table = sun50i_h5_pinctrl_match, + }, +}; +builtin_platform_driver(sun50i_h5_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c deleted file mode 100644 index 8575f3f6d3dd..000000000000 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c +++ /dev/null @@ -1,403 +0,0 @@ -/* - * Allwinner A13 SoCs pinctrl driver. - * - * Copyright (C) 2014 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/pinctrl/pinctrl.h> - -#include "pinctrl-sunxi.h" - -static const struct sunxi_desc_pin sun5i_a13_pins[] = { - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm"), - SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ - SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ - SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ - SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ - SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ - SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ - SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ - SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x4, "uart1"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart1"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart3"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart3"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ - SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ -}; - -static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = { - .pins = sun5i_a13_pins, - .npins = ARRAY_SIZE(sun5i_a13_pins), - .irq_banks = 1, -}; - -static int sun5i_a13_pinctrl_probe(struct platform_device *pdev) -{ - return sunxi_pinctrl_init(pdev, - &sun5i_a13_pinctrl_data); -} - -static const struct of_device_id sun5i_a13_pinctrl_match[] = { - { .compatible = "allwinner,sun5i-a13-pinctrl", }, - {} -}; - -static struct platform_driver sun5i_a13_pinctrl_driver = { - .probe = sun5i_a13_pinctrl_probe, - .driver = { - .name = "sun5i-a13-pinctrl", - .of_match_table = sun5i_a13_pinctrl_match, - }, -}; -builtin_platform_driver(sun5i_a13_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i.c index a5b57fdff9e1..c8a94323ce8b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i.c @@ -1,16 +1,15 @@ /* - * Allwinner A10s SoCs pinctrl driver. + * Allwinner sun5i SoCs pinctrl driver. * - * Copyright (C) 2014 Maxime Ripard + * Copyright (C) 2014-2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * Copyright (C) 2016 Mylene Josserand <mylene.josserand@free-electrons.com> * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public +g * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include <linux/init.h> +#include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_device.h> @@ -18,115 +17,133 @@ #include "pinctrl-sunxi.h" -static const struct sunxi_desc_pin sun5i_a10s_pins[] = { - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), +static const struct sunxi_desc_pin sun5i_pins[] = { + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 0), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ SUNXI_FUNCTION(0x3, "ts0"), /* CLK */ SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 1), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ SUNXI_FUNCTION(0x3, "ts0"), /* ERR */ SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 2), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */ SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 3), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */ SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 4), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ SUNXI_FUNCTION(0x3, "ts0"), /* D0 */ SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 5), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ SUNXI_FUNCTION(0x3, "ts0"), /* D1 */ SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 6), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ SUNXI_FUNCTION(0x3, "ts0"), /* D2 */ SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 7), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 8), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 9), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 10), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 11), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ SUNXI_FUNCTION(0x3, "ts0"), /* D7 */ SUNXI_FUNCTION(0x4, "uart1"), /* RING */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 12), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ SUNXI_FUNCTION(0x3, "uart1"), /* TX */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 13), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ SUNXI_FUNCTION(0x3, "uart1"), /* RX */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 14), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ SUNXI_FUNCTION(0x4, "uart3"), /* TX */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 15), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ SUNXI_FUNCTION(0x4, "uart3"), /* RX */ SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 16), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ SUNXI_FUNCTION(0x3, "uart2")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(A, 17), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ @@ -145,6 +162,9 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ + SUNXI_FUNCTION_VARIANT(0x3, + "spdif", /* DO */ + PINCTRL_SUN5I_GR8), SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -156,55 +176,70 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ir0"), /* RX */ SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 5), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 6), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 7), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 8), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s"), /* DO */ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 9), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION_VARIANT(0x3, + "spdif", /* DI */ + PINCTRL_SUN5I_GR8), SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ + SUNXI_FUNCTION_VARIANT(0x3, + "spdif", /* DO */ + PINCTRL_SUN5I_GR8), SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 14), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ @@ -226,12 +261,14 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 19), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /* TX */ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 20), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /* RX */ @@ -251,7 +288,7 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -315,17 +352,20 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 16), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NWP */ SUNXI_FUNCTION(0x4, "uart3")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 17), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */ SUNXI_FUNCTION(0x4, "uart3")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 18), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */ @@ -338,11 +378,13 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x3, "uart2"), /* RX */ SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */ @@ -376,11 +418,13 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */ @@ -414,11 +458,13 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17), + PINCTRL_SUN5I_A10S, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */ @@ -600,26 +646,30 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ SUNXI_FUNCTION(0x4, "uart1"), /* RX */ SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 5), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* DO */ SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ SUNXI_FUNCTION(0x5, "uart2"), /* TX */ SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ @@ -649,7 +699,8 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13), + PINCTRL_SUN5I_A10S | PINCTRL_SUN5I_GR8, SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ @@ -658,28 +709,48 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = { SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ }; -static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = { - .pins = sun5i_a10s_pins, - .npins = ARRAY_SIZE(sun5i_a10s_pins), +static const struct sunxi_pinctrl_desc sun5i_pinctrl_data = { + .pins = sun5i_pins, + .npins = ARRAY_SIZE(sun5i_pins), .irq_banks = 1, }; -static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev) +static int sun5i_pinctrl_probe(struct platform_device *pdev) { - return sunxi_pinctrl_init(pdev, - &sun5i_a10s_pinctrl_data); + unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); + + printk("prout\n"); + + return sunxi_pinctrl_init_with_variant(pdev, &sun5i_pinctrl_data, + variant); } -static const struct of_device_id sun5i_a10s_pinctrl_match[] = { - { .compatible = "allwinner,sun5i-a10s-pinctrl", }, - {} +static const struct of_device_id sun5i_pinctrl_match[] = { + { + .compatible = "allwinner,sun5i-a10s-pinctrl", + .data = (void *)PINCTRL_SUN5I_A10S + }, + { + .compatible = "allwinner,sun5i-a13-pinctrl", + .data = (void *)PINCTRL_SUN5I_A13 + }, + { + .compatible = "nextthing,gr8-pinctrl", + .data = (void *)PINCTRL_SUN5I_GR8 + }, + { }, }; +MODULE_DEVICE_TABLE(of, sun5i_pinctrl_match); -static struct platform_driver sun5i_a10s_pinctrl_driver = { - .probe = sun5i_a10s_pinctrl_probe, +static struct platform_driver sun5i_pinctrl_driver = { + .probe = sun5i_pinctrl_probe, .driver = { - .name = "sun5i-a10s-pinctrl", - .of_match_table = sun5i_a10s_pinctrl_match, + .name = "sun5i-pinctrl", + .of_match_table = sun5i_pinctrl_match, }, }; -builtin_platform_driver(sun5i_a10s_pinctrl_driver); +module_platform_driver(sun5i_pinctrl_driver); + +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); +MODULE_DESCRIPTION("Allwinner sun5i pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c new file mode 100644 index 000000000000..c86d3c42a905 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -0,0 +1,321 @@ +/* + * Allwinner V3s SoCs pinctrl driver. + * + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + * + * Based on pinctrl-sun8i-h3.c, which is: + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_v3s_pins[] = { + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm1"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2"), /* CLK */ + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2"), /* CMD */ + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2"), /* RST */ + SUNXI_FUNCTION(0x3, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */ + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x3, "lcd")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "lcd")), /* DE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lcd")), /* HSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lcd")), /* VSYNC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D10 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D11 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D12 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D13 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D14 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D15 */ + SUNXI_FUNCTION(0x3, "lcd")), /* D21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* FIELD */ + SUNXI_FUNCTION(0x3, "csi_mipi")), /* MCLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "lcd"), /* D22 */ + SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "lcd"), /* D23 */ + SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag")), /* MS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag")), /* DI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0")), /* TX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag")), /* CK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ +}; + +static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { + .pins = sun8i_v3s_pins, + .npins = ARRAY_SIZE(sun8i_v3s_pins), + .irq_banks = 2, + .irq_read_needs_mux = true +}; + +static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_v3s_pinctrl_data); +} + +static const struct of_device_id sun8i_v3s_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-v3s-pinctrl", }, + {} +}; + +static struct platform_driver sun8i_v3s_pinctrl_driver = { + .probe = sun8i_v3s_pinctrl_probe, + .driver = { + .name = "sun8i-v3s-pinctrl", + .of_match_table = sun8i_v3s_pinctrl_match, + }, +}; +builtin_platform_driver(sun8i_v3s_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index b38f7492aba0..60e6e36c4a7e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1040,21 +1040,35 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev) struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); int i; - pctl->ngroups = pctl->desc->npins; + /* + * Allocate groups + * + * We assume that the number of groups is the number of pins + * given in the data array. - /* Allocate groups */ + * This will not always be true, since some pins might not be + * available in the current variant, but fortunately for us, + * this means that the number of pins is the maximum group + * number we will ever see. + */ pctl->groups = devm_kzalloc(&pdev->dev, - pctl->ngroups * sizeof(*pctl->groups), + pctl->desc->npins * sizeof(*pctl->groups), GFP_KERNEL); if (!pctl->groups) return -ENOMEM; for (i = 0; i < pctl->desc->npins; i++) { const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - struct sunxi_pinctrl_group *group = pctl->groups + i; + struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; + + if (pin->variant && !(pctl->variant & pin->variant)) + continue; group->name = pin->pin.name; group->pin = pin->pin.number; + + /* And now we count the actual number of pins / groups */ + pctl->ngroups++; } /* @@ -1062,17 +1076,23 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev) * we'll reallocate that later anyway */ pctl->functions = devm_kzalloc(&pdev->dev, - pctl->desc->npins * sizeof(*pctl->functions), - GFP_KERNEL); + pctl->ngroups * sizeof(*pctl->functions), + GFP_KERNEL); if (!pctl->functions) return -ENOMEM; /* Count functions and their associated groups */ for (i = 0; i < pctl->desc->npins; i++) { const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - struct sunxi_desc_function *func = pin->functions; + struct sunxi_desc_function *func; + + if (pin->variant && !(pctl->variant & pin->variant)) + continue; + + for (func = pin->functions; func->name; func++) { + if (func->variant && !(pctl->variant & func->variant)) + continue; - while (func->name) { /* Create interrupt mapping while we're at it */ if (!strcmp(func->name, "irq")) { int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; @@ -1080,22 +1100,32 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev) } sunxi_pinctrl_add_function(pctl, func->name); - func++; } } + /* And now allocated and fill the array for real */ pctl->functions = krealloc(pctl->functions, - pctl->nfunctions * sizeof(*pctl->functions), - GFP_KERNEL); + pctl->nfunctions * sizeof(*pctl->functions), + GFP_KERNEL); + if (!pctl->functions) { + kfree(pctl->functions); + return -ENOMEM; + } for (i = 0; i < pctl->desc->npins; i++) { const struct sunxi_desc_pin *pin = pctl->desc->pins + i; - struct sunxi_desc_function *func = pin->functions; + struct sunxi_desc_function *func; - while (func->name) { + if (pin->variant && !(pctl->variant & pin->variant)) + continue; + + for (func = pin->functions; func->name; func++) { struct sunxi_pinctrl_function *func_item; const char **func_grp; + if (func->variant && !(pctl->variant & func->variant)) + continue; + func_item = sunxi_pinctrl_find_function_by_name(pctl, func->name); if (!func_item) @@ -1115,7 +1145,6 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev) func_grp++; *func_grp = pin->pin.name; - func++; } } @@ -1207,15 +1236,16 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, return 0; } -int sunxi_pinctrl_init(struct platform_device *pdev, - const struct sunxi_pinctrl_desc *desc) +int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, + const struct sunxi_pinctrl_desc *desc, + unsigned long variant) { struct device_node *node = pdev->dev.of_node; struct pinctrl_desc *pctrl_desc; struct pinctrl_pin_desc *pins; struct sunxi_pinctrl *pctl; struct resource *res; - int i, ret, last_pin; + int i, ret, last_pin, pin_idx; struct clk *clk; pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); @@ -1232,6 +1262,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, pctl->dev = &pdev->dev; pctl->desc = desc; + pctl->variant = variant; pctl->irq_array = devm_kcalloc(&pdev->dev, IRQ_PER_BANK * pctl->desc->irq_banks, @@ -1252,8 +1283,14 @@ int sunxi_pinctrl_init(struct platform_device *pdev, if (!pins) return -ENOMEM; - for (i = 0; i < pctl->desc->npins; i++) - pins[i] = pctl->desc->pins[i].pin; + for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { + const struct sunxi_desc_pin *pin = pctl->desc->pins + i; + + if (pin->variant && !(pctl->variant & pin->variant)) + continue; + + pins[pin_idx++] = pin->pin; + } pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), @@ -1264,7 +1301,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, pctrl_desc->name = dev_name(&pdev->dev); pctrl_desc->owner = THIS_MODULE; pctrl_desc->pins = pins; - pctrl_desc->npins = pctl->desc->npins; + pctrl_desc->npins = pctl->ngroups; pctrl_desc->confops = &sunxi_pconf_ops; pctrl_desc->pctlops = &sunxi_pctrl_ops; pctrl_desc->pmxops = &sunxi_pmx_ops; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index f78a44a03189..56be35387ccf 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -82,7 +82,12 @@ #define SUN4I_FUNC_INPUT 0 #define SUN4I_FUNC_IRQ 6 +#define PINCTRL_SUN5I_A10S BIT(1) +#define PINCTRL_SUN5I_A13 BIT(2) +#define PINCTRL_SUN5I_GR8 BIT(3) + struct sunxi_desc_function { + unsigned long variant; const char *name; u8 muxval; u8 irqbank; @@ -91,6 +96,7 @@ struct sunxi_desc_function { struct sunxi_desc_pin { struct pinctrl_pin_desc pin; + unsigned long variant; struct sunxi_desc_function *functions; }; @@ -128,6 +134,7 @@ struct sunxi_pinctrl { unsigned *irq_array; spinlock_t lock; struct pinctrl_dev *pctl_dev; + unsigned long variant; }; #define SUNXI_PIN(_pin, ...) \ @@ -137,12 +144,27 @@ struct sunxi_pinctrl { __VA_ARGS__, { } }, \ } +#define SUNXI_PIN_VARIANT(_pin, _variant, ...) \ + { \ + .pin = _pin, \ + .variant = _variant, \ + .functions = (struct sunxi_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + #define SUNXI_FUNCTION(_val, _name) \ { \ .name = _name, \ .muxval = _val, \ } +#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \ + { \ + .name = _name, \ + .muxval = _val, \ + .variant = _variant, \ + } + #define SUNXI_FUNCTION_IRQ(_val, _irq) \ { \ .name = "irq", \ @@ -290,7 +312,11 @@ static inline u32 sunxi_irq_status_offset(u16 irq) return irq_num * IRQ_STATUS_IRQ_BITS; } -int sunxi_pinctrl_init(struct platform_device *pdev, - const struct sunxi_pinctrl_desc *desc); +int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, + const struct sunxi_pinctrl_desc *desc, + unsigned long variant); + +#define sunxi_pinctrl_init(_dev, _desc) \ + sunxi_pinctrl_init_with_variant(_dev, _desc, 0) #endif /* __PINCTRL_SUNXI_H */ diff --git a/drivers/pinctrl/ti/Kconfig b/drivers/pinctrl/ti/Kconfig new file mode 100644 index 000000000000..815a88673d38 --- /dev/null +++ b/drivers/pinctrl/ti/Kconfig @@ -0,0 +1,10 @@ +config PINCTRL_TI_IODELAY + tristate "TI IODelay Module pinconf driver" + depends on OF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select REGMAP_MMIO + help + Say Y here to support Texas Instruments' IO delay pinconf driver. + IO delay module is used for the DRA7 SoC family. diff --git a/drivers/pinctrl/ti/Makefile b/drivers/pinctrl/ti/Makefile new file mode 100644 index 000000000000..913744e8b8fa --- /dev/null +++ b/drivers/pinctrl/ti/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_PINCTRL_TI_IODELAY) += pinctrl-ti-iodelay.o diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c new file mode 100644 index 000000000000..717e3404900c --- /dev/null +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -0,0 +1,937 @@ +/* + * Support for configuration of IO Delay module found on Texas Instruments SoCs + * such as DRA7 + * + * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../devicetree.h" + +#define DRIVER_NAME "ti-iodelay" + +/** + * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance + * @signature_mask: CONFIG_REG mask for the signature bits (see TRM) + * @signature_value: CONFIG_REG signature value to be written (see TRM) + * @lock_mask: CONFIG_REG mask for the lock bits (see TRM) + * @lock_val: CONFIG_REG lock value for the lock bits (see TRM) + * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM) + * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM) + * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM) + * @reg_refclk_offset: Refclk register offset + * @refclk_period_mask: Refclk mask + * @reg_coarse_offset: Coarse register configuration offset + * @coarse_delay_count_mask: Coarse delay count mask + * @coarse_ref_count_mask: Coarse ref count mask + * @reg_fine_offset: Fine register configuration offset + * @fine_delay_count_mask: Fine delay count mask + * @fine_ref_count_mask: Fine ref count mask + * @reg_global_lock_offset: Global iodelay module lock register offset + * @global_lock_mask: Lock mask + * @global_unlock_val: Unlock value + * @global_lock_val: Lock value + * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 8 + * @reg_nr_per_pin: Number of iodelay registers for each pin + * @regmap_config: Regmap configuration for the IODelay region + */ +struct ti_iodelay_reg_data { + u32 signature_mask; + u32 signature_value; + u32 lock_mask; + u32 lock_val; + u32 unlock_val; + u32 binary_data_coarse_mask; + u32 binary_data_fine_mask; + + u32 reg_refclk_offset; + u32 refclk_period_mask; + + u32 reg_coarse_offset; + u32 coarse_delay_count_mask; + u32 coarse_ref_count_mask; + + u32 reg_fine_offset; + u32 fine_delay_count_mask; + u32 fine_ref_count_mask; + + u32 reg_global_lock_offset; + u32 global_lock_mask; + u32 global_unlock_val; + u32 global_lock_val; + + u32 reg_start_offset; + u32 reg_nr_per_pin; + + struct regmap_config *regmap_config; +}; + +/** + * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM) + * @coarse_ref_count: Coarse reference count + * @coarse_delay_count: Coarse delay count + * @fine_ref_count: Fine reference count + * @fine_delay_count: Fine Delay count + * @ref_clk_period: Reference Clock period + * @cdpe: Coarse delay parameter + * @fdpe: Fine delay parameter + */ +struct ti_iodelay_reg_values { + u16 coarse_ref_count; + u16 coarse_delay_count; + + u16 fine_ref_count; + u16 fine_delay_count; + + u16 ref_clk_period; + + u32 cdpe; + u32 fdpe; +}; + +/** + * struct ti_iodelay_cfg - Description of each configuration parameters + * @offset: Configuration register offset + * @a_delay: Agnostic Delay (in ps) + * @g_delay: Gnostic Delay (in ps) + */ +struct ti_iodelay_cfg { + u16 offset; + u16 a_delay; + u16 g_delay; +}; + +/** + * struct ti_iodelay_pingroup - Structure that describes one group + * @cfg: configuration array for the pin (from dt) + * @ncfg: number of configuration values allocated + * @config: pinconf "Config" - currently a dummy value + */ +struct ti_iodelay_pingroup { + struct ti_iodelay_cfg *cfg; + int ncfg; + unsigned long config; +}; + +/** + * struct ti_iodelay_device - Represents information for a iodelay instance + * @dev: Device pointer + * @phys_base: Physical address base of the iodelay device + * @reg_base: Virtual address base of the iodelay device + * @regmap: Regmap for this iodelay instance + * @pctl: Pinctrl device + * @desc: pinctrl descriptor for pctl + * @pa: pinctrl pin wise description + * @reg_data: Register definition data for the IODelay instance + * @reg_init_conf_values: Initial configuration values. + */ +struct ti_iodelay_device { + struct device *dev; + unsigned long phys_base; + void __iomem *reg_base; + struct regmap *regmap; + + struct pinctrl_dev *pctl; + struct pinctrl_desc desc; + struct pinctrl_pin_desc *pa; + + const struct ti_iodelay_reg_data *reg_data; + struct ti_iodelay_reg_values reg_init_conf_values; +}; + +/** + * ti_iodelay_extract() - extract bits for a field + * @val: Register value + * @mask: Mask + * + * Return: extracted value which is appropriately shifted + */ +static inline u32 ti_iodelay_extract(u32 val, u32 mask) +{ + return (val & mask) >> __ffs(mask); +} + +/** + * ti_iodelay_compute_dpe() - Compute equation for delay parameter + * @period: Period to use + * @ref: Reference Count + * @delay: Delay count + * @delay_m: Delay multiplier + * + * Return: Computed delay parameter + */ +static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay, + u16 delay_m) +{ + u64 m, d; + + /* Handle overflow conditions */ + m = 10 * (u64)period * (u64)ref; + d = 2 * (u64)delay * (u64)delay_m; + + /* Truncate result back to 32 bits */ + return div64_u64(m, d); +} + +/** + * ti_iodelay_pinconf_set() - Configure the pin configuration + * @iod: iodelay device + * @cfg: Configuration + * + * Update the configuration register as per TRM and lockup once done. + * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only + * while in Isolation. But, then, isolation also implies that every pin + * on the SoC (including DDR) will be isolated out. The only benefit being + * a glitchless configuration, However, the intent of this driver is purely + * to support a "glitchy" configuration where applicable. + * + * Return: 0 in case of success, else appropriate error value + */ +static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, + struct ti_iodelay_cfg *cfg) +{ + const struct ti_iodelay_reg_data *reg = iod->reg_data; + struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; + struct device *dev = iod->dev; + u32 g_delay_coarse, g_delay_fine; + u32 a_delay_coarse, a_delay_fine; + u32 c_elements, f_elements; + u32 total_delay; + u32 reg_mask, reg_val, tmp_val; + int r; + + /* NOTE: Truncation is expected in all division below */ + g_delay_coarse = cfg->g_delay / 920; + g_delay_fine = ((cfg->g_delay % 920) * 10) / 60; + + a_delay_coarse = cfg->a_delay / ival->cdpe; + a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe; + + c_elements = g_delay_coarse + a_delay_coarse; + f_elements = (g_delay_fine + a_delay_fine) / 10; + + if (f_elements > 22) { + total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe; + c_elements = total_delay / ival->cdpe; + f_elements = (total_delay % ival->cdpe) / ival->fdpe; + } + + reg_mask = reg->signature_mask; + reg_val = reg->signature_value << __ffs(reg->signature_mask); + + reg_mask |= reg->binary_data_coarse_mask; + tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); + if (tmp_val & ~reg->binary_data_coarse_mask) { + dev_err(dev, "Masking overflow of coarse elements %08x\n", + tmp_val); + tmp_val &= reg->binary_data_coarse_mask; + } + reg_val |= tmp_val; + + reg_mask |= reg->binary_data_fine_mask; + tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); + if (tmp_val & ~reg->binary_data_fine_mask) { + dev_err(dev, "Masking overflow of fine elements %08x\n", + tmp_val); + tmp_val &= reg->binary_data_fine_mask; + } + reg_val |= tmp_val; + + /* + * NOTE: we leave the iodelay values unlocked - this is to work around + * situations such as those found with mmc mode change. + * However, this leaves open any unwarranted changes to padconf register + * impacting iodelay configuration. Use with care! + */ + reg_mask |= reg->lock_mask; + reg_val |= reg->unlock_val << __ffs(reg->lock_mask); + r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); + + dev_info(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n", + cfg->offset, cfg->a_delay, cfg->g_delay, c_elements, + f_elements, reg_val); + + return r; +} + +/** + * ti_iodelay_pinconf_init_dev() - Initialize IODelay device + * @iod: iodelay device + * + * Unlocks the iodelay region, computes the common parameters + * + * Return: 0 in case of success, else appropriate error value + */ +static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) +{ + const struct ti_iodelay_reg_data *reg = iod->reg_data; + struct device *dev = iod->dev; + struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; + u32 val; + int r; + + /* unlock the iodelay region */ + r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, + reg->global_lock_mask, reg->global_unlock_val); + if (r) + return r; + + /* Read up Recalibration sequence done by bootloader */ + r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); + if (r) + return r; + ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); + dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period); + + r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); + if (r) + return r; + ival->coarse_ref_count = + ti_iodelay_extract(val, reg->coarse_ref_count_mask); + ival->coarse_delay_count = + ti_iodelay_extract(val, reg->coarse_delay_count_mask); + if (!ival->coarse_delay_count) { + dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n", + val); + return -EINVAL; + } + ival->cdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, + ival->coarse_ref_count, + ival->coarse_delay_count, 88); + if (!ival->cdpe) { + dev_err(dev, "Invalid cdpe computed params = %d %d %d\n", + ival->ref_clk_period, ival->coarse_ref_count, + ival->coarse_delay_count); + return -EINVAL; + } + dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n", + ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe); + + r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); + if (r) + return r; + ival->fine_ref_count = + ti_iodelay_extract(val, reg->fine_ref_count_mask); + ival->fine_delay_count = + ti_iodelay_extract(val, reg->fine_delay_count_mask); + if (!ival->fine_delay_count) { + dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n", + val); + return -EINVAL; + } + ival->fdpe = ti_iodelay_compute_dpe(ival->ref_clk_period, + ival->fine_ref_count, + ival->fine_delay_count, 264); + if (!ival->fdpe) { + dev_err(dev, "Invalid fdpe(0) computed params = %d %d %d\n", + ival->ref_clk_period, ival->fine_ref_count, + ival->fine_delay_count); + return -EINVAL; + } + dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n", + ival->fine_ref_count, ival->fine_delay_count, ival->fdpe); + + return 0; +} + +/** + * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device + * @iod: IODelay device + * + * Deinitialize the IODelay device (basically just lock the region back up. + */ +static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod) +{ + const struct ti_iodelay_reg_data *reg = iod->reg_data; + + /* lock the iodelay region back again */ + regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, + reg->global_lock_mask, reg->global_lock_val); +} + +/** + * ti_iodelay_get_pingroup() - Find the group mapped by a group selector + * @iod: iodelay device + * @selector: Group Selector + * + * Return: Corresponding group representing group selector + */ +static struct ti_iodelay_pingroup * +ti_iodelay_get_pingroup(struct ti_iodelay_device *iod, unsigned int selector) +{ + struct group_desc *g; + + g = pinctrl_generic_get_group(iod->pctl, selector); + if (!g) { + dev_err(iod->dev, "%s could not find pingroup %i\n", __func__, + selector); + + return NULL; + } + + return g->data; +} + +/** + * ti_iodelay_offset_to_pin() - get a pin index based on the register offset + * @iod: iodelay driver instance + * @offset: register offset from the base + */ +static int ti_iodelay_offset_to_pin(struct ti_iodelay_device *iod, + unsigned int offset) +{ + const struct ti_iodelay_reg_data *r = iod->reg_data; + unsigned int index; + + if (offset > r->regmap_config->max_register) { + dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n", + offset, r->regmap_config->max_register); + return -EINVAL; + } + + index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride; + index /= r->reg_nr_per_pin; + + return index; +} + +/** + * ti_iodelay_node_iterator() - Iterate iodelay node + * @pctldev: Pin controller driver + * @np: Device node + * @pinctrl_spec: Parsed arguments from device tree + * @pins: Array of pins in the pin group + * @pin_index: Pin index in the pin array + * @data: Pin controller driver specific data + * + */ +static int ti_iodelay_node_iterator(struct pinctrl_dev *pctldev, + struct device_node *np, + const struct of_phandle_args *pinctrl_spec, + int *pins, int pin_index, void *data) +{ + struct ti_iodelay_device *iod; + struct ti_iodelay_cfg *cfg = data; + const struct ti_iodelay_reg_data *r; + struct pinctrl_pin_desc *pd; + int pin; + + iod = pinctrl_dev_get_drvdata(pctldev); + if (!iod) + return -EINVAL; + + r = iod->reg_data; + + if (pinctrl_spec->args_count < r->reg_nr_per_pin) { + dev_err(iod->dev, "invalid args_count for spec: %i\n", + pinctrl_spec->args_count); + + return -EINVAL; + } + + /* Index plus two value cells */ + cfg[pin_index].offset = pinctrl_spec->args[0]; + cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff; + cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff; + + pin = ti_iodelay_offset_to_pin(iod, cfg[pin_index].offset); + if (pin < 0) { + dev_err(iod->dev, "could not add functions for %s %ux\n", + np->name, cfg[pin_index].offset); + return -ENODEV; + } + pins[pin_index] = pin; + + pd = &iod->pa[pin]; + pd->drv_data = &cfg[pin_index]; + + dev_dbg(iod->dev, "%s offset=%x a_delay = %d g_delay = %d\n", + np->name, cfg[pin_index].offset, cfg[pin_index].a_delay, + cfg[pin_index].g_delay); + + return 0; +} + +/** + * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group + * @pctldev: pinctrl device representing IODelay device + * @np: Node Pointer (device tree) + * @map: Pinctrl Map returned back to pinctrl framework + * @num_maps: Number of maps (1) + * + * Maps the device tree description into a group of configuration parameters + * for iodelay block entry. + * + * Return: 0 in case of success, else appropriate error value + */ +static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct ti_iodelay_device *iod; + struct ti_iodelay_cfg *cfg; + struct ti_iodelay_pingroup *g; + const char *name = "pinctrl-pin-array"; + int rows, *pins, error = -EINVAL, i; + + iod = pinctrl_dev_get_drvdata(pctldev); + if (!iod) + return -EINVAL; + + rows = pinctrl_count_index_with_args(np, name); + if (rows == -EINVAL) + return rows; + + *map = devm_kzalloc(iod->dev, sizeof(**map), GFP_KERNEL); + if (!*map) + return -ENOMEM; + *num_maps = 0; + + g = devm_kzalloc(iod->dev, sizeof(*g), GFP_KERNEL); + if (!g) { + error = -ENOMEM; + goto free_map; + } + + pins = devm_kzalloc(iod->dev, sizeof(*pins) * rows, GFP_KERNEL); + if (!pins) + goto free_group; + + cfg = devm_kzalloc(iod->dev, sizeof(*cfg) * rows, GFP_KERNEL); + if (!cfg) { + error = -ENOMEM; + goto free_pins; + } + + for (i = 0; i < rows; i++) { + struct of_phandle_args pinctrl_spec; + + error = pinctrl_parse_index_with_args(np, name, i, + &pinctrl_spec); + if (error) + goto free_data; + + error = ti_iodelay_node_iterator(pctldev, np, &pinctrl_spec, + pins, i, cfg); + if (error) + goto free_data; + } + + g->cfg = cfg; + g->ncfg = i; + g->config = PIN_CONFIG_END; + + error = pinctrl_generic_add_group(iod->pctl, np->name, pins, i, g); + if (error < 0) + goto free_data; + + (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP; + (*map)->data.configs.group_or_pin = np->name; + (*map)->data.configs.configs = &g->config; + (*map)->data.configs.num_configs = 1; + *num_maps = 1; + + return 0; + +free_data: + devm_kfree(iod->dev, cfg); +free_pins: + devm_kfree(iod->dev, pins); +free_group: + devm_kfree(iod->dev, g); +free_map: + devm_kfree(iod->dev, *map); + + return error; +} + +/** + * ti_iodelay_pinconf_group_get() - Get the group configuration + * @pctldev: pinctrl device representing IODelay device + * @selector: Group selector + * @config: Configuration returned + * + * Return: The configuration if the group is valid, else returns -EINVAL + */ +static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *config) +{ + struct ti_iodelay_device *iod; + struct device *dev; + struct ti_iodelay_pingroup *group; + + iod = pinctrl_dev_get_drvdata(pctldev); + dev = iod->dev; + group = ti_iodelay_get_pingroup(iod, selector); + + if (!group) + return -EINVAL; + + *config = group->config; + return 0; +} + +/** + * ti_iodelay_pinconf_group_set() - Configure the groups of pins + * @pctldev: pinctrl device representing IODelay device + * @selector: Group selector + * @configs: Configurations + * @num_configs: Number of configurations + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct ti_iodelay_device *iod; + struct device *dev; + struct ti_iodelay_pingroup *group; + int i; + + iod = pinctrl_dev_get_drvdata(pctldev); + dev = iod->dev; + group = ti_iodelay_get_pingroup(iod, selector); + + if (num_configs != 1) { + dev_err(dev, "Unsupported number of configurations %d\n", + num_configs); + return -EINVAL; + } + + if (*configs != PIN_CONFIG_END) { + dev_err(dev, "Unsupported configuration\n"); + return -EINVAL; + } + + for (i = 0; i < group->ncfg; i++) { + if (ti_iodelay_pinconf_set(iod, &group->cfg[i])) + return -ENOTSUPP; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +/** + * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index + * @iod: iodelay driver instance + * @selector: Pin index + */ +static unsigned int ti_iodelay_pin_to_offset(struct ti_iodelay_device *iod, + unsigned int selector) +{ + const struct ti_iodelay_reg_data *r = iod->reg_data; + unsigned int offset; + + offset = selector * r->regmap_config->reg_stride; + offset *= r->reg_nr_per_pin; + offset += r->reg_start_offset; + + return offset; +} + +static void ti_iodelay_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int pin) +{ + struct ti_iodelay_device *iod; + struct pinctrl_pin_desc *pd; + struct ti_iodelay_cfg *cfg; + const struct ti_iodelay_reg_data *r; + unsigned long offset; + u32 in, oen, out; + + iod = pinctrl_dev_get_drvdata(pctldev); + r = iod->reg_data; + + offset = ti_iodelay_pin_to_offset(iod, pin); + pd = &iod->pa[pin]; + cfg = pd->drv_data; + + regmap_read(iod->regmap, offset, &in); + regmap_read(iod->regmap, offset + r->regmap_config->reg_stride, &oen); + regmap_read(iod->regmap, offset + r->regmap_config->reg_stride * 2, + &out); + + seq_printf(s, "%lx a: %i g: %i (%08x %08x %08x) %s ", + iod->phys_base + offset, + cfg ? cfg->a_delay : -1, + cfg ? cfg->g_delay : -1, + in, oen, out, DRIVER_NAME); +} + +/** + * ti_iodelay_pinconf_group_dbg_show() - show the group information + * @pctldev: Show the group information + * @s: Sequence file + * @selector: Group selector + * + * Provide the configuration information of the selected group + */ +static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int selector) +{ + struct ti_iodelay_device *iod; + struct device *dev; + struct ti_iodelay_pingroup *group; + int i; + + iod = pinctrl_dev_get_drvdata(pctldev); + dev = iod->dev; + group = ti_iodelay_get_pingroup(iod, selector); + if (!group) + return; + + for (i = 0; i < group->ncfg; i++) { + struct ti_iodelay_cfg *cfg; + u32 reg = 0; + + cfg = &group->cfg[i]; + regmap_read(iod->regmap, cfg->offset, ®), + seq_printf(s, "\n\t0x%08x = 0x%08x (%3d, %3d)", + cfg->offset, reg, cfg->a_delay, + cfg->g_delay); + } +} +#endif + +static struct pinctrl_ops ti_iodelay_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = ti_iodelay_pin_dbg_show, +#endif + .dt_node_to_map = ti_iodelay_dt_node_to_map, +}; + +static struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = { + .pin_config_group_get = ti_iodelay_pinconf_group_get, + .pin_config_group_set = ti_iodelay_pinconf_group_set, +#ifdef CONFIG_DEBUG_FS + .pin_config_group_dbg_show = ti_iodelay_pinconf_group_dbg_show, +#endif +}; + +/** + * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay + * @dev: Device pointer + * @iod: iodelay device + * @base_phy: Base Physical Address + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_alloc_pins(struct device *dev, + struct ti_iodelay_device *iod, u32 base_phy) +{ + const struct ti_iodelay_reg_data *r = iod->reg_data; + struct pinctrl_pin_desc *pin; + u32 phy_reg; + int nr_pins, i; + + nr_pins = ti_iodelay_offset_to_pin(iod, r->regmap_config->max_register); + dev_dbg(dev, "Allocating %i pins\n", nr_pins); + + iod->pa = devm_kzalloc(dev, sizeof(*iod->pa) * nr_pins, GFP_KERNEL); + if (!iod->pa) + return -ENOMEM; + + iod->desc.pins = iod->pa; + iod->desc.npins = nr_pins; + + phy_reg = r->reg_start_offset + base_phy; + + for (i = 0; i < nr_pins; i++, phy_reg += 4) { + pin = &iod->pa[i]; + pin->number = i; + } + + return 0; +} + +static struct regmap_config dra7_iodelay_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xd1c, +}; + +static struct ti_iodelay_reg_data dra7_iodelay_data = { + .signature_mask = 0x0003f000, + .signature_value = 0x29, + .lock_mask = 0x00000400, + .lock_val = 1, + .unlock_val = 0, + .binary_data_coarse_mask = 0x000003e0, + .binary_data_fine_mask = 0x0000001f, + + .reg_refclk_offset = 0x14, + .refclk_period_mask = 0xffff, + + .reg_coarse_offset = 0x18, + .coarse_delay_count_mask = 0xffff0000, + .coarse_ref_count_mask = 0x0000ffff, + + .reg_fine_offset = 0x1C, + .fine_delay_count_mask = 0xffff0000, + .fine_ref_count_mask = 0x0000ffff, + + .reg_global_lock_offset = 0x2c, + .global_lock_mask = 0x0000ffff, + .global_unlock_val = 0x0000aaaa, + .global_lock_val = 0x0000aaab, + + .reg_start_offset = 0x30, + .reg_nr_per_pin = 3, + .regmap_config = &dra7_iodelay_regmap_config, +}; + +static const struct of_device_id ti_iodelay_of_match[] = { + {.compatible = "ti,dra7-iodelay", .data = &dra7_iodelay_data}, + { /* Hopefully no more.. */ }, +}; +MODULE_DEVICE_TABLE(of, ti_iodelay_of_match); + +/** + * ti_iodelay_probe() - Standard probe + * @pdev: platform device + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = of_node_get(dev->of_node); + const struct of_device_id *match; + struct resource *res; + struct ti_iodelay_device *iod; + int ret = 0; + + if (!np) { + ret = -EINVAL; + dev_err(dev, "No OF node\n"); + goto exit_out; + } + + match = of_match_device(ti_iodelay_of_match, dev); + if (!match) { + ret = -EINVAL; + dev_err(dev, "No DATA match\n"); + goto exit_out; + } + + iod = devm_kzalloc(dev, sizeof(*iod), GFP_KERNEL); + if (!iod) { + ret = -ENOMEM; + goto exit_out; + } + iod->dev = dev; + iod->reg_data = match->data; + + /* So far We can assume there is only 1 bank of registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "Missing MEM resource\n"); + ret = -ENODEV; + goto exit_out; + } + + iod->phys_base = res->start; + iod->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(iod->reg_base)) { + ret = PTR_ERR(iod->reg_base); + goto exit_out; + } + + iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, + iod->reg_data->regmap_config); + if (IS_ERR(iod->regmap)) { + dev_err(dev, "Regmap MMIO init failed.\n"); + ret = PTR_ERR(iod->regmap); + goto exit_out; + } + + if (ti_iodelay_pinconf_init_dev(iod)) + goto exit_out; + + ret = ti_iodelay_alloc_pins(dev, iod, res->start); + if (ret) + goto exit_out; + + iod->desc.pctlops = &ti_iodelay_pinctrl_ops; + /* no pinmux ops - we are pinconf */ + iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops; + iod->desc.name = dev_name(dev); + iod->desc.owner = THIS_MODULE; + + ret = pinctrl_register_and_init(&iod->desc, dev, iod, &iod->pctl); + if (ret) { + dev_err(dev, "Failed to register pinctrl\n"); + goto exit_out; + } + + platform_set_drvdata(pdev, iod); + +exit_out: + of_node_put(np); + return ret; +} + +/** + * ti_iodelay_remove() - standard remove + * @pdev: platform device + * + * Return: 0 if all went fine, else appropriate error value. + */ +static int ti_iodelay_remove(struct platform_device *pdev) +{ + struct ti_iodelay_device *iod = platform_get_drvdata(pdev); + + if (!iod) + return 0; + + if (iod->pctl) + pinctrl_unregister(iod->pctl); + + ti_iodelay_pinconf_deinit_dev(iod); + + /* Expect other allocations to be freed by devm */ + + return 0; +} + +static struct platform_driver ti_iodelay_driver = { + .probe = ti_iodelay_probe, + .remove = ti_iodelay_remove, + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + .of_match_table = ti_iodelay_of_match, + }, +}; +module_platform_driver(ti_iodelay_driver); + +MODULE_AUTHOR("Texas Instruments, Inc."); +MODULE_DESCRIPTION("Pinconf driver for TI's IO Delay module"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index a42e57da270d..8ce2d87a238b 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -141,12 +141,27 @@ struct pinctrl_desc { }; /* External interface to pin controller */ + +extern int pinctrl_register_and_init(struct pinctrl_desc *pctldesc, + struct device *dev, void *driver_data, + struct pinctrl_dev **pctldev); + +/* Please use pinctrl_register_and_init() instead */ extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, struct device *dev, void *driver_data); + extern void pinctrl_unregister(struct pinctrl_dev *pctldev); + +extern int devm_pinctrl_register_and_init(struct device *dev, + struct pinctrl_desc *pctldesc, + void *driver_data, + struct pinctrl_dev **pctldev); + +/* Please use devm_pinctrl_register_and_init() instead */ extern struct pinctrl_dev *devm_pinctrl_register(struct device *dev, struct pinctrl_desc *pctldesc, void *driver_data); + extern void devm_pinctrl_unregister(struct device *dev, struct pinctrl_dev *pctldev); |