drm/bridge/sii8620: rename symbol names

The patch renames variables and defines to match these in mainline.

Change-Id: Iec05a4477001d57aa09fc34e1eec2c330f84253d
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

3 files changed, 118 insertions, 118 deletions

diff --git a/drivers/gpu/drm/bridge/sii8620.c b/drivers/gpu/drm/bridge/sii8620.c
index f52e6bf40573..dcc08c02191d 100644
--- a/drivers/gpu/drm/bridge/sii8620.c
+++ b/drivers/gpu/drm/bridge/sii8620.c
@@ -229,7 +229,7 @@ static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
 	sii8620_write(ctx, addr, val);
 }
 
-static void sii8620_msc_work(struct sii8620 *ctx)
+static void sii8620_mt_work(struct sii8620 *ctx)
 {
 	struct sii8620_mt_msg *msg;
 
@@ -275,7 +275,7 @@ static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx,
 	}
 }
 
-static struct sii8620_mt_msg *sii8620_msg_new(struct sii8620 *ctx)
+static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx)
 {
 	struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL);
 
@@ -289,7 +289,7 @@ static struct sii8620_mt_msg *sii8620_msg_new(struct sii8620 *ctx)
 
 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
 {
-	struct sii8620_mt_msg *msg = sii8620_msg_new(ctx);
+	struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 
 	if (!msg)
 		return;
@@ -302,7 +302,7 @@ static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
 
 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
 {
-	struct sii8620_mt_msg *msg = sii8620_msg_new(ctx);
+	struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 
 	if (!msg)
 		return;
@@ -313,9 +313,9 @@ static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
 	msg->send = sii8620_mt_msc_cmd_send;
 }
 
-static void sii8620_write_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
+static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
 {
-	struct sii8620_mt_msg *msg = sii8620_msg_new(ctx);
+	struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 
 	if (!msg)
 		return;
@@ -326,9 +326,9 @@ static void sii8620_write_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
 	msg->send = sii8620_mt_msc_cmd_send;
 }
 
-static void sii8620_write_rap(struct sii8620 *ctx, u8 code)
+static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
 {
-	sii8620_write_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
+	sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
 }
 
 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
@@ -376,7 +376,7 @@ static void sii8620_mr_devcap(struct sii8620 *ctx)
 			 MHL_DCAP_SIZE);
 	sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
 
-	if (!(dcap[MHL_DCAP_DEV_CAT] & MHL_DCAP_CAT_SINK))
+	if (!(dcap[MHL_DCAP_CAT] & MHL_DCAP_CAT_SINK))
 		return;
 
 	sii8620_fetch_edid(ctx);
@@ -400,7 +400,7 @@ static void sii8620_mr_xdevcap(struct sii8620 *ctx)
 
 	sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
 			      MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
-	sii8620_write_rap(ctx, MHL_RAP_CBUS_MODE_UP);
+	sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
 }
 
 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,
@@ -768,7 +768,7 @@ static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx)
 
 	sii8620_write_seq_static(ctx,
 		REG_MDT_RCV_TIMEOUT, 100,
-		REG_MDT_RCV_CONTROL, BIT_MDT_RCV_CONTROL_MDT_RCV_EN
+		REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN
 	);
 	ctx->gen2_write_burst = 1;
 }
@@ -779,8 +779,8 @@ static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx)
 		return;
 
 	sii8620_write_seq_static(ctx,
-		REG_MDT_XMIT_CONTROL, 0,
-		REG_MDT_RCV_CONTROL, 0
+		REG_MDT_XMIT_CTRL, 0,
+		REG_MDT_RCV_CTRL, 0
 	);
 	ctx->gen2_write_burst = 0;
 }
@@ -855,7 +855,7 @@ static void sii8620_peer_specific_init(struct sii8620 *ctx)
 			REG_HDCP2X_INTR0, 0xFF,
 			REG_INTR1, 0xFF,
 			REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
-				| BIT_SYS_CTRL1_TX_CONTROL_HDMI
+				| BIT_SYS_CTRL1_TX_CTRL_HDMI
 		);
 }
 
@@ -865,9 +865,9 @@ static void sii8620_peer_specific_init(struct sii8620 *ctx)
 
 static void sii8620_set_dev_cap(struct sii8620 *ctx)
 {
-	static const u8 dev_cap[MHL_DCAP_SIZE] = {
+	static const u8 devcap[MHL_DCAP_SIZE] = {
 		[MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION,
-		[MHL_DCAP_DEV_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
+		[MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
 		[MHL_DCAP_ADOPTER_ID_H] = 0x01,
 		[MHL_DCAP_ADOPTER_ID_L] = 0x41,
 		[MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444
@@ -883,7 +883,7 @@ static void sii8620_set_dev_cap(struct sii8620 *ctx)
 		[MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE,
 		[MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE,
 	};
-	static const u8 xdev_cap[MHL_XDC_SIZE] = {
+	static const u8 xdcap[MHL_XDC_SIZE] = {
 		[MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075
 			| MHL_XDC_ECBUS_S_8BIT,
 		[MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150
@@ -892,16 +892,16 @@ static void sii8620_set_dev_cap(struct sii8620 *ctx)
 		[MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE,
 	};
 
-	sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, dev_cap, ARRAY_SIZE(dev_cap));
-	sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdev_cap, ARRAY_SIZE(xdev_cap));
+	sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap));
+	sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap));
 }
 
 static void sii8620_mhl_init(struct sii8620 *ctx)
 {
 	sii8620_write_seq_static(ctx,
 		REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
-		REG_CBUS_MSC_COMPATIBILITY_CONTROL,
-			BIT_CBUS_MSC_COMPATIBILITY_CONTROL_XDEVCAP_EN,
+		REG_CBUS_MSC_COMPAT_CTRL,
+			BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN,
 	);
 
 	sii8620_peer_specific_init(ctx);
@@ -929,10 +929,10 @@ static void sii8620_mhl_init(struct sii8620 *ctx)
 	sii8620_set_dev_cap(ctx);
 	sii8620_write_seq_static(ctx,
 		REG_MDT_XMIT_TIMEOUT, 100,
-		REG_MDT_XMIT_CONTROL, 0x03,
+		REG_MDT_XMIT_CTRL, 0x03,
 		REG_MDT_XFIFO_STAT, 0x00,
 		REG_MDT_RCV_TIMEOUT, 100,
-		REG_CBUS_LINK_CONTROL_8, 0x1D,
+		REG_CBUS_LINK_CTRL_8, 0x1D,
 	);
 
 	sii8620_start_gen2_write_burst(ctx);
@@ -949,7 +949,7 @@ static void sii8620_mhl_init(struct sii8620 *ctx)
 		REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN,
 		REG_MHL_COC_CTL4, 0x2D,
 		REG_MHL_COC_CTL5, 0xF9,
-		REG_MSC_HEARTBEAT_CONTROL, 0x27,
+		REG_MSC_HEARTBEAT_CTRL, 0x27,
 	);
 	sii8620_disable_gen2_write_burst(ctx);
 
@@ -971,7 +971,7 @@ static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
 	switch (mode) {
 	case CM_MHL1:
 		sii8620_write_seq_static(ctx,
-			REG_CBUS_MSC_COMPATIBILITY_CONTROL, 0x02,
+			REG_CBUS_MSC_COMPAT_CTRL, 0x02,
 			REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE,
 			REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
 				| BIT_DPD_OSC_EN,
@@ -1042,7 +1042,7 @@ static void sii8620_disconnect(struct sii8620 *ctx)
 		REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
 			| BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
 		REG_INT_CTRL, 0x00,
-		REG_MSC_HEARTBEAT_CONTROL, 0x27,
+		REG_MSC_HEARTBEAT_CTRL, 0x27,
 		REG_DISC_CTRL1, 0x25,
 		REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT,
 		REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT,
@@ -1091,8 +1091,8 @@ static void sii8620_mhl_disconnected(struct sii8620 *ctx)
 {
 	sii8620_write_seq_static(ctx,
 		REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
-		REG_CBUS_MSC_COMPATIBILITY_CONTROL,
-			BIT_CBUS_MSC_COMPATIBILITY_CONTROL_XDEVCAP_EN
+		REG_CBUS_MSC_COMPAT_CTRL,
+			BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
 	);
 	sii8620_disconnect(ctx);
 }
@@ -1386,7 +1386,7 @@ static irqreturn_t sii8620_irq_thread(int irq, void *data)
 		if (sii8620_test_bit(irq_vec[i].bit, stats))
 			irq_vec[i].handler(ctx);
 
-	sii8620_msc_work(ctx);
+	sii8620_mt_work(ctx);
 
 	mutex_unlock(&ctx->lock);
 
diff --git a/drivers/gpu/drm/bridge/sii8620.h b/drivers/gpu/drm/bridge/sii8620.h
index 6e2eb1847e38..4261c4a736b6 100644
--- a/drivers/gpu/drm/bridge/sii8620.h
+++ b/drivers/gpu/drm/bridge/sii8620.h
@@ -50,7 +50,7 @@
 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD              (0x10)
 #define BIT_SYS_CTRL1_OTP2XVOVR_EN                  (0x08)
 #define BIT_SYS_CTRL1_OTP2XAOVR_EN                  (0x04)
-#define BIT_SYS_CTRL1_TX_CONTROL_HDMI               (0x02)
+#define BIT_SYS_CTRL1_TX_CTRL_HDMI                  (0x02)
 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET               (0x01)
 
 /* 0x0B System Control DPD                                 (Default: 0x90)    */
@@ -1232,79 +1232,79 @@
 
 /* 0x11 CoC 2nd Ctl Register                               (Default: 0x0A)    */
 #define REG_COC_CTL1                                (0x0711)
-#define MSK_COC_CTL1_COC_CONTROL1_7_6               (0xC0)
-#define MSK_COC_CTL1_COC_CONTROL1_5_0               (0x3F)
+#define MSK_COC_CTL1_COC_CTRL1_7_6                  (0xC0)
+#define MSK_COC_CTL1_COC_CTRL1_5_0                  (0x3F)
 
 /* 0x12 CoC 3rd Ctl Register                               (Default: 0x14)    */
 #define REG_COC_CTL2                                (0x0712)
-#define MSK_COC_CTL2_COC_CONTROL2_7_6               (0xC0)
-#define MSK_COC_CTL2_COC_CONTROL2_5_0               (0x3F)
+#define MSK_COC_CTL2_COC_CTRL2_7_6                  (0xC0)
+#define MSK_COC_CTL2_COC_CTRL2_5_0                  (0x3F)
 
 /* 0x13 CoC 4th Ctl Register                               (Default: 0x40)    */
 #define REG_COC_CTL3                                (0x0713)
-#define BIT_COC_CTL3_COC_CONTROL3_7                 (0x80)
-#define MSK_COC_CTL3_COC_CONTROL3_6_0               (0x7F)
+#define BIT_COC_CTL3_COC_CTRL3_7                    (0x80)
+#define MSK_COC_CTL3_COC_CTRL3_6_0                  (0x7F)
 
 /* 0x16 CoC 7th Ctl Register                               (Default: 0x00)    */
 #define REG_COC_CTL6                                (0x0716)
-#define BIT_COC_CTL6_COC_CONTROL6_7                 (0x80)
-#define BIT_COC_CTL6_COC_CONTROL6_6                 (0x40)
-#define MSK_COC_CTL6_COC_CONTROL6_5_0               (0x3F)
+#define BIT_COC_CTL6_COC_CTRL6_7                    (0x80)
+#define BIT_COC_CTL6_COC_CTRL6_6                    (0x40)
+#define MSK_COC_CTL6_COC_CTRL6_5_0                  (0x3F)
 
 /* 0x17 CoC 8th Ctl Register                               (Default: 0x06)    */
 #define REG_COC_CTL7                                (0x0717)
-#define BIT_COC_CTL7_COC_CONTROL7_7                 (0x80)
-#define BIT_COC_CTL7_COC_CONTROL7_6                 (0x40)
-#define BIT_COC_CTL7_COC_CONTROL7_5                 (0x20)
-#define MSK_COC_CTL7_COC_CONTROL7_4_3               (0x18)
-#define MSK_COC_CTL7_COC_CONTROL7_2_0               (0x07)
+#define BIT_COC_CTL7_COC_CTRL7_7                    (0x80)
+#define BIT_COC_CTL7_COC_CTRL7_6                    (0x40)
+#define BIT_COC_CTL7_COC_CTRL7_5                    (0x20)
+#define MSK_COC_CTL7_COC_CTRL7_4_3                  (0x18)
+#define MSK_COC_CTL7_COC_CTRL7_2_0                  (0x07)
 
 /* 0x19 CoC 10th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTL9                                (0x0719)
-#define MSK_COC_CTL9_COC_CONTROL9                   (0xFF)
+#define MSK_COC_CTL9_COC_CTRL9                      (0xFF)
 
 /* 0x1A CoC 11th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTLA                                (0x071A)
-#define MSK_COC_CTLA_COC_CONTROLA                   (0xFF)
+#define MSK_COC_CTLA_COC_CTRLA                      (0xFF)
 
 /* 0x1B CoC 12th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTLB                                (0x071B)
-#define MSK_COC_CTLB_COC_CONTROLB                   (0xFF)
+#define MSK_COC_CTLB_COC_CTRLB                      (0xFF)
 
 /* 0x1C CoC 13th Ctl Register                              (Default: 0x0F)    */
 #define REG_COC_CTLC                                (0x071C)
-#define MSK_COC_CTLC_COC_CONTROLC                   (0xFF)
+#define MSK_COC_CTLC_COC_CTRLC                      (0xFF)
 
 /* 0x1D CoC 14th Ctl Register                              (Default: 0x0A)    */
 #define REG_COC_CTLD                                (0x071D)
-#define BIT_COC_CTLD_COC_CONTROLD_7                 (0x80)
-#define MSK_COC_CTLD_COC_CONTROLD_6_0               (0x7F)
+#define BIT_COC_CTLD_COC_CTRLD_7                    (0x80)
+#define MSK_COC_CTLD_COC_CTRLD_6_0                  (0x7F)
 
 /* 0x1E CoC 15th Ctl Register                              (Default: 0x0A)    */
 #define REG_COC_CTLE                                (0x071E)
-#define BIT_COC_CTLE_COC_CONTROLE_7                 (0x80)
-#define MSK_COC_CTLE_COC_CONTROLE_6_0               (0x7F)
+#define BIT_COC_CTLE_COC_CTRLE_7                    (0x80)
+#define MSK_COC_CTLE_COC_CTRLE_6_0                  (0x7F)
 
 /* 0x1F CoC 16th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTLF                                (0x071F)
-#define MSK_COC_CTLF_COC_CONTROLF_7_3               (0xF8)
-#define MSK_COC_CTLF_COC_CONTROLF_2_0               (0x07)
+#define MSK_COC_CTLF_COC_CTRLF_7_3                  (0xF8)
+#define MSK_COC_CTLF_COC_CTRLF_2_0                  (0x07)
 
 /* 0x21 CoC 18th Ctl Register                              (Default: 0x32)    */
 #define REG_COC_CTL11                               (0x0721)
-#define MSK_COC_CTL11_COC_CONTROL11_7_4             (0xF0)
-#define MSK_COC_CTL11_COC_CONTROL11_3_0             (0x0F)
+#define MSK_COC_CTL11_COC_CTRL11_7_4                (0xF0)
+#define MSK_COC_CTL11_COC_CTRL11_3_0                (0x0F)
 
 /* 0x24 CoC 21st Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTL14                               (0x0724)
-#define MSK_COC_CTL14_COC_CONTROL14_7_4             (0xF0)
-#define MSK_COC_CTL14_COC_CONTROL14_3_0             (0x0F)
+#define MSK_COC_CTL14_COC_CTRL14_7_4                (0xF0)
+#define MSK_COC_CTL14_COC_CTRL14_3_0                (0x0F)
 
 /* 0x25 CoC 22nd Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTL15                               (0x0725)
-#define BIT_COC_CTL15_COC_CONTROL15_7               (0x80)
-#define MSK_COC_CTL15_COC_CONTROL15_6_4             (0x70)
-#define MSK_COC_CTL15_COC_CONTROL15_3_0             (0x0F)
+#define BIT_COC_CTL15_COC_CTRL15_7                  (0x80)
+#define MSK_COC_CTL15_COC_CTRL15_6_4                (0x70)
+#define MSK_COC_CTL15_COC_CTRL15_3_0                (0x0F)
 
 /* 0x26 CoC Interrupt Register                             (Default: 0x00)    */
 #define REG_COC_INTR                                (0x0726)
@@ -1320,23 +1320,23 @@
 
 /* 0x2A CoC 24th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTL17                               (0x072A)
-#define MSK_COC_CTL17_COC_CONTROL17_7_4             (0xF0)
-#define MSK_COC_CTL17_COC_CONTROL17_3_0             (0x0F)
+#define MSK_COC_CTL17_COC_CTRL17_7_4                (0xF0)
+#define MSK_COC_CTL17_COC_CTRL17_3_0                (0x0F)
 
 /* 0x2B CoC 25th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTL18                               (0x072B)
-#define MSK_COC_CTL18_COC_CONTROL18_7_4             (0xF0)
-#define MSK_COC_CTL18_COC_CONTROL18_3_0             (0x0F)
+#define MSK_COC_CTL18_COC_CTRL18_7_4                (0xF0)
+#define MSK_COC_CTL18_COC_CTRL18_3_0                (0x0F)
 
 /* 0x2C CoC 26th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTL19                               (0x072C)
-#define MSK_COC_CTL19_COC_CONTROL19_7_4             (0xF0)
-#define MSK_COC_CTL19_COC_CONTROL19_3_0             (0x0F)
+#define MSK_COC_CTL19_COC_CTRL19_7_4                (0xF0)
+#define MSK_COC_CTL19_COC_CTRL19_3_0                (0x0F)
 
 /* 0x2D CoC 27th Ctl Register                              (Default: 0x00)    */
 #define REG_COC_CTL1A                               (0x072D)
-#define MSK_COC_CTL1A_COC_CONTROL1A_7_2             (0xFC)
-#define MSK_COC_CTL1A_COC_CONTROL1A_1_0             (0x03)
+#define MSK_COC_CTL1A_COC_CTRL1A_7_2                (0xFC)
+#define MSK_COC_CTL1A_COC_CTRL1A_1_0                (0x03)
 
 /* 0x40 DoC 9th Status Register                            (Default: 0x00)    */
 #define REG_DOC_STAT_8                              (0x0740)
@@ -1355,40 +1355,40 @@
 
 /* 0x57 DoC 7th Ctl Register                               (Default: 0x00)    */
 #define REG_DOC_CTL6                                (0x0757)
-#define BIT_DOC_CTL6_DOC_CONTROL6_7                 (0x80)
-#define BIT_DOC_CTL6_DOC_CONTROL6_6                 (0x40)
-#define MSK_DOC_CTL6_DOC_CONTROL6_5_4               (0x30)
-#define MSK_DOC_CTL6_DOC_CONTROL6_3_0               (0x0F)
+#define BIT_DOC_CTL6_DOC_CTRL6_7                    (0x80)
+#define BIT_DOC_CTL6_DOC_CTRL6_6                    (0x40)
+#define MSK_DOC_CTL6_DOC_CTRL6_5_4                  (0x30)
+#define MSK_DOC_CTL6_DOC_CTRL6_3_0                  (0x0F)
 
 /* 0x58 DoC 8th Ctl Register                               (Default: 0x00)    */
 #define REG_DOC_CTL7                                (0x0758)
-#define BIT_DOC_CTL7_DOC_CONTROL7_7                 (0x80)
-#define BIT_DOC_CTL7_DOC_CONTROL7_6                 (0x40)
-#define BIT_DOC_CTL7_DOC_CONTROL7_5                 (0x20)
-#define MSK_DOC_CTL7_DOC_CONTROL7_4_3               (0x18)
-#define MSK_DOC_CTL7_DOC_CONTROL7_2_0               (0x07)
+#define BIT_DOC_CTL7_DOC_CTRL7_7                    (0x80)
+#define BIT_DOC_CTL7_DOC_CTRL7_6                    (0x40)
+#define BIT_DOC_CTL7_DOC_CTRL7_5                    (0x20)
+#define MSK_DOC_CTL7_DOC_CTRL7_4_3                  (0x18)
+#define MSK_DOC_CTL7_DOC_CTRL7_2_0                  (0x07)
 
 /* 0x6C DoC 9th Ctl Register                               (Default: 0x00)    */
 #define REG_DOC_CTL8                                (0x076C)
-#define BIT_DOC_CTL8_DOC_CONTROL8_7                 (0x80)
-#define MSK_DOC_CTL8_DOC_CONTROL8_6_4               (0x70)
-#define MSK_DOC_CTL8_DOC_CONTROL8_3_2               (0x0C)
-#define MSK_DOC_CTL8_DOC_CONTROL8_1_0               (0x03)
+#define BIT_DOC_CTL8_DOC_CTRL8_7                    (0x80)
+#define MSK_DOC_CTL8_DOC_CTRL8_6_4                  (0x70)
+#define MSK_DOC_CTL8_DOC_CTRL8_3_2                  (0x0C)
+#define MSK_DOC_CTL8_DOC_CTRL8_1_0                  (0x03)
 
 /* 0x6D DoC 10th Ctl Register                              (Default: 0x00)    */
 #define REG_DOC_CTL9                                (0x076D)
-#define MSK_DOC_CTL9_DOC_CONTROL9                   (0xFF)
+#define MSK_DOC_CTL9_DOC_CTRL9                      (0xFF)
 
 /* 0x6E DoC 11th Ctl Register                              (Default: 0x00)    */
 #define REG_DOC_CTLA                                (0x076E)
-#define MSK_DOC_CTLA_DOC_CONTROLA                   (0xFF)
+#define MSK_DOC_CTLA_DOC_CTRLA                      (0xFF)
 
 /* 0x72 DoC 15th Ctl Register                              (Default: 0x00)    */
 #define REG_DOC_CTLE                                (0x0772)
-#define BIT_DOC_CTLE_DOC_CONTROLE_7                 (0x80)
-#define BIT_DOC_CTLE_DOC_CONTROLE_6                 (0x40)
-#define MSK_DOC_CTLE_DOC_CONTROLE_5_4               (0x30)
-#define MSK_DOC_CTLE_DOC_CONTROLE_3_0               (0x0F)
+#define BIT_DOC_CTLE_DOC_CTRLE_7                    (0x80)
+#define BIT_DOC_CTLE_DOC_CTRLE_6                    (0x40)
+#define MSK_DOC_CTLE_DOC_CTRLE_5_4                  (0x30)
+#define MSK_DOC_CTLE_DOC_CTRLE_3_0                  (0x0F)
 
 /* Registers in TX_PAGE_5 (0x00-0xFF)                                         */
 
@@ -1413,29 +1413,29 @@
 #define MSK_MDT_XMIT_TIMEOUT_MDT_XMIT_TIMEOUT_MAX_MSB (0xFF)
 
 /* 0x86 MDT Receive Control Register                       (Default: 0x00)    */
-#define REG_MDT_RCV_CONTROL                         (0x0586)
-#define BIT_MDT_RCV_CONTROL_MDT_RCV_EN              (0x80)
-#define BIT_MDT_RCV_CONTROL_MDT_DELAY_RCV_EN        (0x40)
-#define BIT_MDT_RCV_CONTROL_MDT_RFIFO_OVER_WR_EN    (0x10)
-#define BIT_MDT_RCV_CONTROL_MDT_XFIFO_OVER_WR_EN    (0x08)
-#define BIT_MDT_RCV_CONTROL_MDT_DISABLE             (0x04)
-#define BIT_MDT_RCV_CONTROL_MDT_RFIFO_CLR_ALL       (0x02)
-#define BIT_MDT_RCV_CONTROL_MDT_RFIFO_CLR_CUR       (0x01)
+#define REG_MDT_RCV_CTRL                            (0x0586)
+#define BIT_MDT_RCV_CTRL_MDT_RCV_EN                 (0x80)
+#define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN           (0x40)
+#define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN       (0x10)
+#define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN       (0x08)
+#define BIT_MDT_RCV_CTRL_MDT_DISABLE                (0x04)
+#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL          (0x02)
+#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR          (0x01)
 
 /* 0x87 MDT Receive Read Port                              (Default: 0x00)    */
 #define REG_MDT_RCV_READ_PORT                       (0x0587)
 #define MSK_MDT_RCV_READ_PORT_MDT_RFIFO_DATA        (0xFF)
 
 /* 0x88 MDT Transmit Control Register                      (Default: 0x70)    */
-#define REG_MDT_XMIT_CONTROL                        (0x0588)
-#define BIT_MDT_XMIT_CONTROL_MDT_XMIT_EN            (0x80)
-#define BIT_MDT_XMIT_CONTROL_MDT_XMIT_CMD_MERGE_EN  (0x40)
-#define BIT_MDT_XMIT_CONTROL_MDT_XMIT_FIXED_BURST_LEN (0x20)
-#define BIT_MDT_XMIT_CONTROL_MDT_XMIT_FIXED_AID     (0x10)
-#define BIT_MDT_XMIT_CONTROL_MDT_XMIT_SINGLE_RUN_EN (0x08)
-#define BIT_MDT_XMIT_CONTROL_MDT_CLR_ABORT_WAIT     (0x04)
-#define BIT_MDT_XMIT_CONTROL_MDT_XFIFO_CLR_ALL      (0x02)
-#define BIT_MDT_XMIT_CONTROL_MDT_XFIFO_CLR_CUR      (0x01)
+#define REG_MDT_XMIT_CTRL                           (0x0588)
+#define BIT_MDT_XMIT_CTRL_MDT_XMIT_EN               (0x80)
+#define BIT_MDT_XMIT_CTRL_MDT_XMIT_CMD_MERGE_EN     (0x40)
+#define BIT_MDT_XMIT_CTRL_MDT_XMIT_FIXED_BURST_LEN  (0x20)
+#define BIT_MDT_XMIT_CTRL_MDT_XMIT_FIXED_AID        (0x10)
+#define BIT_MDT_XMIT_CTRL_MDT_XMIT_SINGLE_RUN_EN    (0x08)
+#define BIT_MDT_XMIT_CTRL_MDT_CLR_ABORT_WAIT        (0x04)
+#define BIT_MDT_XMIT_CTRL_MDT_XFIFO_CLR_ALL         (0x02)
+#define BIT_MDT_XMIT_CTRL_MDT_XFIFO_CLR_CUR         (0x01)
 
 /* 0x89 MDT Receive WRITE Port                             (Default: 0x00)    */
 #define REG_MDT_XMIT_WRITE_PORT                     (0x0589)
@@ -1534,8 +1534,8 @@
 #define REG_CBUS_RX_DISC_INT0_MASK                  (0x059F)
 
 /* 0xA7 CBUS_Link_Layer Control #8 Register                (Default: 0x00)    */
-#define REG_CBUS_LINK_CONTROL_8                     (0x05A7)
-#define MSK_CBUS_LINK_CONTROL_8_LNK_XMIT_BIT_TIME   (0xFF)
+#define REG_CBUS_LINK_CTRL_8                        (0x05A7)
+#define MSK_CBUS_LINK_CTRL_8_LNK_XMIT_BIT_TIME      (0xFF)
 
 /* 0xB5 MDT State Machine Status Register                  (Default: 0x00)    */
 #define REG_MDT_SM_STAT                             (0x05B5)
@@ -1567,18 +1567,18 @@
 #define REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA            (0x05C0)
 
 /* 0xC4 CBUS MSC Heartbeat Control Register                (Default: 0x27)    */
-#define REG_MSC_HEARTBEAT_CONTROL                   (0x05C4)
-#define BIT_MSC_HEARTBEAT_CONTROL_MSC_HB_EN         (0x80)
-#define MSK_MSC_HEARTBEAT_CONTROL_MSC_HB_FAIL_LIMIT (0x70)
-#define MSK_MSC_HEARTBEAT_CONTROL_MSC_HB_PERIOD_MSB (0x0F)
+#define REG_MSC_HEARTBEAT_CTRL                      (0x05C4)
+#define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN            (0x80)
+#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_FAIL_LIMIT    (0x70)
+#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_PERIOD_MSB    (0x0F)
 
 /* 0xC7 CBUS MSC Compatibility Control Register            (Default: 0x02)    */
-#define REG_CBUS_MSC_COMPATIBILITY_CONTROL          (0x05C7)
-#define BIT_CBUS_MSC_COMPATIBILITY_CONTROL_XDEVCAP_EN (0x80)
-#define BIT_CBUS_MSC_COMPATIBILITY_CONTROL_DISABLE_MSC_ON_CBUS (0x40)
-#define BIT_CBUS_MSC_COMPATIBILITY_CONTROL_DISABLE_DDC_ON_CBUS (0x20)
-#define BIT_CBUS_MSC_COMPATIBILITY_CONTROL_DISABLE_GET_DDC_ERRORCODE (0x08)
-#define BIT_CBUS_MSC_COMPATIBILITY_CONTROL_DISABLE_GET_VS1_ERRORCODE (0x04)
+#define REG_CBUS_MSC_COMPAT_CTRL                    (0x05C7)
+#define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN         (0x80)
+#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS (0x40)
+#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS (0x20)
+#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE (0x08)
+#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE (0x04)
 
 /* 0xDC CBUS3 Converter Control Register                   (Default: 0x24)    */
 #define REG_CBUS3_CNVT                              (0x05DC)
diff --git a/include/linux/mhl.h b/include/linux/mhl.h
index 44840f4c85a2..10b0c627585e 100644
--- a/include/linux/mhl.h
+++ b/include/linux/mhl.h
@@ -5,7 +5,7 @@
 enum {
 	MHL_DCAP_DEV_STATE,
 	MHL_DCAP_MHL_VERSION,
-	MHL_DCAP_DEV_CAT,
+	MHL_DCAP_CAT,
 	MHL_DCAP_ADOPTER_ID_H,
 	MHL_DCAP_ADOPTER_ID_L,
 	MHL_DCAP_VID_LINK_MODE,