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authorAndrzej Hajda <a.hajda@samsung.com>2016-12-12 14:18:26 +0100
committerSeung-Woo Kim <sw0312.kim@samsung.com>2016-12-14 13:54:35 +0900
commit141d04287de37ac7f6827577db839bf7f34f0ec1 (patch)
tree3f94f4bf7a03308002ab272a1472b756fdfe7cb1
parent529e2563be6f371b31ad0c1742f688359c997d54 (diff)
drm/exynos/hdmi: fix PLL for 27MHz settings
Current settings for 27MHz and 27.027MHz do not work. Use the settings from vendor code instead. Change-Id: I701555eff3fca430736664e0f628fc50d9a6dc4f Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 206d94566e47..f3e3cd728f2a 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -527,9 +527,9 @@ static const struct hdmiphy_config hdmiphy_5430_configs[] = {
{
.pixel_clock = 27000000,
.conf = {
- 0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,
- 0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
- 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
+ 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
+ 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+ 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
},
},
@@ -537,9 +537,9 @@ static const struct hdmiphy_config hdmiphy_5430_configs[] = {
.pixel_clock = 27027000,
.conf = {
0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
- 0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,
- 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
- 0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
+ 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
+ 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
+ 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
},
},
{