diff options
| author | Andrzej Hajda <a.hajda@samsung.com> | 2016-10-20 09:14:42 +0200 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:54:00 +0900 |
| commit | 718043540ad720f6280bf138f3aa4b08773abe43 (patch) | |
| tree | 29c168cf0991ec8c77d5c1830dec772191c23e93 | |
| parent | 5449b94261986faa96296d10b32080402e9dbda9 (diff) | |
drm/exynos/hdmi: add 297MHz pixel clock support
297MHz is used by UHD modes.
Change-Id: I2040adcc3f132dbf1d510309527a9e1574008961
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_hdmi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 3e526ccdc7e7..f512696d7d4d 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -711,6 +711,15 @@ static const struct hdmiphy_config hdmiphy_5430_configs[] = { 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, }, }, + { + .pixel_clock = 297000000, + .conf = { + 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2, + 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, + 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, + 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, + }, + }, }; static const char *hdmi_clk_gates4[] = { |