diff options
| author | Hyungwon Hwang <human.hwang@samsung.com> | 2015-04-21 10:23:00 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:43:24 +0900 |
| commit | 663a75c9fe3236f8e92b2f5c5caed60d6f3645bb (patch) | |
| tree | 9b08c2f761014854fada303a3250f30f0b5bd514 /drivers/gpu/drm/exynos/exynos_drm_dsi.c | |
| parent | 4d830e7a681ddbd49054ebc5699a5f999f207efc (diff) | |
LOCAL / drm/exynos: fix the bug during generalizing the register setting
From the commit f9f70912f41e347acd60e22ad0bb6962e83add81 (drm/exynos:
dsi: generalize register setting and clock control), plltmr setting
has not been done correctly. Also, there was a line which does not use
the newly introduced macro. This patch fixes the problem, make all
code in the driver use the new macro, and clean up the code.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/exynos_drm_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 45dc05125b6f..9b6fd4673422 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -207,8 +207,8 @@ #define DSI_RX_FIFO_EMPTY 0x30800002 #define REG(dsi, reg) ((dsi)->reg_base + dsi->driver_data->regs[(reg)]) -#define DSI_WRITE(dsi, reg, val) writel((val), REG((dsi), (reg))); -#define DSI_READ(dsi, reg) readl(REG((dsi), (reg))); +#define DSI_WRITE(dsi, reg, val) writel((val), REG((dsi), (reg))) +#define DSI_READ(dsi, reg) readl(REG((dsi), (reg))) static char *clk_names[5] = { "bus_clk", "sclk_mipi", "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", @@ -592,7 +592,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, } dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); - DSI_WRITE(dsi, driver_data->plltmr_reg, driver_data->values[PLL_TIMER]); + writel(driver_data->values[PLL_TIMER], + dsi->reg_base + driver_data->plltmr_reg); reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); @@ -634,8 +635,6 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) unsigned long esc_div; u32 reg; - reg = DSI_READ(dsi, DSIM_STATUS_REG); - hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); @@ -1078,7 +1077,7 @@ static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, clear_fifo: length = DSI_RX_FIFO_SIZE / 4; do { - reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); + reg = DSI_READ(dsi, DSIM_RXFIFO_REG); if (reg == DSI_RX_FIFO_EMPTY) break; } while (--length); |