diff options
| author | Matthew Auld <matthew.auld@intel.com> | 2021-02-03 17:12:31 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2021-03-24 19:31:59 +0100 |
| commit | e762bdf582af5b4c9af654553b3c5efc84c7ff65 (patch) | |
| tree | c9484bf51df22a94c040f9ba685f18ab6cbec228 /drivers/gpu/drm/i915/gt/intel_gtt.h | |
| parent | 11724eea0d57c5bf82bf1d0082819d407f1c886e (diff) | |
drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
BSpec: 45015
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20210203171231.551338-3-matthew.auld@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gtt.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gtt.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 0eef625dd787..24b5808df16d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -85,7 +85,9 @@ typedef u64 gen8_pte_t; #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) #define BYT_PTE_WRITEABLE REG_BIT(1) -#define GEN12_PPGTT_PTE_LM BIT_ULL(11) +#define GEN12_PPGTT_PTE_LM BIT_ULL(11) + +#define GEN12_GGTT_PTE_LM BIT_ULL(1) /* * Cacheability Control is a 4-bit value. The low three bits are stored in bits |