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authorJani Nikula <jani.nikula@intel.com>2021-12-02 16:44:56 +0200
committerJani Nikula <jani.nikula@intel.com>2021-12-07 10:41:07 +0200
commit61b98486e4314d39d43921680d68b46c3083b22e (patch)
tree2b5946145b0f9af8df90a8c999542b2ffca2f8f5 /drivers/gpu/drm/i915/i915_reg.h
parent1c7ab5affa5e73ed75732be2f2fabe1ae86c82e1 (diff)
drm/i915/snps: use div32 version of MPLLB word clock for UHBR
The mode set sequence for 128b/132b requires setting the div32 version of MPLLB clock. Bspec: 53880, 54128 Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b0f5865482a0..1a135a73dcd9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2247,6 +2247,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
+#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)