diff options
| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2017-02-09 13:24:41 +1100 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2017-02-09 13:24:41 +1100 |
| commit | 6ebd7f5f95c80e78398c4bd35d6ad0cd483438fe (patch) | |
| tree | 47c28d279d0d382c34db0006aa75fe1c49144c25 /include | |
| parent | 107d43e6f960cc08efe39bad7458926769592e02 (diff) | |
| parent | 744cc304a18f1c9de4f3215fbe93fe878f934179 (diff) | |
Merge remote-tracking branch 'battery/for-next'
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mfd/axp20x.h | 2 | ||||
| -rw-r--r-- | include/linux/power/bq27xxx_battery.h | 12 | ||||
| -rw-r--r-- | include/soc/at91/at91sam9_ddrsdr.h | 3 |
3 files changed, 14 insertions, 3 deletions
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 0aa4ef7157b8..0d9a1ff38393 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -13,7 +13,7 @@ #include <linux/regmap.h> -enum { +enum axp20x_variants { AXP152_ID = 0, AXP202_ID, AXP209_ID, diff --git a/include/linux/power/bq27xxx_battery.h b/include/linux/power/bq27xxx_battery.h index bed9557b69e7..b312bcef53da 100644 --- a/include/linux/power/bq27xxx_battery.h +++ b/include/linux/power/bq27xxx_battery.h @@ -4,8 +4,16 @@ enum bq27xxx_chip { BQ27000 = 1, /* bq27000, bq27200 */ BQ27010, /* bq27010, bq27210 */ - BQ27500, /* bq27500 */ - BQ27510, /* bq27510, bq27520 */ + BQ2750X, /* bq27500 deprecated alias */ + BQ2751X, /* bq27510, bq27520 deprecated alias */ + BQ27500, /* bq27500/1 */ + BQ27510G1, /* bq27510G1 */ + BQ27510G2, /* bq27510G2 */ + BQ27510G3, /* bq27510G3 */ + BQ27520G1, /* bq27520G1 */ + BQ27520G2, /* bq27520G2 */ + BQ27520G3, /* bq27520G3 */ + BQ27520G4, /* bq27520G4 */ BQ27530, /* bq27530, bq27531 */ BQ27541, /* bq27541, bq27542, bq27546, bq27742 */ BQ27545, /* bq27545 */ diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h index dc10c52e0e91..393362bdb860 100644 --- a/include/soc/at91/at91sam9_ddrsdr.h +++ b/include/soc/at91/at91sam9_ddrsdr.h @@ -81,6 +81,7 @@ #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ +#define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */ #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ @@ -96,7 +97,9 @@ #define AT91_DDRSDRC_MD_SDR 0 #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 +#define AT91_DDRSDRC_MD_LPDDR3 5 #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ +#define AT91_DDRSDRC_MD_LPDDR2 7 #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ #define AT91_DDRSDRC_DBW_32BITS (0 << 4) #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |