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-rw-r--r--drivers/gpu/drm/bridge/sil-sii8620.c38
-rw-r--r--drivers/gpu/drm/bridge/sil-sii8620.h10
2 files changed, 44 insertions, 4 deletions
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 3debe98ecdc1..ab32b8bba684 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -484,9 +484,47 @@ static void sii8620_sink_detected(struct sii8620 *ctx, int ret)
dev_info(dev, "detected sink(type: %s)\n", sink_str[ctx->sink_type]);
}
+static void sii8620_hsic_init(struct sii8620 *ctx)
+{
+ if (ctx->mode < CM_MHL3)
+ return;
+
+ sii8620_write(ctx, REG_FCGC,
+ BIT_FCGC_HSIC_HOSTMODE | BIT_FCGC_HSIC_ENABLE);
+ sii8620_setbits(ctx, REG_HRXCTRL3,
+ BIT_HRXCTRL3_HRX_STAY_RESET | BIT_HRXCTRL3_STATUS_EN, ~0);
+ sii8620_setbits(ctx, REG_TTXNUMB, MSK_TTXNUMB_TTX_NUMBPS, 4);
+ sii8620_setbits(ctx, REG_TRXCTRL, BIT_TRXCTRL_TRX_FROM_SE_COC, ~0);
+ sii8620_setbits(ctx, REG_HTXCTRL, BIT_HTXCTRL_HTX_DRVCONN1, 0);
+ sii8620_setbits(ctx, REG_KEEPER, MSK_KEEPER_MODE, VAL_KEEPER_MODE_HOST);
+ sii8620_write_seq_static(ctx,
+ REG_TDMLLCTL, 0,
+ REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST |
+ BIT_UTSRST_KEEPER_SRST | BIT_UTSRST_FC_SRST,
+ REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST,
+ REG_HRXINTL, 0xff,
+ REG_HRXINTH, 0xff,
+ REG_TTXINTL, 0xff,
+ REG_TTXINTH, 0xff,
+ REG_TRXINTL, 0xff,
+ REG_TRXINTH, 0xff,
+ REG_HTXINTL, 0xff,
+ REG_HTXINTH, 0xff,
+ REG_FCINTR0, 0xff,
+ REG_FCINTR1, 0xff,
+ REG_FCINTR2, 0xff,
+ REG_FCINTR3, 0xff,
+ REG_FCINTR4, 0xff,
+ REG_FCINTR5, 0xff,
+ REG_FCINTR6, 0xff,
+ REG_FCINTR7, 0xff
+ );
+}
+
static void sii8620_edid_read(struct sii8620 *ctx, int ret)
{
sii8620_set_upstream_edid(ctx);
+ sii8620_hsic_init(ctx);
sii8620_enable_hpd(ctx);
}
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.h b/drivers/gpu/drm/bridge/sil-sii8620.h
index e42c1c30b2f6..30cc992acef9 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.h
+++ b/drivers/gpu/drm/bridge/sil-sii8620.h
@@ -353,7 +353,7 @@
#define REG_TTXNUMB 0x0116
#define MSK_TTXNUMB_TTX_AFFCTRL_3_0 0xf0
#define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3)
-#define MSK_TTXNUMB_TTX_NUMBPS_2_0 0x07
+#define MSK_TTXNUMB_TTX_NUMBPS 0x07
/* TDM TX NUMSPISYM, default value: 0x04 */
#define REG_TTXSPINUMS 0x0117
@@ -433,12 +433,14 @@
/* HSIC Keeper, default value: 0x00 */
#define REG_KEEPER 0x0181
-#define MSK_KEEPER_KEEPER_MODE_1_0 0x03
+#define MSK_KEEPER_MODE 0x03
+#define VAL_KEEPER_MODE_HOST 0
+#define VAL_KEEPER_MODE_DEVICE 2
/* HSIC Flow Control General, default value: 0x02 */
#define REG_FCGC 0x0183
-#define BIT_FCGC_HSIC_FC_HOSTMODE BIT(1)
-#define BIT_FCGC_HSIC_FC_ENABLE BIT(0)
+#define BIT_FCGC_HSIC_HOSTMODE BIT(1)
+#define BIT_FCGC_HSIC_ENABLE BIT(0)
/* HSIC Flow Control CTR13, default value: 0xfc */
#define REG_FCCTR13 0x0191