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path: root/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c30
1 files changed, 24 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
index ea78da9c6f8b..232cc15979dd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c
@@ -184,7 +184,8 @@ void dccg314_set_dtbclk_dto(
void dccg314_set_dpstreamclk(
struct dccg *dccg,
enum streamclk_source src,
- int otg_inst)
+ int otg_inst,
+ int dp_hpo_inst)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
@@ -192,26 +193,26 @@ void dccg314_set_dpstreamclk(
dccg314_set_dtbclk_p_src(dccg, src, otg_inst);
/* enabled to select one of the DTBCLKs for pipe */
- switch (otg_inst) {
+ switch (dp_hpo_inst) {
case 0:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1,
- DPSTREAMCLK0_SRC_SEL, 0);
+ DPSTREAMCLK0_SRC_SEL, otg_inst);
break;
case 1:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1,
- DPSTREAMCLK1_SRC_SEL, 1);
+ DPSTREAMCLK1_SRC_SEL, otg_inst);
break;
case 2:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1,
- DPSTREAMCLK2_SRC_SEL, 2);
+ DPSTREAMCLK2_SRC_SEL, otg_inst);
break;
case 3:
REG_UPDATE_2(DPSTREAMCLK_CNTL,
DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1,
- DPSTREAMCLK3_SRC_SEL, 3);
+ DPSTREAMCLK3_SRC_SEL, otg_inst);
break;
default:
BREAK_TO_DEBUGGER();
@@ -219,6 +220,21 @@ void dccg314_set_dpstreamclk(
}
}
+void dccg314_set_valid_pixel_rate(
+ struct dccg *dccg,
+ int ref_dtbclk_khz,
+ int otg_inst,
+ int pixclk_khz)
+{
+ struct dtbclk_dto_params dto_params = {0};
+
+ dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
+ dto_params.otg_inst = otg_inst;
+ dto_params.pixclk_khz = pixclk_khz;
+
+ dccg314_set_dtbclk_dto(dccg, &dto_params);
+}
+
static const struct dccg_funcs dccg314_funcs = {
.update_dpp_dto = dccg31_update_dpp_dto,
.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
@@ -237,6 +253,8 @@ static const struct dccg_funcs dccg314_funcs = {
.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
.disable_dsc = dccg31_disable_dscclk,
.enable_dsc = dccg31_enable_dscclk,
+ .set_pixel_rate_div = dccg314_set_pixel_rate_div,
+ .set_valid_pixel_rate = dccg314_set_valid_pixel_rate,
};
struct dccg *dccg314_create(