From a4b78abe0bb3e646bd9550d88fbaa9d8ecf14089 Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Tue, 6 Dec 2016 14:59:35 +0100 Subject: drm/bridge/sii8620: enable MHL3 mode if possible Since all sub-protocols of MHL3 are already supported MHL3 mode can be enabled. With this patch it is possible to use packed pixel modes and clocks up to 300MHz - 1920x1080@60Hz and 4K modes. Change-Id: I04ade01bff1af0cd0c44818bd4be45a33acf2ecd Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/bridge/sil-sii8620.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index ab32b8bba684..c03ec5ddd1d2 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -1364,8 +1364,7 @@ static void sii8620_mhl_init(struct sii8620 *ctx) ); sii8620_disable_gen2_write_burst(ctx); - /* currently MHL3 is not supported, so we force version to 0 */ - sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), 0); + sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP | MHL_DST_CONN_POW_STAT); @@ -1632,14 +1631,16 @@ static void sii8620_irq_g2wb(struct sii8620 *ctx) sii8620_write(ctx, REG_MDT_INT_0, stat); } -static void sii8620_status_changed_dcap(struct sii8620 *ctx) +static void sii8620_status_dcap_ready(struct sii8620 *ctx) { - if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) { - sii8620_set_mode(ctx, CM_MHL1); - sii8620_peer_specific_init(ctx); - sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE - | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); - } + enum sii8620_mode mode; + + mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; + if (mode > ctx->mode) + sii8620_set_mode(ctx, mode); + sii8620_peer_specific_init(ctx); + sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE + | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); } static void sii8620_status_changed_path(struct sii8620 *ctx) @@ -1667,8 +1668,8 @@ static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); - if (st[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) - sii8620_status_changed_dcap(ctx); + if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) + sii8620_status_dcap_ready(ctx); if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) sii8620_status_changed_path(ctx); -- cgit v1.2.3