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authorAndi Shyti <andi@smida.it>2014-03-06 14:45:03 +0100
committerAndi Shyti <andi@smida.it>2014-03-06 14:45:03 +0100
commitb749e3d87ba596cfd50a2e79e10809c0e7d12554 (patch)
treeb8a1989795e5043c0e52656c768aead176d9b8e2
ledspy: initialized kicad repository
ledspy is a simple schematic and PCB layout for debugging gpio pins with an led. It uses two resistors, une bjt transistor and of course the led. Signed-off-by: Andi Shyti <andi@smida.it>
Diffstat
-rw-r--r--_autosave-ledspy.kicad_pcb370
-rw-r--r--ledspy-cache.lib115
-rw-r--r--ledspy.bak163
-rw-r--r--ledspy.cmp38
-rw-r--r--ledspy.kicad_pcb362
-rw-r--r--ledspy.kicad_pcb-bak356
-rw-r--r--ledspy.net115
-rw-r--r--ledspy.pro86
-rw-r--r--ledspy.sch164
-rw-r--r--output/ledspy-B_Cu.pdfbin0 -> 3903 bytes
-rw-r--r--output/ledspy-B_Cu.svg705
-rw-r--r--output/ledspy-B_Mask.pdfbin0 -> 2471 bytes
-rw-r--r--output/ledspy-B_Mask.svg160
-rw-r--r--output/ledspy-F_SilkS.pdfbin0 -> 4035 bytes
-rw-r--r--output/ledspy-F_SilkS.svg377
-rw-r--r--output/ledspy.pdfbin0 -> 10931 bytes
-rw-r--r--output/ledspy.pngbin0 -> 48105 bytes
17 files changed, 3011 insertions, 0 deletions
diff --git a/_autosave-ledspy.kicad_pcb b/_autosave-ledspy.kicad_pcb
new file mode 100644
index 0000000..d341ecb
--- /dev/null
+++ b/_autosave-ledspy.kicad_pcb
@@ -0,0 +1,370 @@
+(kicad_pcb (version 3) (host pcbnew "(2014-02-28 BZR 4729)-product")
+
+ (general
+ (links 6)
+ (no_connects 0)
+ (area 138.657693 99.009999 167.904886 114.350001)
+ (thickness 1.6)
+ (drawings 7)
+ (tracks 17)
+ (zones 0)
+ (modules 5)
+ (nets 7)
+ )
+
+ (page A4)
+ (title_block
+ (title "GPIO Led Spy")
+ (date "02 Mar 2014")
+ (rev 1.0)
+ (company www.smida.it)
+ (comment 1 "Andi Shyti")
+ )
+
+ (layers
+ (15 F.Cu signal hide)
+ (0 B.Cu signal)
+ (16 B.Adhes user hide)
+ (17 F.Adhes user hide)
+ (18 B.Paste user)
+ (19 F.Paste user hide)
+ (20 B.SilkS user hide)
+ (21 F.SilkS user)
+ (22 B.Mask user)
+ (23 F.Mask user)
+ (24 Dwgs.User user hide)
+ (25 Cmts.User user hide)
+ (26 Eco1.User user hide)
+ (27 Eco2.User user hide)
+ (28 Edge.Cuts user hide)
+ )
+
+ (setup
+ (last_trace_width 0.254)
+ (user_trace_width 0.5)
+ (trace_clearance 0.254)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.254)
+ (segment_width 0.2)
+ (edge_width 0.1)
+ (via_size 0.889)
+ (via_drill 0.635)
+ (via_min_size 0.889)
+ (via_min_drill 0.508)
+ (uvia_size 0.508)
+ (uvia_drill 0.127)
+ (uvias_allowed no)
+ (uvia_min_size 0.508)
+ (uvia_min_drill 0.127)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1.5 1.5)
+ (pad_drill 0.6)
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 0 0)
+ (visible_elements FFFFFB1F)
+ (pcbplotparams
+ (layerselection 6291457)
+ (usegerberextensions false)
+ (excludeedgelayer true)
+ (linewidth 0.150000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (hpglpenoverlay 2)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotothertext true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 4)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 GND)
+ (net 2 "Net-(D1-Pad1)")
+ (net 3 "Net-(D1-Pad2)")
+ (net 4 "Net-(K1-Pad2)")
+ (net 5 "Net-(K1-Pad3)")
+ (net 6 "Net-(Q1-Pad2)")
+
+ (net_class Default "This is the default net class."
+ (clearance 0.254)
+ (trace_width 0.254)
+ (via_dia 0.889)
+ (via_drill 0.635)
+ (uvia_dia 0.508)
+ (uvia_drill 0.127)
+ (add_net "")
+ (add_net GND)
+ (add_net "Net-(D1-Pad1)")
+ (add_net "Net-(D1-Pad2)")
+ (add_net "Net-(K1-Pad2)")
+ (add_net "Net-(K1-Pad3)")
+ (add_net "Net-(Q1-Pad2)")
+ )
+
+ (module LEDs:LED-5MM (layer F.Cu) (tedit 531143E7) (tstamp 53114403)
+ (at 143.51 109.22 90)
+ (descr "LED 5mm - Lead pitch 100mil (2,54mm)")
+ (tags "LED led 5mm 5MM 100mil 2,54mm")
+ (path /53110A0F)
+ (fp_text reference D1 (at 0 -3.81 90) (layer F.SilkS)
+ (effects (font (size 0.762 0.762) (thickness 0.0889)))
+ )
+ (fp_text value LED (at 0 3.81 90) (layer F.SilkS)
+ (effects (font (size 0.762 0.762) (thickness 0.0889)))
+ )
+ (fp_line (start 2.8448 1.905) (end 2.8448 -1.905) (layer F.SilkS) (width 0.2032))
+ (fp_circle (center 0.254 0) (end -1.016 1.27) (layer F.SilkS) (width 0.0762))
+ (fp_arc (start 0.254 0) (end 2.794 1.905) (angle 286.2) (layer F.SilkS) (width 0.254))
+ (fp_arc (start 0.254 0) (end -0.889 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end 1.397 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end -1.397 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end 1.905 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end -1.905 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end 2.413 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (pad 1 thru_hole circle (at -1.27 0 90) (size 1.6764 1.6764) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 2 "Net-(D1-Pad1)"))
+ (pad 2 thru_hole circle (at 1.27 0 90) (size 1.6764 1.6764) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 3 "Net-(D1-Pad2)"))
+ (model discret/leds/led5_vertical_verde.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Pin_Headers:Pin_Header_Straight_1x03 (layer F.Cu) (tedit 531143E6) (tstamp 53114411)
+ (at 163.83 106.68 270)
+ (descr "1 pin")
+ (tags "CONN DEV")
+ (path /53110A37)
+ (fp_text reference K1 (at 0 -2.286 270) (layer F.SilkS)
+ (effects (font (size 1.27 1.27) (thickness 0.2032)))
+ )
+ (fp_text value CONN_3 (at 0 0 270) (layer F.SilkS) hide
+ (effects (font (size 1.27 1.27) (thickness 0.2032)))
+ )
+ (fp_line (start -1.27 1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start 3.81 1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start 3.81 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 -1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.254))
+ (pad 1 thru_hole rect (at -2.54 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND))
+ (pad 2 thru_hole oval (at 0 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 4 "Net-(K1-Pad2)"))
+ (pad 3 thru_hole oval (at 2.54 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 5 "Net-(K1-Pad3)"))
+ (model Pin_Headers/Pin_Header_Straight_1x03.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Discret:TO92PN (layer F.Cu) (tedit 531143E8) (tstamp 53114420)
+ (at 143.51 102.87 180)
+ (path /53110A23)
+ (fp_text reference Q1 (at -0.1 -1.1 180) (layer F.SilkS)
+ (effects (font (size 0.7 0.7) (thickness 0.15)))
+ )
+ (fp_text value BC547 (at 0 0.6 180) (layer F.SilkS)
+ (effects (font (size 0.6 0.6) (thickness 0.15)))
+ )
+ (fp_line (start 1.3 1.9) (end -1.3 1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start -2.5 -1.7) (end -2.3 -1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start -2.3 -1.9) (end 2.3 -1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start 2.3 -1.9) (end 2.5 -1.7) (layer F.SilkS) (width 0.15))
+ (fp_line (start 2.5 -1.7) (end 2.5 0.7) (layer F.SilkS) (width 0.15))
+ (fp_line (start 2.5 0.7) (end 1.3 1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.3 1.9) (end -2.5 0.7) (layer F.SilkS) (width 0.15))
+ (fp_line (start -2.5 0.7) (end -2.5 -1.7) (layer F.SilkS) (width 0.15))
+ (pad 1 thru_hole circle (at 1.27 -0.635 180) (size 1.4 1.4) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
+ (net 3 "Net-(D1-Pad2)"))
+ (pad 2 thru_hole circle (at 0 0.635 180) (size 1.4 1.4) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
+ (net 6 "Net-(Q1-Pad2)"))
+ (pad 3 thru_hole circle (at -1.27 -0.635 180) (size 1.4 1.4) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND))
+ (model to-xxx-packages/to92.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Discret:R4 (layer F.Cu) (tedit 531143E8) (tstamp 5311442E)
+ (at 153.67 109.22)
+ (descr "Resitance 4 pas")
+ (tags R)
+ (path /531109F0)
+ (autoplace_cost180 10)
+ (fp_text reference R1 (at 0 0) (layer F.SilkS)
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_text value 560 (at 0 0) (layer F.SilkS) hide
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_line (start -5.08 0) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 0) (end -4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -1.016) (end 4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 -1.016) (end 4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 1.016) (end -4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 1.016) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -0.508) (end -3.556 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 5.08 0) (end 4.064 0) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole circle (at -5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 2 "Net-(D1-Pad1)"))
+ (pad 2 thru_hole circle (at 5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 5 "Net-(K1-Pad3)"))
+ (model discret/resistor.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.4 0.4 0.4))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Discret:R4 (layer F.Cu) (tedit 531143E8) (tstamp 5311443C)
+ (at 153.67 104.14)
+ (descr "Resitance 4 pas")
+ (tags R)
+ (path /53110A02)
+ (autoplace_cost180 10)
+ (fp_text reference R2 (at 0 0) (layer F.SilkS)
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_text value 2.2k (at 0 0) (layer F.SilkS) hide
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_line (start -5.08 0) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 0) (end -4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -1.016) (end 4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 -1.016) (end 4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 1.016) (end -4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 1.016) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -0.508) (end -3.556 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 5.08 0) (end 4.064 0) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole circle (at -5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 6 "Net-(Q1-Pad2)"))
+ (pad 2 thru_hole circle (at 5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 4 "Net-(K1-Pad2)"))
+ (model discret/resistor.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.4 0.4 0.4))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (gr_text smida.it (at 155.575 112.395) (layer B.Mask)
+ (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
+ )
+ (gr_text smida.it (at 155.575 112.395) (layer F.Mask)
+ (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
+ )
+ (gr_text smida.it (at 155.575 112.395) (layer B.Cu)
+ (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
+ )
+ (gr_line (start 139.7 99.06) (end 166.37 99.06) (angle 90) (layer Edge.Cuts) (width 0.1))
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+
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+
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+ (min_thickness 0.254)
+ (fill (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
+ (polygon
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+ (xy 140.385 113.615) (xy 140.385 99.745) (xy 165.685 99.745) (xy 165.685 113.615)
+ )
+ )
+ )
+)
diff --git a/ledspy-cache.lib b/ledspy-cache.lib
new file mode 100644
index 0000000..7bec6ec
--- /dev/null
+++ b/ledspy-cache.lib
@@ -0,0 +1,115 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# BC547
+#
+DEF BC547 Q 0 0 Y Y 1 F N
+F0 "Q" 0 -149 40 H V R CNN
+F1 "BC547" 0 150 40 H V R CNN
+F2 "TO92" -100 102 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC546 BC548 BC549 BC550
+$FPLIST
+ TO92*
+$ENDFPLIST
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 40 40 1 1 P
+X B 2 -200 0 225 R 40 40 1 1 I
+X E 3 100 -200 100 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_3
+#
+DEF CONN_3 K 0 40 Y N 1 F N
+F0 "K" -50 0 50 V V C CNN
+F1 "CONN_3" 50 0 40 V V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -100 150 100 -150 0 1 0 N
+X P1 1 -350 100 250 R 60 60 1 1 P I
+X PM 2 -350 0 250 R 60 60 1 1 P I
+X P3 3 -350 -100 250 R 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# LED
+#
+DEF LED D 0 40 Y N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "LED" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ LED-3MM
+ LED-5MM
+ LED-10MM
+ LED-0603
+ LED-0805
+ LED-1206
+ LEDV
+$ENDFPLIST
+DRAW
+P 2 0 1 0 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+P 3 0 1 0 65 -40 110 -80 105 -55 N
+P 3 0 1 0 80 -25 125 -65 120 -40 N
+X A 1 -200 0 150 R 40 40 1 1 P
+X K 2 200 0 150 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 30 H I C CNN
+F1 "PWR_FLAG" 0 180 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 40 V V C CNN
+F1 "R" 7 1 40 V V C CNN
+F2 "" -70 0 30 V V C CNN
+F3 "" 0 0 30 H V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+ SM1206
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/ledspy.bak b/ledspy.bak
new file mode 100644
index 0000000..41bf6a4
--- /dev/null
+++ b/ledspy.bak
@@ -0,0 +1,163 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+EELAYER 24 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L R R1
+U 1 1 531109F0
+P 5900 3350
+F 0 "R1" V 5980 3350 40 0000 C CNN
+F 1 "560" V 5907 3351 40 0000 C CNN
+F 2 "" V 5830 3350 30 0000 C CNN
+F 3 "" H 5900 3350 30 0000 C CNN
+ 1 5900 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L R R2
+U 1 1 53110A02
+P 5900 3750
+F 0 "R2" V 5980 3750 40 0000 C CNN
+F 1 "2.2k" V 5907 3751 40 0000 C CNN
+F 2 "" V 5830 3750 30 0000 C CNN
+F 3 "" H 5900 3750 30 0000 C CNN
+ 1 5900 3750
+ 0 1 1 0
+$EndComp
+$Comp
+L LED D1
+U 1 1 53110A0F
+P 6500 3350
+F 0 "D1" H 6500 3450 50 0000 C CNN
+F 1 "LED" H 6500 3250 50 0000 C CNN
+F 2 "" H 6500 3350 60 0000 C CNN
+F 3 "" H 6500 3350 60 0000 C CNN
+ 1 6500 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L BC547 Q1
+U 1 1 53110A23
+P 6900 3750
+F 0 "Q1" H 6900 3601 40 0000 R CNN
+F 1 "BC547" H 6900 3900 40 0000 R CNN
+F 2 "TO92" H 6800 3852 29 0000 C CNN
+F 3 "" H 6900 3750 60 0000 C CNN
+ 1 6900 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L CONN_3 K1
+U 1 1 53110A37
+P 5050 3750
+F 0 "K1" V 5000 3750 50 0000 C CNN
+F 1 "CONN_3" V 5100 3750 40 0000 C CNN
+F 2 "" H 5050 3750 60 0000 C CNN
+F 3 "" H 5050 3750 60 0000 C CNN
+ 1 5050 3750
+ -1 0 0 1
+$EndComp
+$Comp
+L PWR_FLAG #FLG?
+U 1 1 53110A5F
+P 7950 3050
+F 0 "#FLG?" H 7950 3145 30 0001 C CNN
+F 1 "PWR_FLAG" H 7950 3230 30 0000 C CNN
+F 2 "" H 7950 3050 60 0000 C CNN
+F 3 "" H 7950 3050 60 0000 C CNN
+ 1 7950 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 53110A71
+P 7950 3300
+F 0 "#PWR?" H 7950 3300 30 0001 C CNN
+F 1 "GND" H 7950 3230 30 0001 C CNN
+F 2 "" H 7950 3300 60 0000 C CNN
+F 3 "" H 7950 3300 60 0000 C CNN
+ 1 7950 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5400 3750 5650 3750
+Wire Wire Line
+ 7950 3050 7950 3300
+Wire Wire Line
+ 5400 3650 5550 3650
+Wire Wire Line
+ 5550 3650 5550 3350
+Wire Wire Line
+ 5550 3350 5650 3350
+Wire Wire Line
+ 6150 3750 6700 3750
+Wire Wire Line
+ 6150 3350 6300 3350
+Wire Wire Line
+ 6700 3350 7000 3350
+Wire Wire Line
+ 7000 3350 7000 3550
+Wire Wire Line
+ 5400 3850 5550 3850
+Wire Wire Line
+ 5550 3850 5550 4100
+Wire Wire Line
+ 5550 4100 7000 4100
+Wire Wire Line
+ 7000 4100 7000 3950
+$Comp
+L GND #PWR?
+U 1 1 5311179A
+P 6300 4250
+F 0 "#PWR?" H 6300 4250 30 0001 C CNN
+F 1 "GND" H 6300 4180 30 0001 C CNN
+F 2 "" H 6300 4250 60 0000 C CNN
+F 3 "" H 6300 4250 60 0000 C CNN
+ 1 6300 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6300 4250 6300 4100
+Connection ~ 6300 4100
+$EndSCHEMATC
diff --git a/ledspy.cmp b/ledspy.cmp
new file mode 100644
index 0000000..dd7f234
--- /dev/null
+++ b/ledspy.cmp
@@ -0,0 +1,38 @@
+Cmp-Mod V01 Created by CvPcb (2014-02-28 BZR 4729)-product date = Sat 01 Mar 2014 03:20:12 AM CET
+
+BeginCmp
+TimeStamp = /53110A0F;
+Reference = D1;
+ValeurCmp = LED;
+IdModule = LEDs:LED-5MM;
+EndCmp
+
+BeginCmp
+TimeStamp = /53110A37;
+Reference = K1;
+ValeurCmp = CONN_3;
+IdModule = Pin_Headers:Pin_Header_Straight_1x03;
+EndCmp
+
+BeginCmp
+TimeStamp = /53110A23;
+Reference = Q1;
+ValeurCmp = BC547;
+IdModule = Discret:TO92PN;
+EndCmp
+
+BeginCmp
+TimeStamp = /531109F0;
+Reference = R1;
+ValeurCmp = 560;
+IdModule = Discret:R4;
+EndCmp
+
+BeginCmp
+TimeStamp = /53110A02;
+Reference = R2;
+ValeurCmp = 2.2k;
+IdModule = Discret:R4;
+EndCmp
+
+EndListe
diff --git a/ledspy.kicad_pcb b/ledspy.kicad_pcb
new file mode 100644
index 0000000..87e157d
--- /dev/null
+++ b/ledspy.kicad_pcb
@@ -0,0 +1,362 @@
+(kicad_pcb (version 3) (host pcbnew "(2014-02-28 BZR 4729)-product")
+
+ (general
+ (links 6)
+ (no_connects 0)
+ (area 138.657693 99.009999 167.904886 114.350001)
+ (thickness 1.6)
+ (drawings 7)
+ (tracks 17)
+ (zones 0)
+ (modules 5)
+ (nets 7)
+ )
+
+ (page A4)
+ (layers
+ (15 F.Cu signal hide)
+ (0 B.Cu signal)
+ (16 B.Adhes user hide)
+ (17 F.Adhes user hide)
+ (18 B.Paste user)
+ (19 F.Paste user hide)
+ (20 B.SilkS user hide)
+ (21 F.SilkS user)
+ (22 B.Mask user)
+ (23 F.Mask user)
+ (24 Dwgs.User user hide)
+ (25 Cmts.User user hide)
+ (26 Eco1.User user hide)
+ (27 Eco2.User user hide)
+ (28 Edge.Cuts user hide)
+ )
+
+ (setup
+ (last_trace_width 0.254)
+ (user_trace_width 0.5)
+ (trace_clearance 0.254)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.254)
+ (segment_width 0.2)
+ (edge_width 0.1)
+ (via_size 0.889)
+ (via_drill 0.635)
+ (via_min_size 0.889)
+ (via_min_drill 0.508)
+ (uvia_size 0.508)
+ (uvia_drill 0.127)
+ (uvias_allowed no)
+ (uvia_min_size 0.508)
+ (uvia_min_drill 0.127)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1.5 1.5)
+ (pad_drill 0.6)
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 0 0)
+ (visible_elements FFFFFB1F)
+ (pcbplotparams
+ (layerselection 14680065)
+ (usegerberextensions false)
+ (excludeedgelayer true)
+ (linewidth 0.150000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (hpglpenoverlay 2)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotothertext true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 5)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 GND)
+ (net 2 "Net-(D1-Pad1)")
+ (net 3 "Net-(D1-Pad2)")
+ (net 4 "Net-(K1-Pad2)")
+ (net 5 "Net-(K1-Pad3)")
+ (net 6 "Net-(Q1-Pad2)")
+
+ (net_class Default "This is the default net class."
+ (clearance 0.254)
+ (trace_width 0.254)
+ (via_dia 0.889)
+ (via_drill 0.635)
+ (uvia_dia 0.508)
+ (uvia_drill 0.127)
+ (add_net "")
+ (add_net GND)
+ (add_net "Net-(D1-Pad1)")
+ (add_net "Net-(D1-Pad2)")
+ (add_net "Net-(K1-Pad2)")
+ (add_net "Net-(K1-Pad3)")
+ (add_net "Net-(Q1-Pad2)")
+ )
+
+ (module LEDs:LED-5MM (layer F.Cu) (tedit 531143E7) (tstamp 53114403)
+ (at 143.51 109.22 90)
+ (descr "LED 5mm - Lead pitch 100mil (2,54mm)")
+ (tags "LED led 5mm 5MM 100mil 2,54mm")
+ (path /53110A0F)
+ (fp_text reference D1 (at 0 -3.81 90) (layer F.SilkS)
+ (effects (font (size 0.762 0.762) (thickness 0.0889)))
+ )
+ (fp_text value LED (at 0 3.81 90) (layer F.SilkS)
+ (effects (font (size 0.762 0.762) (thickness 0.0889)))
+ )
+ (fp_line (start 2.8448 1.905) (end 2.8448 -1.905) (layer F.SilkS) (width 0.2032))
+ (fp_circle (center 0.254 0) (end -1.016 1.27) (layer F.SilkS) (width 0.0762))
+ (fp_arc (start 0.254 0) (end 2.794 1.905) (angle 286.2) (layer F.SilkS) (width 0.254))
+ (fp_arc (start 0.254 0) (end -0.889 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end 1.397 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end -1.397 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end 1.905 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end -1.905 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (fp_arc (start 0.254 0) (end 2.413 0) (angle 90) (layer F.SilkS) (width 0.1524))
+ (pad 1 thru_hole circle (at -1.27 0 90) (size 1.6764 1.6764) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 2 "Net-(D1-Pad1)"))
+ (pad 2 thru_hole circle (at 1.27 0 90) (size 1.6764 1.6764) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 3 "Net-(D1-Pad2)"))
+ (model discret/leds/led5_vertical_verde.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Pin_Headers:Pin_Header_Straight_1x03 (layer F.Cu) (tedit 531143E6) (tstamp 53114411)
+ (at 163.83 106.68 270)
+ (descr "1 pin")
+ (tags "CONN DEV")
+ (path /53110A37)
+ (fp_text reference K1 (at 0 -2.286 270) (layer F.SilkS)
+ (effects (font (size 1.27 1.27) (thickness 0.2032)))
+ )
+ (fp_text value CONN_3 (at 0 0 270) (layer F.SilkS) hide
+ (effects (font (size 1.27 1.27) (thickness 0.2032)))
+ )
+ (fp_line (start -1.27 1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start 3.81 1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start 3.81 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 -1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.254))
+ (pad 1 thru_hole rect (at -2.54 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND))
+ (pad 2 thru_hole oval (at 0 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 4 "Net-(K1-Pad2)"))
+ (pad 3 thru_hole oval (at 2.54 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 5 "Net-(K1-Pad3)"))
+ (model Pin_Headers/Pin_Header_Straight_1x03.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Discret:TO92PN (layer F.Cu) (tedit 531143E8) (tstamp 53114420)
+ (at 143.51 102.87 180)
+ (path /53110A23)
+ (fp_text reference Q1 (at -0.1 -1.1 180) (layer F.SilkS)
+ (effects (font (size 0.7 0.7) (thickness 0.15)))
+ )
+ (fp_text value BC547 (at 0 0.6 180) (layer F.SilkS)
+ (effects (font (size 0.6 0.6) (thickness 0.15)))
+ )
+ (fp_line (start 1.3 1.9) (end -1.3 1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start -2.5 -1.7) (end -2.3 -1.9) (layer F.SilkS) (width 0.15))
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diff --git a/ledspy.kicad_pcb-bak b/ledspy.kicad_pcb-bak
new file mode 100644
index 0000000..8354f03
--- /dev/null
+++ b/ledspy.kicad_pcb-bak
@@ -0,0 +1,356 @@
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+ (thickness 1.6)
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+ (page A4)
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+ (model discret/leds/led5_vertical_verde.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Pin_Headers:Pin_Header_Straight_1x03 (layer F.Cu) (tedit 531143E6) (tstamp 53114411)
+ (at 163.83 106.68 270)
+ (descr "1 pin")
+ (tags "CONN DEV")
+ (path /53110A37)
+ (fp_text reference K1 (at 0 -2.286 270) (layer F.SilkS)
+ (effects (font (size 1.27 1.27) (thickness 0.2032)))
+ )
+ (fp_text value CONN_3 (at 0 0 270) (layer F.SilkS) hide
+ (effects (font (size 1.27 1.27) (thickness 0.2032)))
+ )
+ (fp_line (start -1.27 1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start 3.81 1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start 3.81 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 -1.27) (end -1.27 -1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 -1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.254))
+ (fp_line (start -3.81 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.254))
+ (pad 1 thru_hole rect (at -2.54 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND))
+ (pad 2 thru_hole oval (at 0 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 4 "Net-(K1-Pad2)"))
+ (pad 3 thru_hole oval (at 2.54 0 270) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 5 "Net-(K1-Pad3)"))
+ (model Pin_Headers/Pin_Header_Straight_1x03.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Discret:TO92PN (layer F.Cu) (tedit 531143E8) (tstamp 53114420)
+ (at 143.51 102.87 180)
+ (path /53110A23)
+ (fp_text reference Q1 (at -0.1 -1.1 180) (layer F.SilkS)
+ (effects (font (size 0.7 0.7) (thickness 0.15)))
+ )
+ (fp_text value BC547 (at 0 0.6 180) (layer F.SilkS)
+ (effects (font (size 0.6 0.6) (thickness 0.15)))
+ )
+ (fp_line (start 1.3 1.9) (end -1.3 1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start -2.5 -1.7) (end -2.3 -1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start -2.3 -1.9) (end 2.3 -1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start 2.3 -1.9) (end 2.5 -1.7) (layer F.SilkS) (width 0.15))
+ (fp_line (start 2.5 -1.7) (end 2.5 0.7) (layer F.SilkS) (width 0.15))
+ (fp_line (start 2.5 0.7) (end 1.3 1.9) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.3 1.9) (end -2.5 0.7) (layer F.SilkS) (width 0.15))
+ (fp_line (start -2.5 0.7) (end -2.5 -1.7) (layer F.SilkS) (width 0.15))
+ (pad 1 thru_hole circle (at 1.27 -0.635 180) (size 1.4 1.4) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
+ (net 3 "Net-(D1-Pad2)"))
+ (pad 2 thru_hole circle (at 0 0.635 180) (size 1.4 1.4) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
+ (net 6 "Net-(Q1-Pad2)"))
+ (pad 3 thru_hole circle (at -1.27 -0.635 180) (size 1.4 1.4) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND))
+ (model to-xxx-packages/to92.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Discret:R4 (layer F.Cu) (tedit 531143E8) (tstamp 5311442E)
+ (at 153.67 109.22)
+ (descr "Resitance 4 pas")
+ (tags R)
+ (path /531109F0)
+ (autoplace_cost180 10)
+ (fp_text reference R1 (at 0 0) (layer F.SilkS)
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_text value 560 (at 0 0) (layer F.SilkS) hide
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_line (start -5.08 0) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 0) (end -4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -1.016) (end 4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 -1.016) (end 4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 1.016) (end -4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 1.016) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -0.508) (end -3.556 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 5.08 0) (end 4.064 0) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole circle (at -5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 2 "Net-(D1-Pad1)"))
+ (pad 2 thru_hole circle (at 5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 5 "Net-(K1-Pad3)"))
+ (model discret/resistor.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.4 0.4 0.4))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module Discret:R4 (layer F.Cu) (tedit 531143E8) (tstamp 5311443C)
+ (at 153.67 104.14)
+ (descr "Resitance 4 pas")
+ (tags R)
+ (path /53110A02)
+ (autoplace_cost180 10)
+ (fp_text reference R2 (at 0 0) (layer F.SilkS)
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_text value 2.2k (at 0 0) (layer F.SilkS) hide
+ (effects (font (size 1.397 1.27) (thickness 0.2032)))
+ )
+ (fp_line (start -5.08 0) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 0) (end -4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -1.016) (end 4.064 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 -1.016) (end 4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 4.064 1.016) (end -4.064 1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 1.016) (end -4.064 0) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -4.064 -0.508) (end -3.556 -1.016) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 5.08 0) (end 4.064 0) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole circle (at -5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 6 "Net-(Q1-Pad2)"))
+ (pad 2 thru_hole circle (at 5.08 0) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
+ (net 4 "Net-(K1-Pad2)"))
+ (model discret/resistor.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.4 0.4 0.4))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (gr_text smida.it (at 155.575 112.395) (layer B.Cu)
+ (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
+ )
+ (gr_line (start 139.7 99.06) (end 166.37 99.06) (angle 90) (layer Edge.Cuts) (width 0.1))
+ (gr_line (start 139.7 114.3) (end 139.7 99.06) (angle 90) (layer Edge.Cuts) (width 0.1))
+ (gr_line (start 166.37 114.3) (end 139.7 114.3) (angle 90) (layer Edge.Cuts) (width 0.1))
+ (gr_line (start 166.37 99.06) (end 166.37 114.3) (angle 90) (layer Edge.Cuts) (width 0.1))
+
+ (segment (start 144.78 103.505) (end 144.78 105.41) (width 0.5) (layer B.Cu) (net 1))
+ (segment (start 161.29 101.6) (end 163.83 104.14) (width 0.5) (layer B.Cu) (net 1) (tstamp 531146C6))
+ (segment (start 156.21 101.6) (end 161.29 101.6) (width 0.5) (layer B.Cu) (net 1) (tstamp 531146C3))
+ (segment (start 151.13 106.68) (end 156.21 101.6) (width 0.5) (layer B.Cu) (net 1) (tstamp 531146C0))
+ (segment (start 146.05 106.68) (end 151.13 106.68) (width 0.5) (layer B.Cu) (net 1) (tstamp 531146BC))
+ (segment (start 144.78 105.41) (end 146.05 106.68) (width 0.5) (layer B.Cu) (net 1) (tstamp 531146BB))
+ (segment (start 143.51 110.49) (end 147.32 110.49) (width 0.5) (layer B.Cu) (net 2))
+ (segment (start 147.32 110.49) (end 148.59 109.22) (width 0.5) (layer B.Cu) (net 2) (tstamp 53114639))
+ (segment (start 142.24 103.505) (end 142.24 106.68) (width 0.5) (layer B.Cu) (net 3))
+ (segment (start 142.24 106.68) (end 143.51 107.95) (width 0.5) (layer B.Cu) (net 3) (tstamp 53114636))
+ (segment (start 158.75 104.14) (end 158.75 105.41) (width 0.5) (layer B.Cu) (net 4))
+ (segment (start 160.02 106.68) (end 163.83 106.68) (width 0.5) (layer B.Cu) (net 4) (tstamp 5311462F))
+ (segment (start 158.75 105.41) (end 160.02 106.68) (width 0.5) (layer B.Cu) (net 4) (tstamp 5311462E))
+ (segment (start 158.75 109.22) (end 163.83 109.22) (width 0.5) (layer B.Cu) (net 5))
+ (segment (start 148.59 104.14) (end 148.59 102.87) (width 0.5) (layer B.Cu) (net 6))
+ (segment (start 147.955 102.235) (end 143.51 102.235) (width 0.5) (layer B.Cu) (net 6) (tstamp 53114633))
+ (segment (start 148.59 102.87) (end 147.955 102.235) (width 0.5) (layer B.Cu) (net 6) (tstamp 53114632))
+
+ (zone (net 1) (net_name GND) (layer B.Cu) (tstamp 53114A57) (hatch edge 0.508)
+ (connect_pads (clearance 0.508))
+ (min_thickness 0.254)
+ (fill (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
+ (polygon
+ (pts
+ (xy 166.37 114.3) (xy 139.7 114.3) (xy 139.7 99.06) (xy 166.37 99.06)
+ )
+ )
+ (filled_polygon
+ (pts
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+)
diff --git a/ledspy.net b/ledspy.net
new file mode 100644
index 0000000..de1abfd
--- /dev/null
+++ b/ledspy.net
@@ -0,0 +1,115 @@
+(export (version D)
+ (design
+ (source /workspace/workspace/schematics/ledspy/ledspy.sch)
+ (date "Sat 01 Mar 2014 02:18:16 AM CET")
+ (tool "eeschema (2014-02-28 BZR 4729)-product"))
+ (components
+ (comp (ref R1)
+ (value 560)
+ (libsource (lib device) (part R))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 531109F0))
+ (comp (ref R2)
+ (value 2.2k)
+ (libsource (lib device) (part R))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 53110A02))
+ (comp (ref D1)
+ (value LED)
+ (libsource (lib device) (part LED))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 53110A0F))
+ (comp (ref Q1)
+ (value BC547)
+ (footprint TO92)
+ (libsource (lib transistors) (part BC547))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 53110A23))
+ (comp (ref K1)
+ (value CONN_3)
+ (libsource (lib conn) (part CONN_3))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 53110A37)))
+ (libparts
+ (libpart (lib device) (part LED)
+ (footprints
+ (fp LED-3MM)
+ (fp LED-5MM)
+ (fp LED-10MM)
+ (fp LED-0603)
+ (fp LED-0805)
+ (fp LED-1206)
+ (fp LEDV))
+ (fields
+ (field (name Reference) D)
+ (field (name Value) LED))
+ (pins
+ (pin (num 1) (name A) (type passive))
+ (pin (num 2) (name K) (type passive))))
+ (libpart (lib device) (part R)
+ (description Resistance)
+ (footprints
+ (fp R?)
+ (fp SM0603)
+ (fp SM0805)
+ (fp R?-*)
+ (fp SM1206))
+ (fields
+ (field (name Reference) R)
+ (field (name Value) R))
+ (pins
+ (pin (num 1) (name ~) (type passive))
+ (pin (num 2) (name ~) (type passive))))
+ (libpart (lib transistors) (part BC547)
+ (aliases
+ (alias BC546)
+ (alias BC548)
+ (alias BC549)
+ (alias BC550))
+ (description "BC547, 45V Vce, 0.1A Ic, NPN, Small Signal Transistor,TO-92")
+ (docs http://www.fairchildsemi.com/ds/BC/BC547.pdf)
+ (footprints
+ (fp TO92*))
+ (fields
+ (field (name Reference) Q)
+ (field (name Value) BC547)
+ (field (name Footprint) TO92))
+ (pins
+ (pin (num 1) (name C) (type passive))
+ (pin (num 2) (name B) (type input))
+ (pin (num 3) (name E) (type passive))))
+ (libpart (lib conn) (part CONN_3)
+ (description "Symbole general de connecteur")
+ (fields
+ (field (name Reference) K)
+ (field (name Value) CONN_3))
+ (pins
+ (pin (num 1) (name P1) (type passive))
+ (pin (num 2) (name PM) (type passive))
+ (pin (num 3) (name P3) (type passive)))))
+ (libraries
+ (library (logical device)
+ (uri /usr/local/share/kicad/library/device.lib))
+ (library (logical transistors)
+ (uri /usr/local/share/kicad/library/transistors.lib))
+ (library (logical conn)
+ (uri /usr/local/share/kicad/library/conn.lib)))
+ (nets
+ (net (code 1) (name GND)
+ (node (ref K1) (pin 1))
+ (node (ref Q1) (pin 3)))
+ (net (code 2) (name "Net-(D1-Pad2)")
+ (node (ref D1) (pin 2))
+ (node (ref Q1) (pin 1)))
+ (net (code 3) (name "Net-(D1-Pad1)")
+ (node (ref D1) (pin 1))
+ (node (ref R1) (pin 1)))
+ (net (code 4) (name "Net-(Q1-Pad2)")
+ (node (ref Q1) (pin 2))
+ (node (ref R2) (pin 1)))
+ (net (code 5) (name "Net-(K1-Pad3)")
+ (node (ref K1) (pin 3))
+ (node (ref R1) (pin 2)))
+ (net (code 6) (name "Net-(K1-Pad2)")
+ (node (ref K1) (pin 2))
+ (node (ref R2) (pin 2))))) \ No newline at end of file
diff --git a/ledspy.pro b/ledspy.pro
new file mode 100644
index 0000000..d91a1fe
--- /dev/null
+++ b/ledspy.pro
@@ -0,0 +1,86 @@
+update=Fri 28 Feb 2014 11:12:18 PM CET
+version=1
+last_client=kicad
+[cvpcb]
+version=1
+NetIExt=net
+[cvpcb/libraries]
+EquName1=devcms
+[eeschema]
+version=1
+LibDir=
+NetFmtName=
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[pcbnew/libraries]
+LibDir=
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=smd_capacitors
+LibName7=smd_resistors
+LibName8=smd_crystal&oscillator
+LibName9=smd_dil
+LibName10=smd_transistors
+LibName11=libcms
+LibName12=display
+LibName13=led
+LibName14=dip_sockets
+LibName15=pga_sockets
+LibName16=valves
+[general]
+version=1
diff --git a/ledspy.sch b/ledspy.sch
new file mode 100644
index 0000000..41db743
--- /dev/null
+++ b/ledspy.sch
@@ -0,0 +1,164 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:ledspy-cache
+EELAYER 24 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title "GPIO Led Spy"
+Date "02 Mar 2014"
+Rev "1.0"
+Comp "www.smida.it"
+Comment1 "Andi Shyti"
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+$EndComp
+$Comp
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+$Comp
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+ 1 5050 3750
+ -1 0 0 1
+$EndComp
+$Comp
+L PWR_FLAG #FLG?
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+F 2 "" H 7950 3050 60 0000 C CNN
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+ 1 7950 3050
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+$EndComp
+$Comp
+L GND #PWR?
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+F 2 "" H 7950 3300 60 0000 C CNN
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+Wire Wire Line
+ 5400 3750 5650 3750
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+Wire Wire Line
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+$EndSCHEMATC
diff --git a/output/ledspy-B_Cu.pdf b/output/ledspy-B_Cu.pdf
new file mode 100644
index 0000000..742d378
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