diff options
| author | Mattias Nilsson <mattias.i.nilsson@stericsson.com> | 2011-11-23 19:33:57 +0100 |
|---|---|---|
| committer | Philippe Langlais <philippe.langlais@stericsson.com> | 2012-05-22 10:59:22 +0200 |
| commit | 3c6b47432f8a1d916f421e9cc38da05d415be471 (patch) | |
| tree | af784a4c929274880c4a0cac937259cd75f148e7 | |
| parent | 859a4d909c641e43837c29a0fe383801c08f57a1 (diff) | |
arm: ux500: configure the sgaclk according to firmware version
This patch sets the parent of sgaclk to soc0_pll for the firmwares
for which this is the case.
ST Ericsson ID: 369379
ST Ericsson FOSS-OUT ID: trivial
Change-Id: I4f9184d2288c698b856ed6858e61f9ee3ebbf9bc
Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/40034
Reviewed-by: QABUILD
Reviewed-by: Bengt JONSSON <bengt.g.jonsson@stericsson.com>
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
| -rw-r--r-- | arch/arm/mach-ux500/clock-db8500.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/clock-db8500.c b/arch/arm/mach-ux500/clock-db8500.c index 7bfe4e50044..cdc7a99451c 100644 --- a/arch/arm/mach-ux500/clock-db8500.c +++ b/arch/arm/mach-ux500/clock-db8500.c @@ -1108,8 +1108,16 @@ static int __init init_clock_states(void) } late_initcall(init_clock_states); +static void __init configure_c2_clocks(void) +{ + sgaclk.parent = &soc0_pll; + sgaclk.mutex = &soc0_pll_mutex; +} + int __init db8500_clk_init(void) { + struct prcmu_fw_version *fw_version; + /* * Disable pwl's and slimbus' bus and kernel clocks without touching * any parents. Because for slimbus, the prcmu fw has not correctly @@ -1124,11 +1132,20 @@ int __init db8500_clk_init(void) writel(1 << 3, __io_address(U8500_CLKRST2_BASE) + PRCC_PCKDIS); writel(1 << 1, __io_address(U8500_CLKRST2_BASE) + PRCC_KCKDIS); + fw_version = prcmu_get_fw_version(); + if (fw_version != NULL) + switch (fw_version->project) { + case PRCMU_FW_PROJECT_U8500_C2: + case PRCMU_FW_PROJECT_U9500_C2: + configure_c2_clocks(); + break; + default: + break; + } clkdev_add_table(u8500_v2_sysclks, ARRAY_SIZE(u8500_v2_sysclks)); clkdev_add_table(u8500_clocks, ARRAY_SIZE(u8500_clocks)); - return 0; } |