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authorJonas Aaberg <jonas.aberg@stericsson.com>2011-12-15 13:32:10 +0100
committerPhilippe Langlais <philippe.langlais@stericsson.com>2012-05-22 10:59:24 +0200
commitefd06585cbb5931476dd7a5a6d70d6c1656e7e97 (patch)
treec8d1bc4a61b9def9519cfab746b27f1a699a4d76
parent63612fdc53c5daa2a91f716604032ce404bc9e25 (diff)
ARM: ux500: prcmu-qos: Set correct initial values
ST-Ericsson Linux next: - ST-Ericsson ID: 370799 ST-Ericsson FOSS-OUT ID: Trivial Change-Id: I9246260bd30bfa39f30aca9238259647d37fc617 Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/42698 Reviewed-by: Rabin VINCENT <rabin.vincent@stericsson.com> Reviewed-by: QABUILD
-rw-r--r--arch/arm/mach-ux500/pm/prcmu-qos-power.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/mach-ux500/pm/prcmu-qos-power.c b/arch/arm/mach-ux500/pm/prcmu-qos-power.c
index 71c52bc76b8..a600a57dc13 100644
--- a/arch/arm/mach-ux500/pm/prcmu-qos-power.c
+++ b/arch/arm/mach-ux500/pm/prcmu-qos-power.c
@@ -74,7 +74,7 @@ static struct prcmu_qos_object ape_opp_qos = {
/* Target value in % APE OPP */
.default_value = 50,
.force_value = 0,
- .target_value = ATOMIC_INIT(0),
+ .target_value = ATOMIC_INIT(50),
.comparitor = max_compare
};
@@ -87,7 +87,7 @@ static struct prcmu_qos_object ddr_opp_qos = {
/* Target value in % DDR OPP */
.default_value = 25,
.force_value = 0,
- .target_value = ATOMIC_INIT(0),
+ .target_value = ATOMIC_INIT(25),
.comparitor = max_compare
};
@@ -103,7 +103,7 @@ static struct prcmu_qos_object arm_opp_qos = {
/* Target value in % ARM OPP, note can be 125% */
.default_value = 25,
.force_value = 0,
- .target_value = ATOMIC_INIT(0),
+ .target_value = ATOMIC_INIT(25),
.comparitor = max_compare
};
@@ -233,6 +233,7 @@ static void update_target(int target)
));
}
}
+
spin_unlock_irqrestore(&prcmu_qos_lock, flags);
if (!update)
@@ -682,8 +683,10 @@ static int __init prcmu_qos_power_init(void)
int ret;
/* 25% DDR OPP is not supported on u5500 */
- if (cpu_is_u5500())
+ if (cpu_is_u5500()) {
ddr_opp_qos.default_value = 50;
+ atomic_set(&ddr_opp_qos.target_value, 50);
+ }
ret = register_prcmu_qos_misc(&ape_opp_qos, &prcmu_qos_ape_power_fops);
if (ret < 0) {