diff options
| author | ramesh.chandrasekaran <ramesh.chandrasekaran@stericsson.com> | 2012-07-04 15:55:20 +0530 |
|---|---|---|
| committer | Rajanikanth H.V <rajanikanth.hv@stericsson.com> | 2012-12-14 17:07:18 +0530 |
| commit | e16d9d8a926ede00fd0cca7f178692cf50ec3cc5 (patch) | |
| tree | 0117132cc536500097a7268b3f364e0ed6ec5793 | |
| parent | 876e3661b1dce628941685a0166b793337edc8a1 (diff) | |
mach-ux500: clk: Enable lcd clock for snowball DPI display
Signed-off-by: ramesh.chandrasekaran <ramesh.chandrasekaran@stericsson.com>
| -rw-r--r-- | drivers/mfd/db8500-prcmu.c | 12 | ||||
| -rw-r--r-- | drivers/mfd/dbx500-prcmu-regs.h | 2 |
2 files changed, 10 insertions, 4 deletions
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 7c26c41a7ef..35042849312 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -540,9 +540,13 @@ static struct dsiescclk dsiescclk[3] = { /* PLLDIV=12, PLLSW=4 (PLLDDR) */ #define PRCMU_DSI_CLOCK_SETTING 0x0000008C -/* DPI 50000000 Hz */ -#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ - (16 << PRCMU_CLK_PLL_DIV_SHIFT)) +#define PRCMU_LCDCLKEN (1 << 17) +/* DPI 66000000 Hz */ +/* modified as specified in the STE application note about LCD */ +#define PRCMU_CLK_EN (1<<8) +#define PRCMU_DPI_CLOCK_SETTING (PRCMU_CLK_EN | (4 << PRCMU_CLK_PLL_SW_SHIFT) | \ + (12 << PRCMU_CLK_PLL_DIV_SHIFT)) + #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 /* D=101, N=1, R=4, SELDIV2=0 */ @@ -609,6 +613,8 @@ int db8500_prcmu_set_display_clocks(void) cpu_relax(); writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); + /* Enable LCD Clock */ + writel(PRCMU_LCDCLKEN, PRCM_YYCLKEN0_MGT_SET); writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index 0835a57dac1..70840a8ba0c 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h @@ -154,9 +154,9 @@ #define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) #define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) +#define PRCM_YYCLKEN0_MGT_SET (_PRCMU_BASE + 0x510) #define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) #define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) -#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) #define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) #define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) |