diff options
| author | Philippe Langlais <philippe.langlais@linaro.org> | 2012-01-11 10:37:58 +0100 |
|---|---|---|
| committer | Philippe Langlais <philippe.langlais@stericsson.com> | 2012-05-22 11:03:24 +0200 |
| commit | 22e8d8ce6d22656af59b4324a99bd6735de7f613 (patch) | |
| tree | 05cffa306b5becb3cf2e7229a503f0b18d12af07 | |
| parent | 5dce3732e65887c11f439e954cbf3afcd9356bbf (diff) | |
mach-ux500: stm: u8500: API for PRCMU_GPIOCR register
The PRCMU_GPIOCR register modification within
STM driver is implemented via corresponding
API functions.
ST-Ericsson ID: 349677
ST-Ericsson Linux next: N/A
ST-Ericsson FOSS-OUT ID: Trivial
Signed-off-by: Jurijs Soloveckis <jurijs.soloveckis@stericsson.com>
| -rw-r--r-- | arch/arm/mach-ux500/board-mop500-stm.c | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/arch/arm/mach-ux500/board-mop500-stm.c b/arch/arm/mach-ux500/board-mop500-stm.c index 7d8148c5878..20d3f9a546b 100644 --- a/arch/arm/mach-ux500/board-mop500-stm.c +++ b/arch/arm/mach-ux500/board-mop500-stm.c @@ -77,15 +77,9 @@ static int stm_ste_disable_ape_on_mipi60(void) /* * Manage STM output pins connection (MIP34/MIPI60 connectors) */ -#define PRCM_GPIOCR (_PRCMU_BASE + 0x138) -#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 -#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 - - static int stm_ste_connection(enum stm_connection_type con_type) { int retval = -EINVAL; - u32 gpiocr = readl(PRCM_GPIOCR); if (con_type != STM_DISCONNECT) { /* Always enable MIPI34 GPIO pins */ @@ -101,26 +95,19 @@ static int stm_ste_connection(enum stm_connection_type con_type) case STM_DEFAULT_CONNECTION: case STM_STE_MODEM_ON_MIPI34_NONE_ON_MIPI60: /* Enable altC3 on GPIO70-74 (STMMOD) & GPIO75-76 (UARTMOD) */ - gpiocr |= (PRCM_GPIOCR_DBG_STM_MOD_CMD1 - | PRCM_GPIOCR_DBG_UARTMOD_CMD0); - writel(gpiocr, PRCM_GPIOCR); + prcmu_enable_stm_mod_uart(); retval = stm_ste_disable_ape_on_mipi60(); break; case STM_STE_APE_ON_MIPI34_NONE_ON_MIPI60: /* Disable altC3 on GPIO70-74 (STMMOD) & GPIO75-76 (UARTMOD) */ - gpiocr &= ~(PRCM_GPIOCR_DBG_STM_MOD_CMD1 - | PRCM_GPIOCR_DBG_UARTMOD_CMD0); - writel(gpiocr, PRCM_GPIOCR); + prcmu_disable_stm_mod_uart(); retval = stm_ste_disable_ape_on_mipi60(); break; case STM_STE_MODEM_ON_MIPI34_APE_ON_MIPI60: /* Enable altC3 on GPIO70-74 (STMMOD) and GPIO75-76 (UARTMOD) */ - gpiocr |= (PRCM_GPIOCR_DBG_STM_MOD_CMD1 - | PRCM_GPIOCR_DBG_UARTMOD_CMD0); - writel(gpiocr, PRCM_GPIOCR); - + prcmu_enable_stm_mod_uart(); /* Enable APE on MIPI60 */ retval = nmk_config_pins_sleep(ARRAY_AND_SIZE(mop500_ske_pins)); if (retval) |