diff options
| author | Rabin Vincent <rabin.vincent@stericsson.com> | 2011-09-06 16:06:55 +0530 |
|---|---|---|
| committer | Rabin Vincent <rabin.vincent@stericsson.com> | 2011-09-22 15:41:26 +0530 |
| commit | aa6583cd791c847bc27ddcf810cde35610b33be0 (patch) | |
| tree | 312a4d2eff9878fdf9fcb7695a9535e0c121e4d6 | |
| parent | ff06a7b800df8a7dd93981b8971c572dcd897f49 (diff) | |
u5500: prcmu: implement DDR OPP handling
ST-Ericsson ID: 348762
ST-Ericsson FOSS-OUT ID: Trivial
ST-Ericsson Linux next: NA
Change-Id: I26770ee6151f91c70eebba1c1c460e7cdedd43e1
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/30502
Reviewed-by: QATOOLS
Reviewed-by: QABUILD
Reviewed-by: Vijaya Kumar K-1 <vijay.kilari@stericsson.com>
Reviewed-by: Mattias NILSSON <mattias.i.nilsson@stericsson.com>
Reviewed-by: QATEST
| -rw-r--r-- | arch/arm/mach-ux500/prcmu-db5500.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/prcmu-qos-power.c | 15 | ||||
| -rw-r--r-- | arch/arm/mach-ux500/prcmu-regs-db5500.h | 1 |
3 files changed, 22 insertions, 6 deletions
diff --git a/arch/arm/mach-ux500/prcmu-db5500.c b/arch/arm/mach-ux500/prcmu-db5500.c index 7e174ce377a..dbd9dfccfa6 100644 --- a/arch/arm/mach-ux500/prcmu-db5500.c +++ b/arch/arm/mach-ux500/prcmu-db5500.c @@ -1232,12 +1232,20 @@ int prcmu_get_ape_opp(void) int prcmu_get_ddr_opp(void) { - return DDR_100_OPP; + return readb(_PRCMU_BASE + PRCM_DDR_SUBSYS_APE_MINBW); } int prcmu_set_ddr_opp(u8 opp) { - return opp == DDR_100_OPP ? 0 : -EINVAL; + if (cpu_is_u5500v1()) + return -EINVAL; + + if (opp != DDR_100_OPP && opp != DDR_50_OPP) + return -EINVAL; + + writeb(opp, _PRCMU_BASE + PRCM_DDR_SUBSYS_APE_MINBW); + + return 0; } /** diff --git a/arch/arm/mach-ux500/prcmu-qos-power.c b/arch/arm/mach-ux500/prcmu-qos-power.c index bda51726bf3..1f49a60b92e 100644 --- a/arch/arm/mach-ux500/prcmu-qos-power.c +++ b/arch/arm/mach-ux500/prcmu-qos-power.c @@ -245,10 +245,6 @@ static void update_target(int target) switch (target) { case PRCMU_QOS_DDR_OPP: switch (extreme_value) { - case 25: - op = DDR_25_OPP; - pr_debug("prcmu qos: set ddr opp to 25%%\n"); - break; case 50: op = DDR_50_OPP; pr_debug("prcmu qos: set ddr opp to 50%%\n"); @@ -257,6 +253,13 @@ static void update_target(int target) op = DDR_100_OPP; pr_debug("prcmu qos: set ddr opp to 100%%\n"); break; + case 25: + /* 25% DDR OPP is not supported on 5500 */ + if (!cpu_is_u5500()) { + op = DDR_25_OPP; + pr_debug("prcmu qos: set ddr opp to 25%%\n"); + break; + } default: pr_err("prcmu qos: Incorrect ddr target value (%d)", extreme_value); @@ -667,6 +670,10 @@ static int __init prcmu_qos_power_init(void) { int ret = 0; + /* 25% DDR OPP is not supported on 5500 */ + if (cpu_is_u5500()) + ddr_opp_qos.default_value = 50; + ret = register_prcmu_qos_misc(&ape_opp_qos, &prcmu_qos_ape_power_fops); if (ret < 0) { pr_err("prcmu ape qos: setup failed\n"); diff --git a/arch/arm/mach-ux500/prcmu-regs-db5500.h b/arch/arm/mach-ux500/prcmu-regs-db5500.h index 12e8d10ca46..e8aa2901478 100644 --- a/arch/arm/mach-ux500/prcmu-regs-db5500.h +++ b/arch/arm/mach-ux500/prcmu-regs-db5500.h @@ -116,6 +116,7 @@ #define PRCM_MMIP_LS_CLAMP_SET 0x420 #define PRCM_MMIP_LS_CLAMP_CLR 0x424 +#define PRCM_DDR_SUBSYS_APE_MINBW 0x438 /* Miscellaneous unit registers */ #define PRCM_DSI_SW_RESET 0x324 |