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authorPawel Szyszuk <pawel.szyszuk@stericsson.com>2011-10-03 10:00:43 +0100
committerAndrew LYNN <andrew.lynn@stericsson.com>2011-10-03 11:35:56 +0200
commit43b316da6147f18a9382ca51520c5f3871b8b28f (patch)
treee73b2aeebe05ffb8334de34dad47c22f16b43a4c
parentd10756e942b172f6fe37fc16ad12674814a2554d (diff)
ARM: U9500: HSI core clocks initialization
ST-Ericsson Linux next: NA ST-Ericsson ID: 343481 ST-Ericsson FOSS-OUT ID: Trivial Change-Id: Ic59f08e1bb5d858344d95b5d34ae8a5d85d9aa1d Signed-off-by: Pawel Szyszuk <pawel.szyszuk@stericsson.com> Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/32518 Reviewed-by: Andrew LYNN <andrew.lynn@stericsson.com>
-rw-r--r--arch/arm/mach-ux500/clock-db8500.c22
-rw-r--r--arch/arm/mach-ux500/clock.c6
-rw-r--r--arch/arm/mach-ux500/clock.h1
-rw-r--r--drivers/hsi/controllers/ste_hsi.c17
4 files changed, 42 insertions, 4 deletions
diff --git a/arch/arm/mach-ux500/clock-db8500.c b/arch/arm/mach-ux500/clock-db8500.c
index f82fbaa5c83..f03d8361157 100644
--- a/arch/arm/mach-ux500/clock-db8500.c
+++ b/arch/arm/mach-ux500/clock-db8500.c
@@ -511,8 +511,8 @@ static DEF_PRCMU_CLK(per6clk, PRCMU_PER6CLK, 133330000);
static DEF_PRCMU_CLK(per7clk, PRCMU_PER7CLK, 100000000);
static DEF_PRCMU_SCALABLE_CLK(lcdclk, PRCMU_LCDCLK);
static DEF_PRCMU_OPP100_CLK(bmlclk, PRCMU_BMLCLK, 200000000);
-static DEF_PRCMU_CLK(hsitxclk, PRCMU_HSITXCLK, 100000000);
-static DEF_PRCMU_CLK(hsirxclk, PRCMU_HSIRXCLK, 200000000);
+static DEF_PRCMU_SCALABLE_CLK(hsitxclk, PRCMU_HSITXCLK);
+static DEF_PRCMU_SCALABLE_CLK(hsirxclk, PRCMU_HSIRXCLK);
static DEF_PRCMU_SCALABLE_CLK(hdmiclk, PRCMU_HDMICLK);
static DEF_PRCMU_CLK(apeatclk, PRCMU_APEATCLK, 160000000);
static DEF_PRCMU_CLK(apetraceclk, PRCMU_APETRACECLK, 160000000);
@@ -640,10 +640,24 @@ static DEF_PER2_KCLK(5, p2_sdi3_kclk, &sdmmcclk);
static DEF_PER_CLK(p2_sdi3_clk, &p2_pclk7, &p2_sdi3_kclk);
/* HSIR */
-static DEF_PER2_KCLK(6, p2_ssirx_kclk, &hsirxclk);
+static struct clk p2_ssirx_kclk = {
+ .name = "p2_ssirx_kclk",
+ .ops = &prcc_kclk_rec_ops,
+ .io_base = U8500_CLKRST2_BASE,
+ .cg_sel = BIT(6),
+ .parent = &hsirxclk,
+ .clock = &per2clk,
+};
/* HSIT */
-static DEF_PER2_KCLK(7, p2_ssitx_kclk, &hsitxclk);
+static struct clk p2_ssitx_kclk = {
+ .name = "p2_ssitx_kclk",
+ .ops = &prcc_kclk_rec_ops,
+ .io_base = U8500_CLKRST2_BASE,
+ .cg_sel = BIT(7),
+ .parent = &hsitxclk,
+ .clock = &per2clk,
+};
/* SSP0 */
static DEF_PER3_KCLK(1, p3_ssp0_kclk, &sspclk);
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 2f9ca7ea64d..06a9bdaec7d 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -428,6 +428,12 @@ struct clkops prcc_kclk_ops = {
.disable = prcc_kclk_disable,
};
+struct clkops prcc_kclk_rec_ops = {
+ .enable = prcc_kclk_enable,
+ .disable = prcc_kclk_disable,
+ .round_rate = clk_round_rate_rec,
+ .set_rate = clk_set_rate_rec,
+};
int __init clk_init(void)
{
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index 205c768b896..39d8a61d79b 100644
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -76,6 +76,7 @@ extern struct clkops prcmu_opp100_clk_ops;
extern struct mutex clk_opp100_mutex;
extern struct clkops prcc_pclk_ops;
extern struct clkops prcc_kclk_ops;
+extern struct clkops prcc_kclk_rec_ops;
extern struct clkops sga_clk_ops;
#define CLK_LOOKUP(_clk, _dev_id, _con_id) \
diff --git a/drivers/hsi/controllers/ste_hsi.c b/drivers/hsi/controllers/ste_hsi.c
index 07b39bb2868..a2cbb2108f7 100644
--- a/drivers/hsi/controllers/ste_hsi.c
+++ b/drivers/hsi/controllers/ste_hsi.c
@@ -1514,6 +1514,7 @@ static int __init ste_hsi_add_controller(struct hsi_controller *hsi,
char overrun_name[] = "hsi_rx_overrun_chxxx";
unsigned char i;
int err;
+ unsigned long rate;
ste_hsi = kzalloc(sizeof(struct ste_hsi_controller), GFP_KERNEL);
if (!ste_hsi) {
@@ -1586,6 +1587,22 @@ static int __init ste_hsi_add_controller(struct hsi_controller *hsi,
goto err_clk_free;
}
+ /* Set HSITXCLK rate to 100 MHz */
+ rate = clk_round_rate(ste_hsi->tx_clk, 100000000);
+ err = clk_set_rate(ste_hsi->tx_clk, rate);
+ if (unlikely(err)) {
+ dev_err(&hsi->device, "Couldn't set HSIT clock rate\n");
+ goto err_clk_free;
+ }
+
+ /* Set HSIRXCLK rate to 200 MHz */
+ rate = clk_round_rate(ste_hsi->rx_clk, 200000000);
+ err = clk_set_rate(ste_hsi->rx_clk, rate);
+ if (unlikely(err)) {
+ dev_err(&hsi->device, "Couldn't set HSIR clock rate\n");
+ goto err_clk_free;
+ }
+
err = ste_hsi_clock_enable(hsi);
if (unlikely(err))
goto err_clk_free;