video: mcde: Update mcde_regs.h

Updates mcde_regs.h according to new hardware specification.
No functional changes just renaming of constants.

ST-Ericsson ID: 362765
ST-Ericsson Linux next: NA
ST-Ericsson FOSS-OUT ID: Trivial

Change-Id: I45c4d84bf35c48cc0ea02f372451fc5ca6f89b17
Signed-off-by: Jimmy Rubin <jimmy.rubin@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/33327
Reviewed-by: QATOOLS
Reviewed-by: Per PERSSON <per.xb.persson@stericsson.com>
Reviewed-by: Marcus LORENTZON <marcus.xm.lorentzon@stericsson.com>

2 files changed, 105 insertions, 128 deletions

diff --git a/drivers/video/mcde/mcde_hw.c b/drivers/video/mcde/mcde_hw.c
index 3a3d273c3cb..7e8c010c710 100644
--- a/drivers/video/mcde/mcde_hw.c
+++ b/drivers/video/mcde/mcde_hw.c
@@ -1567,9 +1567,9 @@ void update_channel_registers(enum mcde_chnl chnl_id, struct chnl_regs *regs,
 			switch (port->sync_src) {
 			case MCDE_SYNCSRC_TE0:
 				out_synch_src =
-				MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC0;
+				MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_TE0;
 				src_synch =
-				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT;
+				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE;
 				break;
 			case MCDE_SYNCSRC_OFF:
 				src_synch =
@@ -1578,26 +1578,26 @@ void update_channel_registers(enum mcde_chnl chnl_id, struct chnl_regs *regs,
 			case MCDE_SYNCSRC_TE1:
 			default:
 				out_synch_src =
-				MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC1;
+				MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_TE1;
 				src_synch =
-				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT;
+				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE;
 				break;
 			case MCDE_SYNCSRC_TE_POLLING:
 				src_synch =
-				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT;
+				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE;
 				break;
 			}
 		} else {
 			if (port->sync_src == MCDE_SYNCSRC_TE0) {
 				out_synch_src =
-				MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC0;
+				MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_TE0;
 				src_synch =
-				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT;
+				MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE;
 			}
 		}
 	} else if (port->type == MCDE_PORTTYPE_DPI) {
 		src_synch = port->update_auto_trig ?
-					MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT :
+					MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE :
 					MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE;
 	}
 
@@ -1741,8 +1741,7 @@ void update_channel_registers(enum mcde_chnl chnl_id, struct chnl_regs *regs,
 		mcde_wreg(MCDE_ROTADD1A + chnl_id * MCDE_ROTADD1A_GROUPOFFSET,
 			regs->rotbuf2);
 		mcde_wreg(MCDE_ROTACONF + chnl_id * MCDE_ROTACONF_GROUPOFFSET,
-			MCDE_ROTACONF_ROTBURSTSIZE_ENUM(8W) |
-			MCDE_ROTACONF_ROTBURSTSIZE_HW(1) |
+			MCDE_ROTACONF_ROTBURSTSIZE_ENUM(HW_8W) |
 			MCDE_ROTACONF_ROTDIR(regs->rotdir) |
 			MCDE_ROTACONF_STRIP_WIDTH_ENUM(16PIX) |
 			MCDE_ROTACONF_RD_MAXOUT_ENUM(4_REQ) |
@@ -2239,7 +2238,7 @@ static int _mcde_chnl_apply(struct mcde_chnl_state *chnl)
 	chnl->regs.map_g = chnl->map_g;
 	chnl->regs.map_b = chnl->map_b;
 	if (chnl->port.type == MCDE_PORTTYPE_DSI) {
-		chnl->regs.clksel = MCDE_CRA1_CLKSEL_166MHZ;
+		chnl->regs.clksel = MCDE_CRA1_CLKSEL_MCDECLK;
 		chnl->regs.dsipacking =
 				portfmt2dsipacking(chnl->port.pixel_format);
 	} else if (chnl->port.type == MCDE_PORTTYPE_DPI) {
@@ -2247,12 +2246,12 @@ static int _mcde_chnl_apply(struct mcde_chnl_state *chnl)
 			chnl->regs.internal_clk = false;
 			chnl->regs.bcd = true;
 			if (chnl->id == MCDE_CHNL_A)
-				chnl->regs.clksel = MCDE_CRA1_CLKSEL_EXT_TV1;
+				chnl->regs.clksel = MCDE_CRA1_CLKSEL_TV1CLK;
 			else
-				chnl->regs.clksel = MCDE_CRA1_CLKSEL_EXT_TV2;
+				chnl->regs.clksel = MCDE_CRA1_CLKSEL_TV2CLK;
 		} else {
 			chnl->regs.internal_clk = true;
-			chnl->regs.clksel = MCDE_CRA1_CLKSEL_LCD;
+			chnl->regs.clksel = MCDE_CRA1_CLKSEL_CLKPLL72;
 			chnl->regs.cdwin =
 					portfmt2cdwin(chnl->port.pixel_format);
 			chnl->regs.bcd = (chnl->port.phy.dpi.clock_div < 2);
diff --git a/drivers/video/mcde/mcde_regs.h b/drivers/video/mcde/mcde_regs.h
index 034044d7401..0eece3faea2 100644
--- a/drivers/video/mcde/mcde_regs.h
+++ b/drivers/video/mcde/mcde_regs.h
@@ -2464,10 +2464,9 @@
 #define MCDE_CHNL0SYNCHMOD_GROUPOFFSET 0x20
 #define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SHIFT 0
 #define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_MASK 0x00000003
-#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT 0
-#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_AUTO 1
+#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE 0
+#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_NO_SYNCH 1
 #define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE 2
-#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_EXTERNAL 3
 #define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, SRC_SYNCH, \
 	MCDE_CHNL0SYNCHMOD_SRC_SYNCH_##__x)
@@ -2476,8 +2475,8 @@
 #define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
 #define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C
 #define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0
-#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1
-#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2
+#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_TE0 1
+#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_TE1 2
 #define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, OUT_SYNCH_SRC, \
 	MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_##__x)
@@ -2486,10 +2485,9 @@
 #define MCDE_CHNL1SYNCHMOD 0x00000628
 #define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_SHIFT 0
 #define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_MASK 0x00000003
-#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_OUTPUT 0
-#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_AUTO 1
+#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_HARDWARE 0
+#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_NO_SYNCH 1
 #define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_SOFTWARE 2
-#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_EXTERNAL 3
 #define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, SRC_SYNCH, \
 	MCDE_CHNL1SYNCHMOD_SRC_SYNCH_##__x)
@@ -2498,8 +2496,8 @@
 #define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
 #define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C
 #define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0
-#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1
-#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2
+#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_TE0 1
+#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_TE1 2
 #define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, OUT_SYNCH_SRC, \
 	MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_##__x)
@@ -2508,10 +2506,9 @@
 #define MCDE_CHNL2SYNCHMOD 0x00000648
 #define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_SHIFT 0
 #define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_MASK 0x00000003
-#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_OUTPUT 0
-#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_AUTO 1
+#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_HARDWARE 0
+#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_NO_SYNCH 1
 #define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_SOFTWARE 2
-#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_EXTERNAL 3
 #define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, SRC_SYNCH, \
 	MCDE_CHNL2SYNCHMOD_SRC_SYNCH_##__x)
@@ -2520,8 +2517,8 @@
 #define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
 #define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C
 #define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0
-#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1
-#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2
+#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_TE0 1
+#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_TE1 2
 #define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, OUT_SYNCH_SRC, \
 	MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_##__x)
@@ -2530,10 +2527,9 @@
 #define MCDE_CHNL3SYNCHMOD 0x00000668
 #define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_SHIFT 0
 #define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_MASK 0x00000003
-#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_OUTPUT 0
-#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_AUTO 1
+#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_HARDWARE 0
+#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_NO_SYNCH 1
 #define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_SOFTWARE 2
-#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_EXTERNAL 3
 #define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, SRC_SYNCH, \
 	MCDE_CHNL3SYNCHMOD_SRC_SYNCH_##__x)
@@ -2542,8 +2538,8 @@
 #define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
 #define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C
 #define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0
-#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1
-#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2
+#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_TE0 1
+#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_TE1 2
 #define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, OUT_SYNCH_SRC, \
 	MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_##__x)
@@ -2674,10 +2670,6 @@
 #define MCDE_CRA0_FLOEN_MASK 0x00000001
 #define MCDE_CRA0_FLOEN(__x) \
 	MCDE_VAL2REG(MCDE_CRA0, FLOEN, __x)
-#define MCDE_CRA0_POWEREN_SHIFT 1
-#define MCDE_CRA0_POWEREN_MASK 0x00000002
-#define MCDE_CRA0_POWEREN(__x) \
-	MCDE_VAL2REG(MCDE_CRA0, POWEREN, __x)
 #define MCDE_CRA0_BLENDEN_SHIFT 2
 #define MCDE_CRA0_BLENDEN_MASK 0x00000004
 #define MCDE_CRA0_BLENDEN(__x) \
@@ -2757,10 +2749,6 @@
 #define MCDE_CRB0_FLOEN_MASK 0x00000001
 #define MCDE_CRB0_FLOEN(__x) \
 	MCDE_VAL2REG(MCDE_CRB0, FLOEN, __x)
-#define MCDE_CRB0_POWEREN_SHIFT 1
-#define MCDE_CRB0_POWEREN_MASK 0x00000002
-#define MCDE_CRB0_POWEREN(__x) \
-	MCDE_VAL2REG(MCDE_CRB0, POWEREN, __x)
 #define MCDE_CRB0_BLENDEN_SHIFT 2
 #define MCDE_CRB0_BLENDEN_MASK 0x00000004
 #define MCDE_CRB0_BLENDEN(__x) \
@@ -2843,12 +2831,11 @@
 	MCDE_VAL2REG(MCDE_CRA1, PCD, __x)
 #define MCDE_CRA1_CLKSEL_SHIFT 10
 #define MCDE_CRA1_CLKSEL_MASK 0x00001C00
-#define MCDE_CRA1_CLKSEL_LCD 0
-#define MCDE_CRA1_CLKSEL_HDMI 1
-#define MCDE_CRA1_CLKSEL_TV 2
-#define MCDE_CRA1_CLKSEL_EXT_TV1 3
-#define MCDE_CRA1_CLKSEL_EXT_TV2 4
-#define MCDE_CRA1_CLKSEL_166MHZ 5
+#define MCDE_CRA1_CLKSEL_CLKPLL72 0
+#define MCDE_CRA1_CLKSEL_CLKPLL27 2
+#define MCDE_CRA1_CLKSEL_TV1CLK 3
+#define MCDE_CRA1_CLKSEL_TV2CLK 4
+#define MCDE_CRA1_CLKSEL_MCDECLK 5
 #define MCDE_CRA1_CLKSEL_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CRA1, CLKSEL, MCDE_CRA1_CLKSEL_##__x)
 #define MCDE_CRA1_CLKSEL(__x) \
@@ -2890,8 +2877,8 @@
 	MCDE_VAL2REG(MCDE_CRA1, BCD, __x)
 #define MCDE_CRA1_CLKTYPE_SHIFT 30
 #define MCDE_CRA1_CLKTYPE_MASK 0x40000000
-#define MCDE_CRA1_CLKTYPE_EXTERNAL 0
-#define MCDE_CRA1_CLKTYPE_INTERNAL 1
+#define MCDE_CRA1_CLKTYPE_TVXCLKSEL0 0
+#define MCDE_CRA1_CLKTYPE_TVXCLKSEL1 1
 #define MCDE_CRA1_CLKTYPE_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, MCDE_CRA1_CLKTYPE_##__x)
 #define MCDE_CRA1_CLKTYPE(__x) \
@@ -2903,12 +2890,11 @@
 	MCDE_VAL2REG(MCDE_CRB1, PCD, __x)
 #define MCDE_CRB1_CLKSEL_SHIFT 10
 #define MCDE_CRB1_CLKSEL_MASK 0x00001C00
-#define MCDE_CRB1_CLKSEL_LCD 0
-#define MCDE_CRB1_CLKSEL_HDMI 1
-#define MCDE_CRB1_CLKSEL_TV 2
-#define MCDE_CRB1_CLKSEL_EXT_TV1 3
-#define MCDE_CRB1_CLKSEL_EXT_TV2 4
-#define MCDE_CRB1_CLKSEL_166MHZ 5
+#define MCDE_CRB1_CLKSEL_CLKPLL72 0
+#define MCDE_CRB1_CLKSEL_CLKPLL27 2
+#define MCDE_CRB1_CLKSEL_TV1CLK 3
+#define MCDE_CRB1_CLKSEL_TV2CLK 4
+#define MCDE_CRB1_CLKSEL_MCDECLK 5
 #define MCDE_CRB1_CLKSEL_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CRB1, CLKSEL, MCDE_CRB1_CLKSEL_##__x)
 #define MCDE_CRB1_CLKSEL(__x) \
@@ -2950,8 +2936,8 @@
 	MCDE_VAL2REG(MCDE_CRB1, BCD, __x)
 #define MCDE_CRB1_CLKTYPE_SHIFT 30
 #define MCDE_CRB1_CLKTYPE_MASK 0x40000000
-#define MCDE_CRB1_CLKTYPE_EXTERNAL 0
-#define MCDE_CRB1_CLKTYPE_INTERNAL 1
+#define MCDE_CRB1_CLKTYPE_TVXCLKSEL0 0
+#define MCDE_CRB1_CLKTYPE_TVXCLKSEL1 1
 #define MCDE_CRB1_CLKTYPE_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, MCDE_CRB1_CLKTYPE_##__x)
 #define MCDE_CRB1_CLKTYPE(__x) \
@@ -3231,8 +3217,6 @@
 #define MCDE_TVCRA_TVMODE_SHIFT 3
 #define MCDE_TVCRA_TVMODE_MASK 0x00000038
 #define MCDE_TVCRA_TVMODE_SDTV_656P 0
-#define MCDE_TVCRA_TVMODE_HDTV_480P 1
-#define MCDE_TVCRA_TVMODE_HDTV_720P 2
 #define MCDE_TVCRA_TVMODE_SDTV_656P_LE 3
 #define MCDE_TVCRA_TVMODE_SDTV_656P_BE 4
 #define MCDE_TVCRA_TVMODE_ENUM(__x) \
@@ -3275,8 +3259,6 @@
 #define MCDE_TVCRB_TVMODE_SHIFT 3
 #define MCDE_TVCRB_TVMODE_MASK 0x00000038
 #define MCDE_TVCRB_TVMODE_SDTV_656P 0
-#define MCDE_TVCRB_TVMODE_HDTV_480P 1
-#define MCDE_TVCRB_TVMODE_HDTV_720P 2
 #define MCDE_TVCRB_TVMODE_SDTV_656P_LE 3
 #define MCDE_TVCRB_TVMODE_SDTV_656P_BE 4
 #define MCDE_TVCRB_TVMODE_ENUM(__x) \
@@ -3485,6 +3467,10 @@
 #define MCDE_DITCTRLA_COMP_MASK 0x00000002
 #define MCDE_DITCTRLA_COMP(__x) \
 	MCDE_VAL2REG(MCDE_DITCTRLA, COMP, __x)
+#define MCDE_DITCTRLA_MODE_SHIFT 2
+#define MCDE_DITCTRLA_MODE_MASK 0x0000000C
+#define MCDE_DITCTRLA_MODE(__x) \
+	MCDE_VAL2REG(MCDE_DITCTRLA, MODE, __x)
 #define MCDE_DITCTRLA_MASK_SHIFT 4
 #define MCDE_DITCTRLA_MASK_MASK 0x00000010
 #define MCDE_DITCTRLA_MASK(__x) \
@@ -3506,6 +3492,10 @@
 #define MCDE_DITCTRLB_COMP_MASK 0x00000002
 #define MCDE_DITCTRLB_COMP(__x) \
 	MCDE_VAL2REG(MCDE_DITCTRLB, COMP, __x)
+#define MCDE_DITCTRLB_MODE_SHIFT 2
+#define MCDE_DITCTRLB_MODE_MASK 0x0000000C
+#define MCDE_DITCTRLB_MODE(__x) \
+	MCDE_VAL2REG(MCDE_DITCTRLB, MODE, __x)
 #define MCDE_DITCTRLB_MASK_SHIFT 4
 #define MCDE_DITCTRLB_MASK_MASK 0x00000010
 #define MCDE_DITCTRLB_MASK(__x) \
@@ -3608,20 +3598,20 @@
 #define MCDE_ROTACONF 0x0000087C
 #define MCDE_ROTACONF_GROUPOFFSET 0x200
 #define MCDE_ROTACONF_ROTBURSTSIZE_SHIFT 0
-#define MCDE_ROTACONF_ROTBURSTSIZE_MASK 0x00000003
+#define MCDE_ROTACONF_ROTBURSTSIZE_MASK 0x00000007
 #define MCDE_ROTACONF_ROTBURSTSIZE_1W 0
 #define MCDE_ROTACONF_ROTBURSTSIZE_2W 1
 #define MCDE_ROTACONF_ROTBURSTSIZE_4W 2
 #define MCDE_ROTACONF_ROTBURSTSIZE_8W 3
+#define MCDE_ROTACONF_ROTBURSTSIZE_HW_1W 4
+#define MCDE_ROTACONF_ROTBURSTSIZE_HW_2W 5
+#define MCDE_ROTACONF_ROTBURSTSIZE_HW_4W 6
+#define MCDE_ROTACONF_ROTBURSTSIZE_HW_8W 7
 #define MCDE_ROTACONF_ROTBURSTSIZE_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE, \
 	MCDE_ROTACONF_ROTBURSTSIZE_##__x)
 #define MCDE_ROTACONF_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE, __x)
-#define MCDE_ROTACONF_ROTBURSTSIZE_HW_SHIFT 2
-#define MCDE_ROTACONF_ROTBURSTSIZE_HW_MASK 0x00000004
-#define MCDE_ROTACONF_ROTBURSTSIZE_HW(__x) \
-	MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE_HW, __x)
 #define MCDE_ROTACONF_ROTDIR_SHIFT 3
 #define MCDE_ROTACONF_ROTDIR_MASK 0x00000008
 #define MCDE_ROTACONF_ROTDIR_CCW 0
@@ -3676,20 +3666,20 @@
 	MCDE_VAL2REG(MCDE_ROTACONF, RD_ROPC, __x)
 #define MCDE_ROTBCONF 0x00000A7C
 #define MCDE_ROTBCONF_ROTBURSTSIZE_SHIFT 0
-#define MCDE_ROTBCONF_ROTBURSTSIZE_MASK 0x00000003
+#define MCDE_ROTBCONF_ROTBURSTSIZE_MASK 0x00000007
 #define MCDE_ROTBCONF_ROTBURSTSIZE_1W 0
 #define MCDE_ROTBCONF_ROTBURSTSIZE_2W 1
 #define MCDE_ROTBCONF_ROTBURSTSIZE_4W 2
 #define MCDE_ROTBCONF_ROTBURSTSIZE_8W 3
+#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_1W 4
+#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_2W 5
+#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_4W 6
+#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_8W 7
 #define MCDE_ROTBCONF_ROTBURSTSIZE_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE, \
 	MCDE_ROTBCONF_ROTBURSTSIZE_##__x)
 #define MCDE_ROTBCONF_ROTBURSTSIZE(__x) \
 	MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE, __x)
-#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_SHIFT 2
-#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_MASK 0x00000004
-#define MCDE_ROTBCONF_ROTBURSTSIZE_HW(__x) \
-	MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE_HW, __x)
 #define MCDE_ROTBCONF_ROTDIR_SHIFT 3
 #define MCDE_ROTBCONF_ROTDIR_MASK 0x00000008
 #define MCDE_ROTBCONF_ROTDIR_CCW 0
@@ -4026,14 +4016,6 @@
 #define MCDE_OLEDCONV6B_OFF_BLUE(__x) \
 	MCDE_VAL2REG(MCDE_OLEDCONV6B, OFF_BLUE, __x)
 #define MCDE_CRC 0x00000C00
-#define MCDE_CRC_FLOEN_SHIFT 0
-#define MCDE_CRC_FLOEN_MASK 0x00000001
-#define MCDE_CRC_FLOEN(__x) \
-	MCDE_VAL2REG(MCDE_CRC, FLOEN, __x)
-#define MCDE_CRC_POWEREN_SHIFT 1
-#define MCDE_CRC_POWEREN_MASK 0x00000002
-#define MCDE_CRC_POWEREN(__x) \
-	MCDE_VAL2REG(MCDE_CRC, POWEREN, __x)
 #define MCDE_CRC_C1EN_SHIFT 2
 #define MCDE_CRC_C1EN_MASK 0x00000004
 #define MCDE_CRC_C1EN(__x) \
@@ -4042,18 +4024,6 @@
 #define MCDE_CRC_C2EN_MASK 0x00000008
 #define MCDE_CRC_C2EN(__x) \
 	MCDE_VAL2REG(MCDE_CRC, C2EN, __x)
-#define MCDE_CRC_WMLVL1_SHIFT 4
-#define MCDE_CRC_WMLVL1_MASK 0x00000010
-#define MCDE_CRC_WMLVL1(__x) \
-	MCDE_VAL2REG(MCDE_CRC, WMLVL1, __x)
-#define MCDE_CRC_WMLVL2_SHIFT 5
-#define MCDE_CRC_WMLVL2_MASK 0x00000020
-#define MCDE_CRC_WMLVL2(__x) \
-	MCDE_VAL2REG(MCDE_CRC, WMLVL2, __x)
-#define MCDE_CRC_SYNCSEL_SHIFT 6
-#define MCDE_CRC_SYNCSEL_MASK 0x00000040
-#define MCDE_CRC_SYNCSEL(__x) \
-	MCDE_VAL2REG(MCDE_CRC, SYNCSEL, __x)
 #define MCDE_CRC_SYCEN0_SHIFT 7
 #define MCDE_CRC_SYCEN0_MASK 0x00000080
 #define MCDE_CRC_SYCEN0(__x) \
@@ -4070,23 +4040,6 @@
 #define MCDE_CRC_SIZE2_MASK 0x00000400
 #define MCDE_CRC_SIZE2(__x) \
 	MCDE_VAL2REG(MCDE_CRC, SIZE2, __x)
-#define MCDE_CRC_INBAND1_SHIFT 11
-#define MCDE_CRC_INBAND1_MASK 0x00000800
-#define MCDE_CRC_INBAND1(__x) \
-	MCDE_VAL2REG(MCDE_CRC, INBAND1, __x)
-#define MCDE_CRC_INBAND2_SHIFT 12
-#define MCDE_CRC_INBAND2_MASK 0x00001000
-#define MCDE_CRC_INBAND2(__x) \
-	MCDE_VAL2REG(MCDE_CRC, INBAND2, __x)
-#define MCDE_CRC_CLKSEL_SHIFT 13
-#define MCDE_CRC_CLKSEL_MASK 0x00006000
-#define MCDE_CRC_CLKSEL_166MHz 0
-#define MCDE_CRC_CLKSEL_48MHz 1
-#define MCDE_CRC_CLKSEL_LCD 2
-#define MCDE_CRC_CLKSEL_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CRC, CLKSEL, MCDE_CRC_CLKSEL_##__x)
-#define MCDE_CRC_CLKSEL(__x) \
-	MCDE_VAL2REG(MCDE_CRC, CLKSEL, __x)
 #define MCDE_CRC_YUVCONVC1EN_SHIFT 15
 #define MCDE_CRC_YUVCONVC1EN_MASK 0x00008000
 #define MCDE_CRC_YUVCONVC1EN(__x) \
@@ -4099,10 +4052,6 @@
 #define MCDE_CRC_CS2EN_MASK 0x00020000
 #define MCDE_CRC_CS2EN(__x) \
 	MCDE_VAL2REG(MCDE_CRC, CS2EN, __x)
-#define MCDE_CRC_RESEN_SHIFT 18
-#define MCDE_CRC_RESEN_MASK 0x00040000
-#define MCDE_CRC_RESEN(__x) \
-	MCDE_VAL2REG(MCDE_CRC, RESEN, __x)
 #define MCDE_CRC_CS1POL_SHIFT 19
 #define MCDE_CRC_CS1POL_MASK 0x00080000
 #define MCDE_CRC_CS1POL(__x) \
@@ -4135,19 +4084,11 @@
 #define MCDE_CRC_RD2POL_MASK 0x04000000
 #define MCDE_CRC_RD2POL(__x) \
 	MCDE_VAL2REG(MCDE_CRC, RD2POL, __x)
-#define MCDE_CRC_RES1POL_SHIFT 27
-#define MCDE_CRC_RES1POL_MASK 0x08000000
-#define MCDE_CRC_RES1POL(__x) \
-	MCDE_VAL2REG(MCDE_CRC, RES1POL, __x)
-#define MCDE_CRC_RES2POL_SHIFT 28
-#define MCDE_CRC_RES2POL_MASK 0x10000000
-#define MCDE_CRC_RES2POL(__x) \
-	MCDE_VAL2REG(MCDE_CRC, RES2POL, __x)
 #define MCDE_CRC_SYNCCTRL_SHIFT 29
 #define MCDE_CRC_SYNCCTRL_MASK 0x60000000
-#define MCDE_CRC_SYNCCTRL_OFF 0
-#define MCDE_CRC_SYNCCTRL_C0 1
-#define MCDE_CRC_SYNCCTRL_C1 2
+#define MCDE_CRC_SYNCCTRL_NO_SYNC 0
+#define MCDE_CRC_SYNCCTRL_DBI0 1
+#define MCDE_CRC_SYNCCTRL_DBI1 2
 #define MCDE_CRC_SYNCCTRL_PING_PONG 3
 #define MCDE_CRC_SYNCCTRL_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_CRC, SYNCCTRL, MCDE_CRC_SYNCCTRL_##__x)
@@ -4337,6 +4278,16 @@
 	MCDE_VAL2REG(MCDE_VSCRC0, VSPMAX, __x)
 #define MCDE_VSCRC0_VSPDIV_SHIFT 24
 #define MCDE_VSCRC0_VSPDIV_MASK 0x07000000
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_1 0
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_2 1
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_4 2
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_8 3
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_16 4
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_32 5
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_64 6
+#define MCDE_VSCRC0_VSPDIV_MCDECLK_DIV_128 7
+#define MCDE_VSCRC0_VSPDIV_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_VSCRC0, VSPDIV, MCDE_VSCRC0_VSPDIV_##__x)
 #define MCDE_VSCRC0_VSPDIV(__x) \
 	MCDE_VAL2REG(MCDE_VSCRC0, VSPDIV, __x)
 #define MCDE_VSCRC0_VSPOL_SHIFT 27
@@ -4349,8 +4300,8 @@
 	MCDE_VAL2REG(MCDE_VSCRC0, VSPOL, __x)
 #define MCDE_VSCRC0_VSSEL_SHIFT 28
 #define MCDE_VSCRC0_VSSEL_MASK 0x10000000
-#define MCDE_VSCRC0_VSSEL_VSYNC 0
-#define MCDE_VSCRC0_VSSEL_HSYNC 1
+#define MCDE_VSCRC0_VSSEL_VSYNC0 0
+#define MCDE_VSCRC0_VSSEL_VSYNC1 1
 #define MCDE_VSCRC0_VSSEL_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_VSCRC0, VSSEL, MCDE_VSCRC0_VSSEL_##__x)
 #define MCDE_VSCRC0_VSSEL(__x) \
@@ -4370,6 +4321,16 @@
 	MCDE_VAL2REG(MCDE_VSCRC1, VSPMAX, __x)
 #define MCDE_VSCRC1_VSPDIV_SHIFT 24
 #define MCDE_VSCRC1_VSPDIV_MASK 0x07000000
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_1 0
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_2 1
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_4 2
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_8 3
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_16 4
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_32 5
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_64 6
+#define MCDE_VSCRC1_VSPDIV_MCDECLK_DIV_128 7
+#define MCDE_VSCRC1_VSPDIV_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_VSCRC1, VSPDIV, MCDE_VSCRC1_VSPDIV_##__x)
 #define MCDE_VSCRC1_VSPDIV(__x) \
 	MCDE_VAL2REG(MCDE_VSCRC1, VSPDIV, __x)
 #define MCDE_VSCRC1_VSPOL_SHIFT 27
@@ -4382,8 +4343,8 @@
 	MCDE_VAL2REG(MCDE_VSCRC1, VSPOL, __x)
 #define MCDE_VSCRC1_VSSEL_SHIFT 28
 #define MCDE_VSCRC1_VSSEL_MASK 0x10000000
-#define MCDE_VSCRC1_VSSEL_VSYNC 0
-#define MCDE_VSCRC1_VSSEL_HSYNC 1
+#define MCDE_VSCRC1_VSSEL_VSYNC0 0
+#define MCDE_VSCRC1_VSSEL_VSYNC1 1
 #define MCDE_VSCRC1_VSSEL_ENUM(__x) \
 	MCDE_VAL2REG(MCDE_VSCRC1, VSSEL, MCDE_VSCRC1_VSSEL_##__x)
 #define MCDE_VSCRC1_VSSEL(__x) \
@@ -4512,11 +4473,19 @@
 #define MCDE_WDATADC0_DATAVALUE_MASK 0x00FFFFFF
 #define MCDE_WDATADC0_DATAVALUE(__x) \
 	MCDE_VAL2REG(MCDE_WDATADC0, DATAVALUE, __x)
+#define MCDE_WDATADC0_DC_SHIFT 24
+#define MCDE_WDATADC0_DC_MASK 0x01000000
+#define MCDE_WDATADC0_DC(__x) \
+	MCDE_VAL2REG(MCDE_WDATADC0, DC, __x)
 #define MCDE_WDATADC1 0x00000C98
 #define MCDE_WDATADC1_DATAVALUE_SHIFT 0
 #define MCDE_WDATADC1_DATAVALUE_MASK 0x00FFFFFF
 #define MCDE_WDATADC1_DATAVALUE(__x) \
 	MCDE_VAL2REG(MCDE_WDATADC1, DATAVALUE, __x)
+#define MCDE_WDATADC1_DC_SHIFT 24
+#define MCDE_WDATADC1_DC_MASK 0x01000000
+#define MCDE_WDATADC1_DC(__x) \
+	MCDE_VAL2REG(MCDE_WDATADC1, DC, __x)
 #define MCDE_RDATADC0 0x00000C9C
 #define MCDE_RDATADC0_GROUPOFFSET 0x4
 #define MCDE_RDATADC0_DATAREADFROMDISPLAYMODULE_SHIFT 0
@@ -4536,6 +4505,15 @@
 #define MCDE_RDATADC1_STARTREAD_MASK 0x00010000
 #define MCDE_RDATADC1_STARTREAD(__x) \
 	MCDE_VAL2REG(MCDE_RDATADC1, STARTREAD, __x)
+#define MCDE_STATC 0x00000CA4
+#define MCDE_STATC_STATBUSY0_SHIFT 0
+#define MCDE_STATC_STATBUSY0_MASK 0x00000001
+#define MCDE_STATC_STATBUSY0(__x) \
+	MCDE_VAL2REG(MCDE_STATC, STATBUSY0, __x)
+#define MCDE_STATC_STATBUSY1_SHIFT 5
+#define MCDE_STATC_STATBUSY1_MASK 0x00000020
+#define MCDE_STATC_STATBUSY1(__x) \
+	MCDE_VAL2REG(MCDE_STATC, STATBUSY1, __x)
 #define MCDE_CTRLC0 0x00000CA8
 #define MCDE_CTRLC0_GROUPOFFSET 0x4
 #define MCDE_CTRLC0_FIFOWTRMRK_SHIFT 0