video: mcde: Remove MCDE 3_0_5 version support

This MCDE version is used in db8500 v1.

ST-Ericsson ID: 362765
ST-Ericsson Linux next: NA
ST-Ericsson FOSS-OUT ID: Trivial

Change-Id: Ie5039e8d2bb838c900f6b14c18cce097f57a393d
Signed-off-by: Jimmy Rubin <jimmy.rubin@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/33321
Reviewed-by: QATOOLS
Reviewed-by: Per PERSSON <per.xb.persson@stericsson.com>
Reviewed-by: Marcus LORENTZON <marcus.xm.lorentzon@stericsson.com>

3 files changed, 96 insertions, 525 deletions

diff --git a/drivers/video/mcde/mcde_hw.c b/drivers/video/mcde/mcde_hw.c
index 164bead10b5..aab9c30966c 100644
--- a/drivers/video/mcde/mcde_hw.c
+++ b/drivers/video/mcde/mcde_hw.c
@@ -69,7 +69,7 @@ static void dsi_te_poll_set_timer(struct mcde_chnl_state *chnl,
 		unsigned int timeout);
 static void dsi_te_timer_function(unsigned long value);
 static int wait_for_vcmp(struct mcde_chnl_state *chnl);
-static void probe_hw(void);
+static int probe_hw(void);
 static void wait_for_flow_disabled(struct mcde_chnl_state *chnl);
 
 #define OVLY_TIMEOUT 100
@@ -322,7 +322,6 @@ struct mcde_chnl_state {
 	struct mcde_port port;
 	struct mcde_ovly_state *ovly0;
 	struct mcde_ovly_state *ovly1;
-	const struct chnl_config *cfg;
 	enum chnl_state state;
 	wait_queue_head_t state_waitq;
 	wait_queue_head_t vcmp_waitq;
@@ -364,105 +363,6 @@ struct mcde_chnl_state {
 };
 
 static struct mcde_chnl_state *channels;
-
-struct chnl_config {
-	/* Key */
-	enum mcde_chnl_path path;
-
-	/* Value */
-	bool swap_a_c0;
-	bool swap_a_c0_set;
-	bool swap_b_c1;
-	bool swap_b_c1_set;
-	bool fabmux;
-	bool fabmux_set;
-	bool f01mux;
-	bool f01mux_set;
-};
-
-static /* TODO: const, compiler bug? */ struct chnl_config chnl_configs[] = {
-	/* Channel A */
-	{ .path = MCDE_CHNLPATH_CHNLA_FIFOA_DPI_0,
-	  .swap_a_c0 = false, .swap_a_c0_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_0,
-	  .swap_a_c0 = false, .swap_a_c0_set = true,
-	  .fabmux = false, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_1,
-	  .swap_a_c0 = false, .swap_a_c0_set = true,
-	  .fabmux = true, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC0_2,
-	  .swap_a_c0 = true, .swap_a_c0_set = true,
-	  .f01mux = false, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_0,
-	  .swap_a_c0 = true, .swap_a_c0_set = true,
-	  .f01mux = false, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_1,
-	  .swap_a_c0 = true, .swap_a_c0_set = true,
-	  .f01mux = true, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC1_2,
-	  .swap_a_c0 = false, .swap_a_c0_set = true,
-	  .fabmux = false, .fabmux_set = true },
-	/* Channel B */
-	{ .path = MCDE_CHNLPATH_CHNLB_FIFOB_DPI_1,
-	  .swap_b_c1 = false, .swap_b_c1_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_0,
-	  .swap_b_c1 = false, .swap_b_c1_set = true,
-	  .fabmux = true, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_1,
-	  .swap_b_c1 = false, .swap_b_c1_set = true,
-	  .fabmux = false, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC0_2,
-	  .swap_b_c1 = true, .swap_b_c1_set = true,
-	  .f01mux = true, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_0,
-	  .swap_b_c1 = true, .swap_b_c1_set = true,
-	  .f01mux = true, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_1,
-	  .swap_b_c1 = true, .swap_b_c1_set = true,
-	  .f01mux = false, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC1_2,
-	  .swap_b_c1 = false, .swap_b_c1_set = true,
-	  .fabmux = true, .fabmux_set = true },
-	/* Channel C0 */
-	{ .path = MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_0,
-	  .swap_a_c0 = true, .swap_a_c0_set = true,
-	  .fabmux = false, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_1,
-	  .swap_a_c0 = true, .swap_a_c0_set = true,
-	  .fabmux = true, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC0_2,
-	  .swap_a_c0 = false, .swap_a_c0_set = true,
-	  .f01mux = false, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_0,
-	  .swap_a_c0 = false, .swap_a_c0_set = true,
-	  .f01mux = false, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_1,
-	  .swap_a_c0 = false, .swap_a_c0_set = true,
-	  .f01mux = true, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC1_2,
-	  .swap_a_c0 = true, .swap_a_c0_set = true,
-	  .fabmux = false, .fabmux_set = true },
-	/* Channel C1 */
-	{ .path = MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_0,
-	  .swap_b_c1 = true, .swap_b_c1_set = true,
-	  .fabmux = true, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_1,
-	  .swap_b_c1 = true, .swap_b_c1_set = true,
-	  .fabmux = false, .fabmux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC0_2,
-	  .swap_b_c1 = false, .swap_b_c1_set = true,
-	  .f01mux = true, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_0,
-	  .swap_b_c1 = false, .swap_b_c1_set = true,
-	  .f01mux = true, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_1,
-	  .swap_b_c1 = false, .swap_b_c1_set = true,
-	  .f01mux = false, .f01mux_set = true },
-	{ .path = MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC1_2,
-	  .swap_b_c1 = true, .swap_b_c1_set = true,
-	  .fabmux = true, .fabmux_set = true },
-};
-
 /*
  * Wait for CSM_RUNNING, all data sent for display
  */
@@ -647,15 +547,7 @@ static void dpi_video_mode_apply(struct mcde_chnl_state *chnl)
 			chnl->tv_regs.tv_mode = MCDE_TVCRA_TVMODE_SDTV_656P_BE;
 		else
 			chnl->tv_regs.tv_mode = MCDE_TVCRA_TVMODE_SDTV_656P;
-		if (hardware_version == MCDE_CHIP_VERSION_3_0_8 ||
-			hardware_version == MCDE_CHIP_VERSION_4_0_4)
-			chnl->tv_regs.inv_clk = true;
-		else {
-			chnl->tv_regs.dho  = MCDE_CONFIG_TVOUT_HBORDER;
-			chnl->tv_regs.alw  = MCDE_CONFIG_TVOUT_HBORDER;
-			chnl->tv_regs.dvo  = MCDE_CONFIG_TVOUT_VBORDER;
-			chnl->tv_regs.bsl  = MCDE_CONFIG_TVOUT_VBORDER;
-		}
+		chnl->tv_regs.inv_clk = true;
 	} else {
 		/* LCD mode */
 		u32 polarity;
@@ -714,24 +606,11 @@ static void update_dpi_registers(enum mcde_chnl chnl_id, struct tv_regs *regs)
 					MCDE_TVISLA_FSL2(regs->fsl2));
 
 	/* Horizontal timing registers */
-	if (!regs->sel_mode_tv ||
-			hardware_version == MCDE_CHIP_VERSION_3_0_8 ||
-			hardware_version == MCDE_CHIP_VERSION_4_0_4) {
-		mcde_wreg(MCDE_TVLBALWA + idx * MCDE_TVLBALWA_GROUPOFFSET,
-					MCDE_TVLBALWA_LBW(regs->hsw) |
-					MCDE_TVLBALWA_ALW(regs->alw));
-		mcde_wreg(MCDE_TVTIM1A + idx * MCDE_TVTIM1A_GROUPOFFSET,
-					MCDE_TVTIM1A_DHO(regs->dho));
-	} else {
-		/* in earlier versions the LBW and DHO fields are swapped
-		 * TV mode only
-		 */
-		mcde_wreg(MCDE_TVLBALWA + idx * MCDE_TVLBALWA_GROUPOFFSET,
-					MCDE_TVLBALWA_LBW(regs->dho) |
-					MCDE_TVLBALWA_ALW(regs->alw));
-		mcde_wreg(MCDE_TVTIM1A + idx * MCDE_TVTIM1A_GROUPOFFSET,
-					MCDE_TVTIM1A_DHO(regs->hsw));
-	}
+	mcde_wreg(MCDE_TVLBALWA + idx * MCDE_TVLBALWA_GROUPOFFSET,
+				MCDE_TVLBALWA_LBW(regs->hsw) |
+				MCDE_TVLBALWA_ALW(regs->alw));
+	mcde_wreg(MCDE_TVTIM1A + idx * MCDE_TVTIM1A_GROUPOFFSET,
+				MCDE_TVTIM1A_DHO(regs->dho));
 	if (!regs->sel_mode_tv)
 		mcde_wreg(MCDE_LCDTIM1A + idx * MCDE_LCDTIM1A_GROUPOFFSET,
 								regs->lcdtim1);
@@ -1076,46 +955,14 @@ static int wait_for_vcmp(struct mcde_chnl_state *chnl)
 
 static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 {
-	const struct chnl_config *cfg = chnl->cfg;
 	const struct mcde_port *port = &chnl->port;
 
-	if (hardware_version == MCDE_CHIP_VERSION_3_0_5) {
-		/* Fifo & muxing */
-		if (cfg->swap_a_c0_set)
-			mcde_wfld(MCDE_CONF0, SWAP_A_C0_V1, cfg->swap_a_c0);
-		if (cfg->swap_b_c1_set)
-			mcde_wfld(MCDE_CONF0, SWAP_B_C1_V1, cfg->swap_b_c1);
-		if (cfg->fabmux_set)
-			mcde_wfld(MCDE_CR, FABMUX_V1, cfg->fabmux);
-		if (cfg->f01mux_set)
-			mcde_wfld(MCDE_CR, F01MUX_V1, cfg->f01mux);
-
-		if (port->type == MCDE_PORTTYPE_DPI) {
-			if (port->link == 0)
-				mcde_wfld(MCDE_CR, DPIA_EN_V1, true);
-			else if (port->link == 1)
-				mcde_wfld(MCDE_CR, DPIB_EN_V1, true);
-		} else if (port->type == MCDE_PORTTYPE_DSI) {
-			if (port->ifc == DSI_VIDEO_MODE && port->link == 0)
-				mcde_wfld(MCDE_CR, DSIVID0_EN_V1, true);
-			else if (port->ifc == DSI_VIDEO_MODE && port->link == 1)
-				mcde_wfld(MCDE_CR, DSIVID1_EN_V1, true);
-			else if (port->ifc == DSI_VIDEO_MODE && port->link == 2)
-				mcde_wfld(MCDE_CR, DSIVID2_EN_V1, true);
-			else if (port->ifc == DSI_CMD_MODE && port->link == 0)
-				mcde_wfld(MCDE_CR, DSICMD0_EN_V1, true);
-			else if (port->ifc == DSI_CMD_MODE && port->link == 1)
-				mcde_wfld(MCDE_CR, DSICMD1_EN_V1, true);
-			else if (port->ifc == DSI_CMD_MODE && port->link == 2)
-				mcde_wfld(MCDE_CR, DSICMD2_EN_V1, true);
-		}
-	} else if (hardware_version == MCDE_CHIP_VERSION_3_0_8 ||
-			hardware_version == MCDE_CHIP_VERSION_4_0_4) {
+	if (hardware_version != MCDE_CHIP_VERSION_1_0_4) {
 		switch (chnl->fifo) {
 		case MCDE_FIFO_A:
-			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
-				MCDE_CHNL0MUXING_V2_GROUPOFFSET,
-				MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_A));
+			mcde_wreg(MCDE_CHNL0MUXING + chnl->id *
+				MCDE_CHNL0MUXING_GROUPOFFSET,
+				MCDE_CHNL0MUXING_FIFO_ID_ENUM(FIFO_A));
 			if (port->type == MCDE_PORTTYPE_DPI) {
 				mcde_wfld(MCDE_CTRLA, FORMTYPE,
 						MCDE_CTRLA_FORMTYPE_DPITV);
@@ -1128,9 +975,9 @@ static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 			}
 			break;
 		case MCDE_FIFO_B:
-			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
-				MCDE_CHNL0MUXING_V2_GROUPOFFSET,
-				MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_B));
+			mcde_wreg(MCDE_CHNL0MUXING + chnl->id *
+				MCDE_CHNL0MUXING_GROUPOFFSET,
+				MCDE_CHNL0MUXING_FIFO_ID_ENUM(FIFO_B));
 			if (port->type == MCDE_PORTTYPE_DPI) {
 				mcde_wfld(MCDE_CTRLB, FORMTYPE,
 						MCDE_CTRLB_FORMTYPE_DPITV);
@@ -1144,9 +991,9 @@ static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 
 			break;
 		case MCDE_FIFO_C0:
-			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
-				MCDE_CHNL0MUXING_V2_GROUPOFFSET,
-				MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_C0));
+			mcde_wreg(MCDE_CHNL0MUXING + chnl->id *
+				MCDE_CHNL0MUXING_GROUPOFFSET,
+				MCDE_CHNL0MUXING_FIFO_ID_ENUM(FIFO_C0));
 			if (port->type == MCDE_PORTTYPE_DPI)
 				return -EINVAL;
 			mcde_wfld(MCDE_CTRLC0, FORMTYPE,
@@ -1154,9 +1001,9 @@ static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 			mcde_wfld(MCDE_CTRLC0, FORMID, get_dsi_formid(port));
 			break;
 		case MCDE_FIFO_C1:
-			mcde_wreg(MCDE_CHNL0MUXING_V2 + chnl->id *
-				MCDE_CHNL0MUXING_V2_GROUPOFFSET,
-				MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(FIFO_C1));
+			mcde_wreg(MCDE_CHNL0MUXING + chnl->id *
+				MCDE_CHNL0MUXING_GROUPOFFSET,
+				MCDE_CHNL0MUXING_FIFO_ID_ENUM(FIFO_C1));
 			if (port->type == MCDE_PORTTYPE_DPI)
 				return -EINVAL;
 			mcde_wfld(MCDE_CTRLC1, FORMTYPE,
@@ -1166,7 +1013,7 @@ static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 		default:
 			return -EINVAL;
 		}
-	} else if (hardware_version == MCDE_CHIP_VERSION_1_0_4) {
+	} else {
 		switch (chnl->fifo) {
 		case MCDE_FIFO_A:
 			/* only channel A is supported */
@@ -1237,12 +1084,6 @@ static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 		dev_dbg(&mcde_dev->dev, "DSI%d LINK_EN\n", lnk);
 
 		if (port->sync_src == MCDE_SYNCSRC_TE_POLLING) {
-			if (hardware_version == MCDE_CHIP_VERSION_3_0_5) {
-				dev_err(&mcde_dev->dev,
-				"DSI TE polling is not supported on this HW\n");
-				goto dsi_link_error;
-			}
-
 			/* Enable DSI TE polling */
 			dsi_te_poll_req(chnl);
 
@@ -1255,15 +1096,7 @@ static int update_channel_static_registers(struct mcde_chnl_state *chnl)
 			dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, true);
 		}
 
-		if (hardware_version == MCDE_CHIP_VERSION_3_0_5) {
-			if (port->phy.dsi.data_lanes_swap) {
-				dev_warn(&mcde_dev->dev,
-				"DSI %d data lane remap not available!\n",
-				lnk);
-				goto dsi_link_error;
-			}
-		} else
-			dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, DLX_REMAP_EN,
+		dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, DLX_REMAP_EN,
 					port->phy.dsi.data_lanes_swap);
 
 		dsi_wreg(lnk, DSI_MCTL_DPHY_STATIC,
@@ -2403,8 +2236,6 @@ static struct mcde_chnl_state *_mcde_chnl_get(enum mcde_chnl chnl_id,
 {
 	int i;
 	struct mcde_chnl_state *chnl = NULL;
-	enum mcde_chnl_path path;
-	const struct chnl_config *cfg = NULL;
 
 	static struct mcde_col_transform ycbcr_2_rgb = {
 		/* Note that in MCDE YUV 422 pixels come as VYU pixels */
@@ -2439,26 +2270,6 @@ static struct mcde_chnl_state *_mcde_chnl_get(enum mcde_chnl chnl_id,
 		return ERR_PTR(-EBUSY);
 	}
 
-	if (hardware_version == MCDE_CHIP_VERSION_3_0_5) {
-		path = MCDE_CHNLPATH(chnl->id, fifo, port->type,
-						port->ifc, port->link);
-		for (i = 0; i < ARRAY_SIZE(chnl_configs); i++)
-			if (chnl_configs[i].path == path) {
-				cfg = &chnl_configs[i];
-				break;
-			}
-		if (cfg == NULL) {
-			dev_dbg(&mcde_dev->dev, "Invalid config, chnl=%d,"
-					" path=0x%.8X\n", chnl_id, path);
-			return ERR_PTR(-EINVAL);
-		} else {
-			dev_info(&mcde_dev->dev, "Config, chnl=%d,"
-					" path=0x%.8X\n", chnl_id, path);
-		}
-	}
-	/* TODO: verify that cfg is ok to activate (check other chnl cfgs) */
-
-	chnl->cfg = cfg;
 	chnl->port = *port;
 	chnl->fifo = fifo;
 	chnl->formatter_updated = false;
@@ -3231,7 +3042,8 @@ static void remove_clocks_and_power(struct platform_device *pdev)
 	regulator_put(regulator_mcde_epod);
 	regulator_put(regulator_esram_epod);
 }
-static void probe_hw(void)
+
+static int probe_hw(void)
 {
 	int i;
 	u8 major_version;
@@ -3260,8 +3072,8 @@ static void probe_hw(void)
 		dev_info(&mcde_dev->dev, "V2 HW\n");
 	} else if (major_version == 3 && minor_version == 0 &&
 					development_version >= 5) {
-		hardware_version = MCDE_CHIP_VERSION_3_0_5;
 		dev_info(&mcde_dev->dev, "V1 HW\n");
+		return -ENOTSUPP;
 	} else if (major_version == 1 && minor_version == 0 &&
 					development_version >= 4) {
 		hardware_version = MCDE_CHIP_VERSION_1_0_4;
@@ -3275,6 +3087,7 @@ static void probe_hw(void)
 		dev_info(&mcde_dev->dev, "V2_U5500 HW\n");
 	} else {
 		dev_err(&mcde_dev->dev, "Unsupported HW version\n");
+		return -ENOTSUPP;
 	}
 
 	/* Init MCDE */
@@ -3318,6 +3131,7 @@ static void probe_hw(void)
 		if (channels[i].ovly1)
 			mcde_debugfs_overlay_create(i, 1);
 	}
+	return 0;
 }
 
 static int __devinit mcde_probe(struct platform_device *pdev)
@@ -3407,7 +3221,9 @@ static int __devinit mcde_probe(struct platform_device *pdev)
 
 	INIT_DELAYED_WORK_DEFERRABLE(&hw_timeout_work, work_sleep_function);
 
-	probe_hw();
+	ret = probe_hw();
+	if (ret)
+		goto failed_probe_hw;
 
 	ret = enable_mcde_hw();
 	if (ret)
@@ -3415,6 +3231,8 @@ static int __devinit mcde_probe(struct platform_device *pdev)
 
 	return 0;
 failed_mcde_enable:
+failed_probe_hw:
+	remove_clocks_and_power(pdev);
 failed_init_clocks:
 failed_map_dsi_io:
 failed_get_dsi_io:
diff --git a/drivers/video/mcde/mcde_regs.h b/drivers/video/mcde/mcde_regs.h
index 7f28c26360b..06e96e45952 100644
--- a/drivers/video/mcde/mcde_regs.h
+++ b/drivers/video/mcde/mcde_regs.h
@@ -5,14 +5,6 @@
 	(((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT)
 
 #define MCDE_CR 0x00000000
-#define MCDE_CR_DSICMD2_EN_V1_SHIFT 0
-#define MCDE_CR_DSICMD2_EN_V1_MASK 0x00000001
-#define MCDE_CR_DSICMD2_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSICMD2_EN_V1, __x)
-#define MCDE_CR_DSICMD1_EN_V1_SHIFT 1
-#define MCDE_CR_DSICMD1_EN_V1_MASK 0x00000002
-#define MCDE_CR_DSICMD1_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSICMD1_EN_V1, __x)
 #define MCDE_CR_DSI0_EN_V3_SHIFT 0
 #define MCDE_CR_DSI0_EN_V3_MASK 0x00000001
 #define MCDE_CR_DSI0_EN_V3(__x) \
@@ -21,42 +13,10 @@
 #define MCDE_CR_DSI1_EN_V3_MASK 0x00000002
 #define MCDE_CR_DSI1_EN_V3(__x) \
 	MCDE_VAL2REG(MCDE_CR, DSI1_EN_V3, __x)
-#define MCDE_CR_DSICMD0_EN_V1_SHIFT 2
-#define MCDE_CR_DSICMD0_EN_V1_MASK 0x00000004
-#define MCDE_CR_DSICMD0_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSICMD0_EN_V1, __x)
-#define MCDE_CR_DSIVID2_EN_V1_SHIFT 3
-#define MCDE_CR_DSIVID2_EN_V1_MASK 0x00000008
-#define MCDE_CR_DSIVID2_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSIVID2_EN_V1, __x)
-#define MCDE_CR_DSIVID1_EN_V1_SHIFT 4
-#define MCDE_CR_DSIVID1_EN_V1_MASK 0x00000010
-#define MCDE_CR_DSIVID1_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSIVID1_EN_V1, __x)
-#define MCDE_CR_DSIVID0_EN_V1_SHIFT 5
-#define MCDE_CR_DSIVID0_EN_V1_MASK 0x00000020
-#define MCDE_CR_DSIVID0_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DSIVID0_EN_V1, __x)
-#define MCDE_CR_DBIC1_EN_V1_SHIFT 6
-#define MCDE_CR_DBIC1_EN_V1_MASK 0x00000040
-#define MCDE_CR_DBIC1_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DBIC1_EN_V1, __x)
-#define MCDE_CR_DBIC0_EN_V1_SHIFT 7
-#define MCDE_CR_DBIC0_EN_V1_MASK 0x00000080
-#define MCDE_CR_DBIC0_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DBIC0_EN_V1, __x)
 #define MCDE_CR_DBI_EN_V3_SHIFT 7
 #define MCDE_CR_DBI_EN_V3_MASK 0x00000080
 #define MCDE_CR_DBI_EN_V3(__x) \
 	MCDE_VAL2REG(MCDE_CR, DBI_EN_V3, __x)
-#define MCDE_CR_DPIB_EN_V1_SHIFT 8
-#define MCDE_CR_DPIB_EN_V1_MASK 0x00000100
-#define MCDE_CR_DPIB_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DPIB_EN_V1, __x)
-#define MCDE_CR_DPIA_EN_V1_SHIFT 9
-#define MCDE_CR_DPIA_EN_V1_MASK 0x00000200
-#define MCDE_CR_DPIA_EN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, DPIA_EN_V1, __x)
 #define MCDE_CR_DPI_EN_V3_SHIFT 9
 #define MCDE_CR_DPI_EN_V3_MASK 0x00000200
 #define MCDE_CR_DPI_EN_V3(__x) \
@@ -65,14 +25,6 @@
 #define MCDE_CR_IFIFOCTRLEN_MASK 0x00008000
 #define MCDE_CR_IFIFOCTRLEN(__x) \
 	MCDE_VAL2REG(MCDE_CR, IFIFOCTRLEN, __x)
-#define MCDE_CR_F01MUX_V1_SHIFT 16
-#define MCDE_CR_F01MUX_V1_MASK 0x00010000
-#define MCDE_CR_F01MUX_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, F01MUX_V1, __x)
-#define MCDE_CR_FABMUX_V1_SHIFT 17
-#define MCDE_CR_FABMUX_V1_MASK 0x00020000
-#define MCDE_CR_FABMUX_V1(__x) \
-	MCDE_VAL2REG(MCDE_CR, FABMUX_V1, __x)
 #define MCDE_CR_AUTOCLKG_EN_SHIFT 30
 #define MCDE_CR_AUTOCLKG_EN_MASK 0x40000000
 #define MCDE_CR_AUTOCLKG_EN(__x) \
@@ -114,22 +66,6 @@
 #define MCDE_CONF0_SYNCMUX7_MASK 0x00000080
 #define MCDE_CONF0_SYNCMUX7(__x) \
 	MCDE_VAL2REG(MCDE_CONF0, SYNCMUX7, __x)
-#define MCDE_CONF0_SWAP_A_C0_V1_SHIFT 8
-#define MCDE_CONF0_SWAP_A_C0_V1_MASK 0x00000100
-#define MCDE_CONF0_SWAP_A_C0_V1(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, SWAP_A_C0_V1, __x)
-#define MCDE_CONF0_SWAP_B_C1_V1_SHIFT 9
-#define MCDE_CONF0_SWAP_B_C1_V1_MASK 0x00000200
-#define MCDE_CONF0_SWAP_B_C1_V1(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, SWAP_B_C1_V1, __x)
-#define MCDE_CONF0_FSYNCTRLA_V1_SHIFT 10
-#define MCDE_CONF0_FSYNCTRLA_V1_MASK 0x00000400
-#define MCDE_CONF0_FSYNCTRLA_V1(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLA_V1, __x)
-#define MCDE_CONF0_FSYNCTRLB_V1_SHIFT 11
-#define MCDE_CONF0_FSYNCTRLB_V1_MASK 0x00000800
-#define MCDE_CONF0_FSYNCTRLB_V1(__x) \
-	MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLB_V1, __x)
 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL(__x) \
@@ -2703,76 +2639,51 @@
 #define MCDE_CHNL3BCKGNDCOL_R_MASK 0x00FF0000
 #define MCDE_CHNL3BCKGNDCOL_R(__x) \
 	MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, R, __x)
-#define MCDE_CHNL0PRIO_V1 0x00000614
-#define MCDE_CHNL0PRIO_V1_GROUPOFFSET 0x20
-#define MCDE_CHNL0PRIO_V1_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL0PRIO_V1_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL0PRIO_V1_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL0PRIO_V1, CHNLPRIO, __x)
-#define MCDE_CHNL1PRIO_V1 0x00000634
-#define MCDE_CHNL1PRIO_V1_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL1PRIO_V1_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL1PRIO_V1_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL1PRIO_V1, CHNLPRIO, __x)
-#define MCDE_CHNL2PRIO_V1 0x00000654
-#define MCDE_CHNL2PRIO_V1_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL2PRIO_V1_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL2PRIO_V1_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL2PRIO_V1, CHNLPRIO, __x)
-#define MCDE_CHNL3PRIO_V1 0x00000674
-#define MCDE_CHNL3PRIO_V1_CHNLPRIO_SHIFT 0
-#define MCDE_CHNL3PRIO_V1_CHNLPRIO_MASK 0x0000000F
-#define MCDE_CHNL3PRIO_V1_CHNLPRIO(__x) \
-	MCDE_VAL2REG(MCDE_CHNL3PRIO_V1, CHNLPRIO, __x)
-#define MCDE_CHNL0MUXING_V2 0x00000614
-#define MCDE_CHNL0MUXING_V2_GROUPOFFSET 0x20
-#define MCDE_CHNL0MUXING_V2_FIFO_ID_SHIFT 0
-#define MCDE_CHNL0MUXING_V2_FIFO_ID_MASK 0x00000007
-#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_A 0
-#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_B 1
-#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_C0 2
-#define MCDE_CHNL0MUXING_V2_FIFO_ID_FIFO_C1 3
-#define MCDE_CHNL0MUXING_V2_FIFO_ID_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CHNL0MUXING_V2, FIFO_ID, \
-	MCDE_CHNL0MUXING_V2_FIFO_ID_##__x)
-#define MCDE_CHNL0MUXING_V2_FIFO_ID(__x) \
-	MCDE_VAL2REG(MCDE_CHNL0MUXING_V2, FIFO_ID, __x)
-#define MCDE_CHNL1MUXING_V2 0x00000634
-#define MCDE_CHNL1MUXING_V2_FIFO_ID_SHIFT 0
-#define MCDE_CHNL1MUXING_V2_FIFO_ID_MASK 0x00000007
-#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_A 0
-#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_B 1
-#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_C0 2
-#define MCDE_CHNL1MUXING_V2_FIFO_ID_FIFO_C1 3
-#define MCDE_CHNL1MUXING_V2_FIFO_ID_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CHNL1MUXING_V2, FIFO_ID, \
-	MCDE_CHNL1MUXING_V2_FIFO_ID_##__x)
-#define MCDE_CHNL1MUXING_V2_FIFO_ID(__x) \
-	MCDE_VAL2REG(MCDE_CHNL1MUXING_V2, FIFO_ID, __x)
-#define MCDE_CHNL2MUXING_V2 0x00000654
-#define MCDE_CHNL2MUXING_V2_FIFO_ID_SHIFT 0
-#define MCDE_CHNL2MUXING_V2_FIFO_ID_MASK 0x00000007
-#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_A 0
-#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_B 1
-#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_C0 2
-#define MCDE_CHNL2MUXING_V2_FIFO_ID_FIFO_C1 3
-#define MCDE_CHNL2MUXING_V2_FIFO_ID_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CHNL2MUXING_V2, FIFO_ID, \
-	MCDE_CHNL2MUXING_V2_FIFO_ID_##__x)
-#define MCDE_CHNL2MUXING_V2_FIFO_ID(__x) \
-	MCDE_VAL2REG(MCDE_CHNL2MUXING_V2, FIFO_ID, __x)
-#define MCDE_CHNL3MUXING_V2 0x00000674
-#define MCDE_CHNL3MUXING_V2_FIFO_ID_SHIFT 0
-#define MCDE_CHNL3MUXING_V2_FIFO_ID_MASK 0x00000007
-#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_A 0
-#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_B 1
-#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_C0 2
-#define MCDE_CHNL3MUXING_V2_FIFO_ID_FIFO_C1 3
-#define MCDE_CHNL3MUXING_V2_FIFO_ID_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CHNL3MUXING_V2, FIFO_ID, \
-	MCDE_CHNL3MUXING_V2_FIFO_ID_##__x)
-#define MCDE_CHNL3MUXING_V2_FIFO_ID(__x) \
-	MCDE_VAL2REG(MCDE_CHNL3MUXING_V2, FIFO_ID, __x)
+#define MCDE_CHNL0MUXING 0x00000614
+#define MCDE_CHNL0MUXING_GROUPOFFSET 0x20
+#define MCDE_CHNL0MUXING_FIFO_ID_SHIFT 0
+#define MCDE_CHNL0MUXING_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL0MUXING_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL0MUXING_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL0MUXING, FIFO_ID, MCDE_CHNL0MUXING_FIFO_ID_##__x)
+#define MCDE_CHNL0MUXING_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL0MUXING, FIFO_ID, __x)
+#define MCDE_CHNL1MUXING 0x00000634
+#define MCDE_CHNL1MUXING_FIFO_ID_SHIFT 0
+#define MCDE_CHNL1MUXING_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL1MUXING_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL1MUXING_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL1MUXING, FIFO_ID, MCDE_CHNL1MUXING_FIFO_ID_##__x)
+#define MCDE_CHNL1MUXING_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL1MUXING, FIFO_ID, __x)
+#define MCDE_CHNL2MUXING 0x00000654
+#define MCDE_CHNL2MUXING_FIFO_ID_SHIFT 0
+#define MCDE_CHNL2MUXING_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL2MUXING_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL2MUXING_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL2MUXING, FIFO_ID, MCDE_CHNL2MUXING_FIFO_ID_##__x)
+#define MCDE_CHNL2MUXING_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL2MUXING, FIFO_ID, __x)
+#define MCDE_CHNL3MUXING 0x00000674
+#define MCDE_CHNL3MUXING_FIFO_ID_SHIFT 0
+#define MCDE_CHNL3MUXING_FIFO_ID_MASK 0x00000007
+#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_A 0
+#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_B 1
+#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_C0 2
+#define MCDE_CHNL3MUXING_FIFO_ID_FIFO_C1 3
+#define MCDE_CHNL3MUXING_FIFO_ID_ENUM(__x) \
+	MCDE_VAL2REG(MCDE_CHNL3MUXING, FIFO_ID, MCDE_CHNL3MUXING_FIFO_ID_##__x)
+#define MCDE_CHNL3MUXING_FIFO_ID(__x) \
+	MCDE_VAL2REG(MCDE_CHNL3MUXING, FIFO_ID, __x)
 #define MCDE_CRA0 0x00000800
 #define MCDE_CRA0_GROUPOFFSET 0x200
 #define MCDE_CRA0_FLOEN_SHIFT 0
@@ -2857,22 +2768,6 @@
 #define MCDE_CRA0_ROTEN_MASK 0x01000000
 #define MCDE_CRA0_ROTEN(__x) \
 	MCDE_VAL2REG(MCDE_CRA0, ROTEN, __x)
-#define MCDE_CRA0_ROTBURSTSIZE_V1_SHIFT 25
-#define MCDE_CRA0_ROTBURSTSIZE_V1_MASK 0x0E000000
-#define MCDE_CRA0_ROTBURSTSIZE_V1_1W 0
-#define MCDE_CRA0_ROTBURSTSIZE_V1_2W 1
-#define MCDE_CRA0_ROTBURSTSIZE_V1_4W 2
-#define MCDE_CRA0_ROTBURSTSIZE_V1_8W 3
-#define MCDE_CRA0_ROTBURSTSIZE_V1_16W 4
-#define MCDE_CRA0_ROTBURSTSIZE_V1_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_V1, \
-	MCDE_CRA0_ROTBURSTSIZE_V1_##__x)
-#define MCDE_CRA0_ROTBURSTSIZE_V1(__x) \
-	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_V1, __x)
-#define MCDE_CRA0_ROTBURSTSIZE_HW_V1_SHIFT 28
-#define MCDE_CRA0_ROTBURSTSIZE_HW_V1_MASK 0x10000000
-#define MCDE_CRA0_ROTBURSTSIZE_HW_V1(__x) \
-	MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_HW_V1, __x)
 #define MCDE_CRB0 0x00000A00
 #define MCDE_CRB0_FLOEN_SHIFT 0
 #define MCDE_CRB0_FLOEN_MASK 0x00000001
@@ -2956,22 +2851,6 @@
 #define MCDE_CRB0_ROTEN_MASK 0x01000000
 #define MCDE_CRB0_ROTEN(__x) \
 	MCDE_VAL2REG(MCDE_CRB0, ROTEN, __x)
-#define MCDE_CRB0_ROTBURSTSIZE_V1_SHIFT 25
-#define MCDE_CRB0_ROTBURSTSIZE_V1_MASK 0x0E000000
-#define MCDE_CRB0_ROTBURSTSIZE_V1_1W 0
-#define MCDE_CRB0_ROTBURSTSIZE_V1_2W 1
-#define MCDE_CRB0_ROTBURSTSIZE_V1_4W 2
-#define MCDE_CRB0_ROTBURSTSIZE_V1_8W 3
-#define MCDE_CRB0_ROTBURSTSIZE_V1_16W 4
-#define MCDE_CRB0_ROTBURSTSIZE_V1_ENUM(__x) \
-	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_V1, \
-	MCDE_CRB0_ROTBURSTSIZE_V1_##__x)
-#define MCDE_CRB0_ROTBURSTSIZE_V1(__x) \
-	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_V1, __x)
-#define MCDE_CRB0_ROTBURSTSIZE_HW_V1_SHIFT 28
-#define MCDE_CRB0_ROTBURSTSIZE_HW_V1_MASK 0x10000000
-#define MCDE_CRB0_ROTBURSTSIZE_HW_V1(__x) \
-	MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_HW_V1, __x)
 #define MCDE_CRA1 0x00000804
 #define MCDE_CRA1_GROUPOFFSET 0x200
 #define MCDE_CRA1_PCD_SHIFT 0
@@ -3033,10 +2912,6 @@
 	MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, MCDE_CRA1_CLKTYPE_##__x)
 #define MCDE_CRA1_CLKTYPE(__x) \
 	MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, __x)
-#define MCDE_CRA1_TEFFECTEN_V1_SHIFT 31
-#define MCDE_CRA1_TEFFECTEN_V1_MASK 0x80000000
-#define MCDE_CRA1_TEFFECTEN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CRA1, TEFFECTEN_V1, __x)
 #define MCDE_CRB1 0x00000A04
 #define MCDE_CRB1_PCD_SHIFT 0
 #define MCDE_CRB1_PCD_MASK 0x000003FF
@@ -3097,10 +2972,6 @@
 	MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, MCDE_CRB1_CLKTYPE_##__x)
 #define MCDE_CRB1_CLKTYPE(__x) \
 	MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, __x)
-#define MCDE_CRB1_TEFFECTEN_V1_SHIFT 31
-#define MCDE_CRB1_TEFFECTEN_V1_MASK 0x80000000
-#define MCDE_CRB1_TEFFECTEN_V1(__x) \
-	MCDE_VAL2REG(MCDE_CRB1, TEFFECTEN_V1, __x)
 #define MCDE_COLKEYA 0x00000808
 #define MCDE_COLKEYA_GROUPOFFSET 0x200
 #define MCDE_COLKEYA_KEYB_SHIFT 0
@@ -3336,25 +3207,25 @@
 #define MCDE_FFCOEF2_T2_MASK 0x0F000000
 #define MCDE_FFCOEF2_T2(__x) \
 	MCDE_VAL2REG(MCDE_FFCOEF2, T2, __x)
-#define MCDE_MCDE_WDATAA_V2 0x00000834
-#define MCDE_MCDE_WDATAA_V2_GROUPOFFSET 0x200
-#define MCDE_MCDE_WDATAA_V2_DC_SHIFT 24
-#define MCDE_MCDE_WDATAA_V2_DC_MASK 0x01000000
-#define MCDE_MCDE_WDATAA_V2_DC(__x) \
-	MCDE_VAL2REG(MCDE_MCDE_WDATAA_V2, DC, __x)
-#define MCDE_MCDE_WDATAA_V2_DATAVALUE_SHIFT 0
-#define MCDE_MCDE_WDATAA_V2_DATAVALUE_MASK 0x00FFFFFF
-#define MCDE_MCDE_WDATAA_V2_DATAVALUE(__x) \
-	MCDE_VAL2REG(MCDE_MCDE_WDATAA_V2, DATAVALUE, __x)
-#define MCDE_MCDE_WDATAB_V2 0x00000A34
-#define MCDE_MCDE_WDATAB_V2_DC_SHIFT 24
-#define MCDE_MCDE_WDATAB_V2_DC_MASK 0x01000000
-#define MCDE_MCDE_WDATAB_V2_DC(__x) \
-	MCDE_VAL2REG(MCDE_MCDE_WDATAB_V2, DC, __x)
-#define MCDE_MCDE_WDATAB_V2_DATAVALUE_SHIFT 0
-#define MCDE_MCDE_WDATAB_V2_DATAVALUE_MASK 0x00FFFFFF
-#define MCDE_MCDE_WDATAB_V2_DATAVALUE(__x) \
-	MCDE_VAL2REG(MCDE_MCDE_WDATAB_V2, DATAVALUE, __x)
+#define MCDE_MCDE_WDATAA 0x00000834
+#define MCDE_MCDE_WDATAA_GROUPOFFSET 0x200
+#define MCDE_MCDE_WDATAA_DC_SHIFT 24
+#define MCDE_MCDE_WDATAA_DC_MASK 0x01000000
+#define MCDE_MCDE_WDATAA_DC(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAA, DC, __x)
+#define MCDE_MCDE_WDATAA_DATAVALUE_SHIFT 0
+#define MCDE_MCDE_WDATAA_DATAVALUE_MASK 0x00FFFFFF
+#define MCDE_MCDE_WDATAA_DATAVALUE(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAA, DATAVALUE, __x)
+#define MCDE_MCDE_WDATAB 0x00000A34
+#define MCDE_MCDE_WDATAB_DC_SHIFT 24
+#define MCDE_MCDE_WDATAB_DC_MASK 0x01000000
+#define MCDE_MCDE_WDATAB_DC(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAB, DC, __x)
+#define MCDE_MCDE_WDATAB_DATAVALUE_SHIFT 0
+#define MCDE_MCDE_WDATAB_DATAVALUE_MASK 0x00FFFFFF
+#define MCDE_MCDE_WDATAB_DATAVALUE(__x) \
+	MCDE_VAL2REG(MCDE_MCDE_WDATAB, DATAVALUE, __x)
 #define MCDE_TVCRA 0x00000838
 #define MCDE_TVCRA_GROUPOFFSET 0x200
 #define MCDE_TVCRA_SEL_MOD_SHIFT 0
@@ -4651,17 +4522,6 @@
 #define MCDE_DOTR1_DODEACT_MASK 0x0000FF00
 #define MCDE_DOTR1_DODEACT(__x) \
 	MCDE_VAL2REG(MCDE_DOTR1, DODEACT, __x)
-#define MCDE_WCMDC0_V1 0x00000C8C
-#define MCDE_WCMDC0_V1_GROUPOFFSET 0x4
-#define MCDE_WCMDC0_V1_COMMANDVALUE_SHIFT 0
-#define MCDE_WCMDC0_V1_COMMANDVALUE_MASK 0x00FFFFFF
-#define MCDE_WCMDC0_V1_COMMANDVALUE(__x) \
-	MCDE_VAL2REG(MCDE_WCMDC0_V1, COMMANDVALUE, __x)
-#define MCDE_WCMDC1_V1 0x00000C90
-#define MCDE_WCMDC1_V1_COMMANDVALUE_SHIFT 0
-#define MCDE_WCMDC1_V1_COMMANDVALUE_MASK 0x00FFFFFF
-#define MCDE_WCMDC1_V1_COMMANDVALUE(__x) \
-	MCDE_VAL2REG(MCDE_WCMDC1_V1, COMMANDVALUE, __x)
 #define MCDE_WDATADC0 0x00000C94
 #define MCDE_WDATADC0_GROUPOFFSET 0x4
 #define MCDE_WDATADC0_DATAVALUE_SHIFT 0
@@ -4692,47 +4552,6 @@
 #define MCDE_RDATADC1_STARTREAD_MASK 0x00010000
 #define MCDE_RDATADC1_STARTREAD(__x) \
 	MCDE_VAL2REG(MCDE_RDATADC1, STARTREAD, __x)
-#define MCDE_STATC_V1 0x00000CA4
-#define MCDE_STATC_V1_STATBUSY0_SHIFT 0
-#define MCDE_STATC_V1_STATBUSY0_MASK 0x00000001
-#define MCDE_STATC_V1_STATBUSY0(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, STATBUSY0, __x)
-#define MCDE_STATC_V1_FIFOEMPTY0_SHIFT 1
-#define MCDE_STATC_V1_FIFOEMPTY0_MASK 0x00000002
-#define MCDE_STATC_V1_FIFOEMPTY0(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOEMPTY0, __x)
-#define MCDE_STATC_V1_FIFOFULL0_SHIFT 2
-#define MCDE_STATC_V1_FIFOFULL0_MASK 0x00000004
-#define MCDE_STATC_V1_FIFOFULL0(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOFULL0, __x)
-#define MCDE_STATC_V1_FIFOCMDEMPTY0_SHIFT 3
-#define MCDE_STATC_V1_FIFOCMDEMPTY0_MASK 0x00000008
-#define MCDE_STATC_V1_FIFOCMDEMPTY0(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDEMPTY0, __x)
-#define MCDE_STATC_V1_FIFOCMDFULL0_SHIFT 4
-#define MCDE_STATC_V1_FIFOCMDFULL0_MASK 0x00000010
-#define MCDE_STATC_V1_FIFOCMDFULL0(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDFULL0, __x)
-#define MCDE_STATC_V1_STATBUSY1_SHIFT 5
-#define MCDE_STATC_V1_STATBUSY1_MASK 0x00000020
-#define MCDE_STATC_V1_STATBUSY1(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, STATBUSY1, __x)
-#define MCDE_STATC_V1_FIFOEMPTY1_SHIFT 6
-#define MCDE_STATC_V1_FIFOEMPTY1_MASK 0x00000040
-#define MCDE_STATC_V1_FIFOEMPTY1(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOEMPTY1, __x)
-#define MCDE_STATC_V1_FIFOFULL1_SHIFT 7
-#define MCDE_STATC_V1_FIFOFULL1_MASK 0x00000080
-#define MCDE_STATC_V1_FIFOFULL1(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOFULL1, __x)
-#define MCDE_STATC_V1_FIFOCMDEMPTY1_SHIFT 8
-#define MCDE_STATC_V1_FIFOCMDEMPTY1_MASK 0x00000100
-#define MCDE_STATC_V1_FIFOCMDEMPTY1(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDEMPTY1, __x)
-#define MCDE_STATC_V1_FIFOCMDFULL1_SHIFT 9
-#define MCDE_STATC_V1_FIFOCMDFULL1_MASK 0x00000200
-#define MCDE_STATC_V1_FIFOCMDFULL1(__x) \
-	MCDE_VAL2REG(MCDE_STATC_V1, FIFOCMDFULL1, __x)
 #define MCDE_CTRLC0 0x00000CA8
 #define MCDE_CTRLC0_GROUPOFFSET 0x4
 #define MCDE_CTRLC0_FIFOWTRMRK_SHIFT 0
diff --git a/include/video/mcde.h b/include/video/mcde.h
index b81d88af5fd..8e4a86a205a 100644
--- a/include/video/mcde.h
+++ b/include/video/mcde.h
@@ -39,69 +39,6 @@ enum mcde_chnl {
 	MCDE_CHNL_C1 = 3,
 };
 
-/* Channel path */
-#define MCDE_CHNLPATH(__chnl, __fifo, __type, __ifc, __link) \
-	(((__chnl) << 16) | ((__fifo) << 12) | \
-	 ((__type) << 8) | ((__ifc) << 4) | ((__link) << 0))
-enum mcde_chnl_path {
-	/* Channel A */
-	MCDE_CHNLPATH_CHNLA_FIFOA_DPI_0 = MCDE_CHNLPATH(MCDE_CHNL_A,
-		MCDE_FIFO_A, MCDE_PORTTYPE_DPI, 0, 0),
-	MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_A,
-		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 0),
-	MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_A,
-		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 1),
-	MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_A,
-		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 0, 2),
-	MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_A,
-		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 0),
-	MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_A,
-		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 1),
-	MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_A,
-		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 1, 2),
-	/* Channel B */
-	MCDE_CHNLPATH_CHNLB_FIFOB_DPI_1 = MCDE_CHNLPATH(MCDE_CHNL_B,
-		MCDE_FIFO_B, MCDE_PORTTYPE_DPI, 0, 1),
-	MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_B,
-		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 0),
-	MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_B,
-		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 1),
-	MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_B,
-		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 0, 2),
-	MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_B,
-		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 0),
-	MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_B,
-		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 1),
-	MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_B,
-		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 1, 2),
-	/* Channel C0 */
-	MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_C0,
-		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 0),
-	MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_C0,
-		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 0, 1),
-	MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_C0,
-		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 0, 2),
-	MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_C0,
-		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 0),
-	MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_C0,
-		MCDE_FIFO_C0, MCDE_PORTTYPE_DSI, 1, 1),
-	MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_C0,
-		MCDE_FIFO_A, MCDE_PORTTYPE_DSI, 1, 2),
-	/* Channel C1 */
-	MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_0 = MCDE_CHNLPATH(MCDE_CHNL_C1,
-		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 0),
-	MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_1 = MCDE_CHNLPATH(MCDE_CHNL_C1,
-		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 0, 1),
-	MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC0_2 = MCDE_CHNLPATH(MCDE_CHNL_C1,
-		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 0, 2),
-	MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_0 = MCDE_CHNLPATH(MCDE_CHNL_C1,
-		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 0),
-	MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_1 = MCDE_CHNLPATH(MCDE_CHNL_C1,
-		MCDE_FIFO_C1, MCDE_PORTTYPE_DSI, 1, 1),
-	MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC1_2 = MCDE_CHNLPATH(MCDE_CHNL_C1,
-		MCDE_FIFO_B, MCDE_PORTTYPE_DSI, 1, 2),
-};
-
 /* Update sync mode */
 enum mcde_sync_src {
 	MCDE_SYNCSRC_OFF = 0, /* No sync */
@@ -235,8 +172,6 @@ enum mcde_display_rotation {
 #define MCDE_INPUT_FIFO_SIZE_3_0_8 128
 
 /* Tv-out defines */
-#define MCDE_CONFIG_TVOUT_HBORDER 2
-#define MCDE_CONFIG_TVOUT_VBORDER 2
 #define MCDE_CONFIG_TVOUT_BACKGROUND_LUMINANCE		0x83
 #define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CB	0x9C
 #define MCDE_CONFIG_TVOUT_BACKGROUND_CHROMINANCE_CR	0x2C
@@ -248,7 +183,6 @@ enum mcde_display_rotation {
 #define MCDE_CHIP_VERSION_4_0_4 4       /* U5500 V2 */
 #define MCDE_CHIP_VERSION_1_0_4 3	/* U5500 V1 */
 #define MCDE_CHIP_VERSION_3_0_8 2	/* U8500 V2 */
-#define MCDE_CHIP_VERSION_3_0_5 1	/* U8500 V1 */
 #define MCDE_CHIP_VERSION_3	0
 
 /* DSI modes */