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| author | Philippe Langlais <philippe.langlais@stericsson.com> | 2012-06-04 19:45:26 +0800 |
|---|---|---|
| committer | Philippe Langlais <philippe.langlais@stericsson.com> | 2012-06-04 19:45:26 +0800 |
| commit | ce8fdbf6b69bcd0c80e9a4558c631c6fdbeedabc (patch) | |
| tree | 1dd31102da7f3c884d54d3ea059f40deff513215 /drivers/mmc/host/mmci.h | |
| parent | 7938fb7c7b5d887cb17915b2fa2923736d9b2467 (diff) | |
| parent | 2a8fe9f1219bffa4c076d33a19a982908480024f (diff) | |
Merge topic branch 'storage-mmc' into integration-linux-ux500
Diffstat (limited to 'drivers/mmc/host/mmci.h')
| -rw-r--r-- | drivers/mmc/host/mmci.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index d437ccf62d6..5a17beafd05 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -60,6 +60,13 @@ #define MCI_ST_DPSM_RWMOD (1 << 10) #define MCI_ST_DPSM_SDIOEN (1 << 11) /* Control register extensions in the ST Micro Ux500 versions */ +/* + * DMA request control is required for write + * if transfer size is not 32 byte aligned. + * DMA request control is also needed if the total + * transfer size is 32 byte aligned but any of the + * sg element lengths are not aligned with 32 byte. + */ #define MCI_ST_DPSM_DMAREQCTL (1 << 12) #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) #define MCI_ST_DPSM_BUSYMODE (1 << 14) @@ -179,8 +186,10 @@ struct mmci_host { unsigned int mclk; unsigned int cclk; + unsigned int cclk_desired; u32 pwr_reg; u32 clk_reg; + u32 datactrl_reg; struct mmci_platform_data *plat; struct variant_data *variant; |