3 files changed, 107 insertions, 22 deletions
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 8bacdcdbc60..a0ac1ec081f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -79,6 +79,7 @@
 #include "pins.h"
 #endif
 
+#include "cpu-db8500.h"
 #include "pins-db8500.h"
 #include "devices-db8500.h"
 #include "board-mop500.h"
@@ -1045,27 +1046,6 @@ static pin_cfg_t mop500_pins_uart0[] = {
 	GPIO3_U0_TXD    | PIN_OUTPUT_HIGH,
 };
 
-#define PRCC_K_SOFTRST_SET      0x18
-#define PRCC_K_SOFTRST_CLEAR    0x1C
-/* pl011 reset */
-static void ux500_uart0_reset(void)
-{
-	void __iomem *prcc_rst_set, *prcc_rst_clr;
-
-	prcc_rst_set = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE +
-			PRCC_K_SOFTRST_SET);
-	prcc_rst_clr = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE +
-			PRCC_K_SOFTRST_CLEAR);
-
-	/* Activate soft reset PRCC_K_SOFTRST_CLEAR */
-	writel((readl(prcc_rst_clr) | 0x1), prcc_rst_clr);
-	udelay(1);
-
-	/* Release soft reset PRCC_K_SOFTRST_SET */
-	writel((readl(prcc_rst_set) | 0x1), prcc_rst_set);
-	udelay(1);
-}
-
 static void ux500_uart0_init(void)
 {
 	int ret;
@@ -1086,7 +1066,23 @@ static void ux500_uart0_exit(void)
 		pr_err("pl011: uart pins_disable failed\n");
 }
 
+static void u8500_uart0_reset(void)
+{
+	/* UART0 lies in PER1 */
+	return u8500_reset_ip(1, PRCC_K_SOFTRST_UART0_MASK);
+}
+
+static void u8500_uart1_reset(void)
+{
+	/* UART1 lies in PER1 */
+	return u8500_reset_ip(1, PRCC_K_SOFTRST_UART1_MASK);
+}
 
+static void u8500_uart2_reset(void)
+{
+	/* UART2 lies in PER3 */
+	return u8500_reset_ip(3, PRCC_K_SOFTRST_UART2_MASK);
+}
 
 static struct amba_pl011_data uart0_plat = {
 #ifdef CONFIG_STE_DMA40_REMOVE
@@ -1096,7 +1092,7 @@ static struct amba_pl011_data uart0_plat = {
 #endif
 	.init = ux500_uart0_init,
 	.exit = ux500_uart0_exit,
-	.reset = ux500_uart0_reset,
+	.reset = u8500_uart0_reset,
 };
 
 static struct amba_pl011_data uart1_plat = {
@@ -1105,6 +1101,7 @@ static struct amba_pl011_data uart1_plat = {
 	.dma_rx_param = &uart1_dma_cfg_rx,
 	.dma_tx_param = &uart1_dma_cfg_tx,
 #endif
+	.reset = u8500_uart1_reset,
 };
 
 static struct amba_pl011_data uart2_plat = {
@@ -1113,6 +1110,7 @@ static struct amba_pl011_data uart2_plat = {
 	.dma_rx_param = &uart2_dma_cfg_rx,
 	.dma_tx_param = &uart2_dma_cfg_tx,
 #endif
+	.reset = u8500_uart2_reset,
 };
 
 static void __init mop500_uart_init(struct device *parent)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 8540f8a6d0c..9f75feb07a2 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
+#include <linux/delay.h>
 
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
@@ -29,6 +30,7 @@
 #include <mach/ste-dma40-db8500.h>
 
 #include "devices-db8500.h"
+#include "prcc.h"
 
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_uart_io_desc[] __initdata = {
@@ -131,6 +133,35 @@ static struct platform_device db8500_prcmu_device = {
 	.name			= "db8500-prcmu",
 };
 
+static unsigned int per_clkrst_base[7] = {
+	0,
+	U8500_CLKRST1_BASE,
+	U8500_CLKRST2_BASE,
+	U8500_CLKRST3_BASE,
+	0,
+	0,
+	U8500_CLKRST6_BASE,
+};
+
+void u8500_reset_ip(unsigned char per, unsigned int ip_mask)
+{
+	void __iomem *prcc_rst_set, *prcc_rst_clr;
+
+	if (per == 0 || per == 4 || per == 5 || per > 6)
+		return;
+
+	prcc_rst_set = __io_address(per_clkrst_base[per] + PRCC_K_SOFTRST_SET);
+	prcc_rst_clr = __io_address(per_clkrst_base[per] + PRCC_K_SOFTRST_CLR);
+
+	/* Activate soft reset PRCC_K_SOFTRST_CLR */
+	writel(ip_mask, prcc_rst_clr);
+	udelay(1);
+
+	/* Release soft reset PRCC_K_SOFTRST_SET */
+	writel(ip_mask, prcc_rst_set);
+	udelay(1);
+}
+
 static struct platform_device *platform_devs[] __initdata = {
 	&u8500_gpio_devs[0],
 	&u8500_gpio_devs[1],
diff --git a/arch/arm/mach-ux500/cpu-db8500.h b/arch/arm/mach-ux500/cpu-db8500.h
new file mode 100644
index 00000000000..0aeefec8613
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-db8500.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2011
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ *
+ * CPU specific routines.
+ *
+ * Author: Shreshtha Kumar SAHU <shreshthakumar.sahu@stericsson.com>
+ */
+
+#ifndef __CPU_DB8500_H__
+#define __CPU_DB8500_H__
+
+/* PER1 IP's softreset masks */
+#define PRCC_K_SOFTRST_UART0_MASK	(1 << 0)
+#define PRCC_K_SOFTRST_UART1_MASK	(1 << 1)
+#define PRCC_K_SOFTRST_I2C1_MASK	(1 << 2)
+#define PRCC_K_SOFTRST_MSP0_MASK	(1 << 3)
+#define PRCC_K_SOFTRST_MSP1_MASK	(1 << 4)
+#define PRCC_K_SOFTRST_SDIO0_MASK	(1 << 5)
+#define PRCC_K_SOFTRST_I2C2_MASK	(1 << 6)
+#define PRCC_K_SOFTRST_SP13_MASK	(1 << 7)
+#define PRCC_K_SOFTRST_SLIMBUS0_MASK	(1 << 8)
+#define PRCC_K_SOFTRST_I2C4_MASK	(1 << 9)
+#define PRCC_K_SOFTRST_MSP3_MASK	(1 << 10)
+#define PRCC_K_SOFTRST_PER_MSP3_MASK	(1 << 11)
+#define PRCC_K_SOFTRST_PER_MSP1_MASK	(1 << 12)
+#define PRCC_K_SOFTRST_PER_MSP0_MASK	(1 << 13)
+#define PRCC_K_SOFTRST_PER_SLIMBUS_MASK	(1 << 14)
+
+/* PER2 IP's softreset masks */
+#define PRCC_K_SOFTRST_I2C3_MASK	(1 << 0)
+#define PRCC_K_SOFTRST_PWL_MASK		(1 << 1)
+#define PRCC_K_SOFTRST_SDI4_MASK	(1 << 2)
+#define PRCC_K_SOFTRST_MSP2_MASK	(1 << 3)
+#define PRCC_K_SOFTRST_SDI1_MASK	(1 << 4)
+#define PRCC_K_SOFTRST_SDI3_MASK	(1 << 5)
+#define PRCC_K_SOFTRST_HSIRX_MASK	(1 << 6)
+#define PRCC_K_SOFTRST_HSITX_MASK	(1 << 7)
+#define PRCC_K_SOFTRST_PER_MSP2_MASK	(1 << 8)
+
+/* PER3 IP's softreset masks */
+#define PRCC_K_SOFTRST_SSP0_MASK	(1 << 1)
+#define PRCC_K_SOFTRST_SSP1_MASK	(1 << 2)
+#define PRCC_K_SOFTRST_I2C0_MASK	(1 << 3)
+#define PRCC_K_SOFTRST_SDI2_MASK	(1 << 4)
+#define PRCC_K_SOFTRST_SKE_MASK		(1 << 5)
+#define PRCC_K_SOFTRST_UART2_MASK	(1 << 6)
+#define PRCC_K_SOFTRST_SDI5_MASK	(1 << 7)
+
+/* PER6 IP's softreset masks */
+#define PRCC_K_SOFTRST_RNG_MASK		(1 << 0)
+
+void u8500_reset_ip(unsigned char per, unsigned int ip_mask);
+
+#endif